irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources
IMX7D contains a new version of GPC IP block (GPCv2). It has two major functions: power management and wakeup source management. When the system is in WFI (wait for interrupt) mode, the GPC block will be the first block on the platform to be activated and signaled. In normal wait mode during cpu idle, the system can be woken up by any enabled interrupts. In standby or suspend mode, the system can only be wokem up by the pre-defined wakeup sources. Based-on-patch-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <shawn.guo@linaro.org> Cc: <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Shenwei Wang
Thomas Gleixner
parent
1a15aaa998
commit
e324c4dc4a
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@ -181,3 +181,9 @@ config RENESAS_H8300H_INTC
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config RENESAS_H8S_INTC
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bool
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select IRQ_DOMAIN
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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@ -54,3 +54,4 @@ obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
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obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
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obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
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obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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@ -0,0 +1,278 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <linux/syscore_ops.h>
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPC_IMR1_CORE0 0x30
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#define GPC_IMR1_CORE1 0x40
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struct gpcv2_irqchip_data {
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struct raw_spinlock rlock;
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void __iomem *gpc_base;
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u32 wakeup_sources[IMR_NUM];
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u32 saved_irq_mask[IMR_NUM];
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u32 cpu2wakeup;
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};
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static struct gpcv2_irqchip_data *imx_gpcv2_instance;
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/*
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* Interface for the low level wakeup code.
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*/
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u32 imx_gpcv2_get_wakeup_source(u32 **sources)
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{
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if (!imx_gpcv2_instance)
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return 0;
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if (sources)
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*sources = imx_gpcv2_instance->wakeup_sources;
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return IMR_NUM;
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}
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static int gpcv2_wakeup_source_save(void)
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{
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struct gpcv2_irqchip_data *cd;
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void __iomem *reg;
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int i;
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cd = imx_gpcv2_instance;
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if (!cd)
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return 0;
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for (i = 0; i < IMR_NUM; i++) {
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reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
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cd->saved_irq_mask[i] = readl_relaxed(reg);
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writel_relaxed(cd->wakeup_sources[i], reg);
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}
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return 0;
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}
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static void gpcv2_wakeup_source_restore(void)
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{
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struct gpcv2_irqchip_data *cd;
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void __iomem *reg;
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int i;
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cd = imx_gpcv2_instance;
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if (!cd)
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return;
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for (i = 0; i < IMR_NUM; i++) {
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reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
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writel_relaxed(cd->saved_irq_mask[i], reg);
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}
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}
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static struct syscore_ops imx_gpcv2_syscore_ops = {
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.suspend = gpcv2_wakeup_source_save,
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.resume = gpcv2_wakeup_source_restore,
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};
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static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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unsigned int idx = d->hwirq / 32;
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unsigned long flags;
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void __iomem *reg;
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u32 mask, val;
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raw_spin_lock_irqsave(&cd->rlock, flags);
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reg = cd->gpc_base + cd->cpu2wakeup + idx * 4;
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mask = 1 << d->hwirq % 32;
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val = cd->wakeup_sources[idx];
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cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
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raw_spin_unlock_irqrestore(&cd->rlock, flags);
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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static void imx_gpcv2_irq_unmask(struct irq_data *d)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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void __iomem *reg;
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u32 val;
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raw_spin_lock(&cd->rlock);
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reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << d->hwirq % 32);
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writel_relaxed(val, reg);
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raw_spin_unlock(&cd->rlock);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpcv2_irq_mask(struct irq_data *d)
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{
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struct gpcv2_irqchip_data *cd = d->chip_data;
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void __iomem *reg;
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u32 val;
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raw_spin_lock(&cd->rlock);
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reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val |= 1 << (d->hwirq % 32);
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writel_relaxed(val, reg);
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raw_spin_unlock(&cd->rlock);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip gpcv2_irqchip_data_chip = {
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.name = "GPCv2",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_gpcv2_irq_mask,
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.irq_unmask = imx_gpcv2_irq_unmask,
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.irq_set_wake = imx_gpcv2_irq_set_wake,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int imx_gpcv2_domain_xlate(struct irq_domain *domain,
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struct device_node *controller,
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const u32 *intspec,
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unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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/* Shouldn't happen, really... */
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if (domain->of_node != controller)
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return -EINVAL;
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/* Not GIC compliant */
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if (intsize != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (intspec[0] != 0)
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return -EINVAL;
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*out_hwirq = intspec[1];
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*out_type = intspec[2];
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return 0;
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}
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static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
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unsigned int irq, unsigned int nr_irqs,
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void *data)
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{
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struct of_phandle_args *args = data;
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struct of_phandle_args parent_args;
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irq_hw_number_t hwirq;
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int i;
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/* Not GIC compliant */
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if (args->args_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (args->args[0] != 0)
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return -EINVAL;
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/* Can't deal with this */
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hwirq = args->args[1];
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if (hwirq >= GPC_MAX_IRQS)
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return -EINVAL;
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for (i = 0; i < nr_irqs; i++) {
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&gpcv2_irqchip_data_chip, domain->host_data);
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}
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parent_args = *args;
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parent_args.np = domain->parent->of_node;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
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}
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static struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
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.xlate = imx_gpcv2_domain_xlate,
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.alloc = imx_gpcv2_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init imx_gpcv2_irqchip_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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struct gpcv2_irqchip_data *cd;
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int i;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to get parent domain\n", node->full_name);
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return -ENXIO;
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}
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cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
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if (!cd) {
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pr_err("kzalloc failed!\n");
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return -ENOMEM;
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}
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cd->gpc_base = of_iomap(node, 0);
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if (!cd->gpc_base) {
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pr_err("fsl-gpcv2: unable to map gpc registers\n");
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kfree(cd);
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return -ENOMEM;
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}
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domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
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node, &gpcv2_irqchip_data_domain_ops, cd);
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if (!domain) {
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iounmap(cd->gpc_base);
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kfree(cd);
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return -ENOMEM;
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}
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irq_set_default_host(domain);
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++) {
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writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
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writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
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cd->wakeup_sources[i] = ~0;
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}
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/* Let CORE0 as the default CPU to wake up by GPC */
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cd->cpu2wakeup = GPC_IMR1_CORE0;
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/*
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* Due to hardware design failure, need to make sure GPR
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* interrupt(#32) is unmasked during RUN mode to avoid entering
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* DSM by mistake.
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*/
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writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
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imx_gpcv2_instance = cd;
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register_syscore_ops(&imx_gpcv2_syscore_ops);
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return 0;
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}
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IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
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