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ARM: imx: irq: fix buggy usage of irq_data irq field 

mach-imx directly references to the irq field in
struct irq_data, and uses this to directly poke hardware register.

But irq is the *virtual* irq number, something that has nothing
to do with the actual HW irq (stored in the hwirq field). And once
we put the stacked domain code in action, the whole thing explodes,
as these two values are *very* different.

Just replacing all instances of irq with hwirq fixes the issue.

Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Marc Zyngier 2014-12-02 16:05:25 +00:00 committed by Olof Johansson
parent 7e8f403fec
commit e2fd06f6be
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/mach-imx/gpc.c
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@ -56,14 +56,14 @@ void imx_gpc_post_resume(void)
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
{
unsigned int idx = d->irq / 32 - 1;
unsigned int idx = d->hwirq / 32 - 1;
u32 mask;
/* Sanity check for SPI irq */
if (d->irq < 32)
if (d->hwirq < 32)
return -EINVAL;
mask = 1 << d->irq % 32;
mask = 1 << d->hwirq % 32;
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
gpc_wake_irqs[idx] & ~mask;
@ -97,12 +97,12 @@ void imx_gpc_irq_unmask(struct irq_data *d)
u32 val;
/* Sanity check for SPI irq */
if (d->irq < 32)
if (d->hwirq < 32)
return;
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val &= ~(1 << d->irq % 32);
val &= ~(1 << d->hwirq % 32);
writel_relaxed(val, reg);
}
@ -112,12 +112,12 @@ void imx_gpc_irq_mask(struct irq_data *d)
u32 val;
/* Sanity check for SPI irq */
if (d->irq < 32)
if (d->hwirq < 32)
return;
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val |= 1 << (d->irq % 32);
val |= 1 << (d->hwirq % 32);
writel_relaxed(val, reg);
}