dt-bindings: PCI: xilinx-cpm: Fix reg property order
All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
This order is also suggested by node name which is pcie@fca10000 which
suggests that cpm_slcr register should be the first.
Driver itself is using devm_platform_ioremap_resource_byname() for both
names that's why there is no functional change even on description which
are using current order.
But still prefer to change order to cover currently used description.
Fixes: e22fadb1d0
("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port")
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220516102217.25960-1-bharat.kumar.gogada@xilinx.com
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@ -18,13 +18,13 @@ properties:
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reg:
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items:
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- description: Configuration space region and bridge registers.
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- description: CPM system level control and status registers.
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- description: Configuration space region and bridge registers.
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reg-names:
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items:
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- const: cfg
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- const: cpm_slcr
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- const: cfg
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interrupts:
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maxItems: 1
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@ -86,9 +86,9 @@ examples:
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ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
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<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
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msi-map = <0x0 &its_gic 0x0 0x10000>;
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reg = <0x6 0x00000000 0x0 0x10000000>,
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<0x0 0xfca10000 0x0 0x1000>;
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reg-names = "cfg", "cpm_slcr";
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reg = <0x0 0xfca10000 0x0 0x1000>,
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<0x6 0x00000000 0x0 0x10000000>;
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reg-names = "cpm_slcr", "cfg";
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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