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riscv: dts: starfive: Add cpu scaling for JH7110 SoC 

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Mason Huo 2023-06-06 18:56:56 +08:00 committed by Conor Dooley
parent 2378341504
commit e2c510d6d6
2 changed files with 49 additions and 0 deletions
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16
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -230,3 +230,19 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&U74_1 {
cpu-supply = <&vdd_cpu>;
};
&U74_2 {
cpu-supply = <&vdd_cpu>;
};
&U74_3 {
cpu-supply = <&vdd_cpu>;
};
&U74_4 {
cpu-supply = <&vdd_cpu>;
};

33
arch/riscv/boot/dts/starfive/jh7110.dtsi
View File

@ -53,6 +53,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -79,6 +82,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -105,6 +111,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -131,6 +140,9 @@
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
operating-points-v2 = <&cpu_opp>;
clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -164,6 +176,27 @@
};
};
cpu_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <800000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <800000>;
};
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
opp-microvolt = <800000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1040000>;
};
};
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";