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Merge branch 'hns3-misc-fixes' 

Salil Mehta says:

====================
Misc. bug fixes & cleanups for HNS3 driver

This patch-set presents some miscellaneous bug fixes and cleanups
for the HNS3 driver.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2018-07-07 11:13:07 +09:00
parent 4fed38cf26 8d40854fc1
commit e2664f97c3
9 changed files with 70 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
View File

@ -239,7 +239,28 @@ static int hns3_nic_set_real_num_queue(struct net_device *netdev)
struct hnae3_handle *h = hns3_get_handle(netdev);
struct hnae3_knic_private_info *kinfo = &h->kinfo;
unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
int ret;
int i, ret;
if (kinfo->num_tc <= 1) {
netdev_reset_tc(netdev);
} else {
ret = netdev_set_num_tc(netdev, kinfo->num_tc);
if (ret) {
netdev_err(netdev,
"netdev_set_num_tc fail, ret=%d!\n", ret);
return ret;
}
for (i = 0; i < HNAE3_MAX_TC; i++) {
if (!kinfo->tc_info[i].enable)
continue;
netdev_set_tc_queue(netdev,
kinfo->tc_info[i].tc,
kinfo->tc_info[i].tqp_count,
kinfo->tc_info[i].tqp_offset);
}
}
ret = netif_set_real_num_tx_queues(netdev, queue_size);
if (ret) {
@ -312,7 +333,9 @@ out_start_err:
static int hns3_nic_net_open(struct net_device *netdev)
{
struct hns3_nic_priv *priv = netdev_priv(netdev);
int ret;
struct hnae3_handle *h = hns3_get_handle(netdev);
struct hnae3_knic_private_info *kinfo;
int i, ret;
netif_carrier_off(netdev);
@ -327,6 +350,12 @@ static int hns3_nic_net_open(struct net_device *netdev)
return ret;
}
kinfo = &h->kinfo;
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
netdev_set_prio_tc_map(netdev, i,
kinfo->prio_tc[i]);
}
priv->ae_handle->last_reset_time = jiffies;
return 0;
}
@ -762,16 +791,14 @@ static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
*/
if (skb_is_gso(skb))
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
} else if (l3.v6->version == 6) {
hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
}
switch (l4_proto) {
case IPPROTO_TCP:
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
hnae3_set_field(*type_cs_vlan_tso,
HNS3_TXD_L4T_M,
HNS3_TXD_L4T_S,
@ -781,12 +808,14 @@ static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
if (hns3_tunnel_csum_bug(skb))
break;
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
hnae3_set_field(*type_cs_vlan_tso,
HNS3_TXD_L4T_M,
HNS3_TXD_L4T_S,
HNS3_L4T_UDP);
break;
case IPPROTO_SCTP:
hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
hnae3_set_field(*type_cs_vlan_tso,
HNS3_TXD_L4T_M,
HNS3_TXD_L4T_S,
@ -1307,7 +1336,6 @@ static int hns3_setup_tc(struct net_device *netdev, void *type_data)
u16 mode = mqprio_qopt->mode;
u8 hw = mqprio_qopt->qopt.hw;
bool if_running;
unsigned int i;
int ret;
if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
@ -1331,24 +1359,6 @@ static int hns3_setup_tc(struct net_device *netdev, void *type_data)
if (ret)
goto out;
if (tc <= 1) {
netdev_reset_tc(netdev);
} else {
ret = netdev_set_num_tc(netdev, tc);
if (ret)
goto out;
for (i = 0; i < HNAE3_MAX_TC; i++) {
if (!kinfo->tc_info[i].enable)
continue;
netdev_set_tc_queue(netdev,
kinfo->tc_info[i].tc,
kinfo->tc_info[i].tqp_count,
kinfo->tc_info[i].tqp_offset);
}
}
ret = hns3_nic_set_real_num_queue(netdev);
out:
@ -3202,7 +3212,6 @@ static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
struct net_device *ndev = kinfo->netdev;
bool if_running;
int ret;
u8 i;
if (tc > HNAE3_MAX_TC)
return -EINVAL;
@ -3212,10 +3221,6 @@ static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
if_running = netif_running(ndev);
ret = netdev_set_num_tc(ndev, tc);
if (ret)
return ret;
if (if_running) {
(void)hns3_nic_net_stop(ndev);
msleep(100);
@ -3226,27 +3231,6 @@ static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
if (ret)
goto err_out;
if (tc <= 1) {
netdev_reset_tc(ndev);
goto out;
}
for (i = 0; i < HNAE3_MAX_TC; i++) {
struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
if (tc_info->enable)
netdev_set_tc_queue(ndev,
tc_info->tc,
tc_info->tqp_count,
tc_info->tqp_offset);
}
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
netdev_set_prio_tc_map(ndev, i,
kinfo->prio_tc[i]);
}
out:
ret = hns3_nic_set_real_num_queue(ndev);
err_out:

2
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
View File

@ -201,7 +201,9 @@ static u32 hns3_lb_check_rx_ring(struct hns3_nic_priv *priv, u32 budget)
rx_group = &ring->tqp_vector->rx_group;
pre_rx_pkt = rx_group->total_packets;
preempt_disable();
hns3_clean_rx_ring(ring, budget, hns3_lb_check_skb_data);
preempt_enable();
rcv_good_pkt_total += (rx_group->total_packets - pre_rx_pkt);
rx_group->total_packets = pre_rx_pkt;

4
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
View File

@ -206,7 +206,8 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
spin_lock_bh(&hw->cmq.csq.lock);
if (num > hclge_ring_space(&hw->cmq.csq)) {
if (num > hclge_ring_space(&hw->cmq.csq) ||
test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
spin_unlock_bh(&hw->cmq.csq.lock);
return -EBUSY;
}
@ -346,6 +347,7 @@ int hclge_cmd_init(struct hclge_dev *hdev)
spin_lock_init(&hdev->hw.cmq.crq.lock);
hclge_cmd_init_regs(&hdev->hw);
clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
if (ret) {

3
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View File

@ -571,7 +571,8 @@ struct hclge_config_auto_neg_cmd {
struct hclge_config_max_frm_size_cmd {
__le16 max_frm_size;
u8 rsv[22];
u8 min_frm_size;
u8 rsv[21];
};
enum hclge_mac_vlan_tbl_opcode {

27
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@ -1834,8 +1834,6 @@ static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
return 0;
}
#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
struct hclge_pkt_buf_alloc *buf_alloc)
{
@ -1863,13 +1861,11 @@ static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
req->tc_wl[j].high =
cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
req->tc_wl[j].high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
HCLGE_RX_PRIV_EN_B);
cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
req->tc_wl[j].low =
cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
req->tc_wl[j].low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
HCLGE_RX_PRIV_EN_B);
cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
}
}
@ -1911,13 +1907,11 @@ static int hclge_common_thrd_config(struct hclge_dev *hdev,
req->com_thrd[j].high =
cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
req->com_thrd[j].high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
HCLGE_RX_PRIV_EN_B);
cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
req->com_thrd[j].low =
cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
req->com_thrd[j].low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
HCLGE_RX_PRIV_EN_B);
cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
}
}
@ -1943,14 +1937,10 @@ static int hclge_common_wl_config(struct hclge_dev *hdev,
req = (struct hclge_rx_com_wl *)desc.data;
req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
req->com_wl.high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
HCLGE_RX_PRIV_EN_B);
req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
req->com_wl.low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
HCLGE_RX_PRIV_EN_B);
req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
@ -2517,12 +2507,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
/* check for vector0 reset event sources */
if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
*clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
return HCLGE_VECTOR0_EVENT_RST;
}
if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
*clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
return HCLGE_VECTOR0_EVENT_RST;
@ -2815,8 +2807,6 @@ static void hclge_clear_reset_cause(struct hclge_dev *hdev)
clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
break;
default:
dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
hdev->reset_type);
break;
}
@ -4997,6 +4987,7 @@ static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
req = (struct hclge_config_max_frm_size_cmd *)desc.data;
req->max_frm_size = cpu_to_le16(max_frm_size);
req->min_frm_size = HCLGE_MAC_MIN_FRAME;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {

1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View File

@ -128,6 +128,7 @@ enum HCLGE_DEV_STATE {
HCLGE_STATE_MBX_SERVICE_SCHED,
HCLGE_STATE_MBX_HANDLING,
HCLGE_STATE_STATISTICS_UPDATING,
HCLGE_STATE_CMD_DISABLE,
HCLGE_STATE_MAX
};

9
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View File

@ -1223,6 +1223,10 @@ static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
tx_en = true;
rx_en = true;
break;
case HCLGE_FC_PFC:
tx_en = false;
rx_en = false;
break;
default:
tx_en = true;
rx_en = true;
@ -1240,8 +1244,9 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev)
if (ret)
return ret;
if (hdev->tm_info.fc_mode != HCLGE_FC_PFC)
return hclge_mac_pause_setup_hw(hdev);
ret = hclge_mac_pause_setup_hw(hdev);
if (ret)
return ret;
/* Only DCB-supported dev supports qset back pressure and pfc cmd */
if (!hnae3_dev_dcb_supported(hdev))

11
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View File

@ -658,8 +658,17 @@ static int hclgevf_unmap_ring_from_vector(
static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
{
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
int vector_id;
hclgevf_free_vector(hdev, vector);
vector_id = hclgevf_get_vector_index(hdev, vector);
if (vector_id < 0) {
dev_err(&handle->pdev->dev,
"hclgevf_put_vector get vector index fail. ret =%d\n",
vector_id);
return vector_id;
}
hclgevf_free_vector(hdev, vector_id);
return 0;
}

3
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
View File

@ -208,7 +208,8 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
/* tail the async message in arq */
msg_q = hdev->arq.msg_q[hdev->arq.tail];
memcpy(&msg_q[0], req->msg, HCLGE_MBX_MAX_ARQ_MSG_SIZE);
memcpy(&msg_q[0], req->msg,
HCLGE_MBX_MAX_ARQ_MSG_SIZE * sizeof(u16));
hclge_mbx_tail_ptr_move_arq(hdev->arq);
hdev->arq.count++;