drm/amdgpu/mes10.1: enable the mes ring during initialization
Enable the mes ring during mes block initialization. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -32,6 +32,8 @@
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MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
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static int mes_v10_1_hw_fini(void *handle);
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#define MES_EOP_SIZE 2048
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static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
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@ -569,6 +571,25 @@ static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev)
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}
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#endif
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static int mes_v10_1_queue_init(struct amdgpu_device *adev)
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{
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int r;
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r = mes_v10_1_mqd_init(&adev->mes.ring);
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if (r)
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return r;
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#if 0
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r = mes_v10_1_kiq_enable_queue(adev);
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if (r)
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return r;
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#else
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mes_v10_1_queue_init_register(&adev->mes.ring);
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#endif
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return 0;
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}
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static int mes_v10_1_ring_init(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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@ -640,6 +661,10 @@ static int mes_v10_1_sw_init(void *handle)
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if (r)
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return r;
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r = mes_v10_1_ring_init(adev);
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if (r)
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return r;
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return 0;
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}
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@ -680,6 +705,12 @@ static int mes_v10_1_hw_init(void *handle)
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mes_v10_1_enable(adev, true);
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r = mes_v10_1_queue_init(adev);
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if (r) {
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mes_v10_1_hw_fini(adev);
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return r;
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}
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return 0;
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}
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