drm/amdgpu: add helper for VM PD/PT allocation parameters v3
Add a helper function to figure them out only once. v2: fix typo with memset v3: rebase on kfd changes (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -467,6 +467,32 @@ error:
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return r;
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}
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/**
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* amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
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*
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* @adev: amdgpu_device pointer
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* @vm: requesting vm
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* @bp: resulting BO allocation parameters
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*/
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static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int level, struct amdgpu_bo_param *bp)
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{
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memset(bp, 0, sizeof(*bp));
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bp->size = amdgpu_vm_bo_size(adev, level);
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bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
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bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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if (vm->use_cpu_for_update)
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bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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else
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bp->flags |= AMDGPU_GEM_CREATE_SHADOW |
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AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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bp->type = ttm_bo_type_kernel;
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if (vm->root.base.bo)
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bp->resv = vm->root.base.bo->tbo.resv;
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}
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/**
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* amdgpu_vm_alloc_levels - allocate the PD/PT levels
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*
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@ -490,8 +516,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
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unsigned level, bool ats)
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{
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unsigned shift = amdgpu_vm_level_shift(adev, level);
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struct amdgpu_bo_param bp;
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unsigned pt_idx, from, to;
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u64 flags;
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int r;
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if (!parent->entries) {
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@ -515,30 +541,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
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saddr = saddr & ((1 << shift) - 1);
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eaddr = eaddr & ((1 << shift) - 1);
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flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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if (vm->root.base.bo->shadow)
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flags |= AMDGPU_GEM_CREATE_SHADOW;
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if (vm->use_cpu_for_update)
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flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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else
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flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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amdgpu_vm_bo_param(adev, vm, level, &bp);
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/* walk over the address space and allocate the page tables */
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for (pt_idx = from; pt_idx <= to; ++pt_idx) {
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struct reservation_object *resv = vm->root.base.bo->tbo.resv;
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struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
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struct amdgpu_bo *pt;
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if (!entry->base.bo) {
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struct amdgpu_bo_param bp;
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memset(&bp, 0, sizeof(bp));
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bp.size = amdgpu_vm_bo_size(adev, level);
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bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp.flags = flags;
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bp.type = ttm_bo_type_kernel;
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bp.resv = resv;
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r = amdgpu_bo_create(adev, &bp, &pt);
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if (r)
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return r;
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@ -2612,8 +2622,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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{
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struct amdgpu_bo_param bp;
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struct amdgpu_bo *root;
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unsigned long size;
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uint64_t flags;
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int r, i;
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vm->va = RB_ROOT_CACHED;
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@ -2651,20 +2659,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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"CPU update of VM recommended only for large BAR system\n");
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vm->last_update = NULL;
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flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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if (vm->use_cpu_for_update)
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flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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else if (vm_context != AMDGPU_VM_CONTEXT_COMPUTE)
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flags |= AMDGPU_GEM_CREATE_SHADOW;
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size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp.flags = flags;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
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r = amdgpu_bo_create(adev, &bp, &root);
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if (r)
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goto error_free_sched_entity;
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