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drm/amd/display: Clean up for DCN1 clock debug logging 

[Why]
To prepare for clock debug logging. With the exception of removing
max_supported_dppclk_khz from logs, there are no functional changes.

[How]
Add clk_bypass struct and clean up buffer logic

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Su Chung <Su.Chung@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fatemeh Darbehani 2018-10-30 11:32:40 -04:00 committed by Alex Deucher
parent e96938a09d
commit e210167522
5 changed files with 32 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
View File

@ -328,12 +328,10 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
*smu_req_cur = smu_req; *smu_req_cur = smu_req;
} }
static const struct clk_mgr_funcs dcn1_funcs = { static const struct clk_mgr_funcs dcn1_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = dcn1_update_clocks .update_clocks = dcn1_update_clocks
}; };
struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx) struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx)
{ {
struct dc_debug_options *debug = &ctx->dc->debug; struct dc_debug_options *debug = &ctx->dc->debug;
@ -373,3 +371,5 @@ struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx)
return &clk_mgr_dce->base; return &clk_mgr_dce->base;
} }

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
View File

@ -28,6 +28,12 @@
#include "../dce/dce_clk_mgr.h" #include "../dce/dce_clk_mgr.h"
struct clk_bypass {
uint32_t dcfclk_bypass;
uint32_t dispclk_pypass;
uint32_t dprefclk_bypass;
};
void dcn1_pplib_apply_display_requirements( void dcn1_pplib_apply_display_requirements(
struct dc *dc, struct dc *dc,
struct dc_state *context); struct dc_state *context);

39
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
View File

@ -44,6 +44,7 @@
#include "dcn10_hubp.h" #include "dcn10_hubp.h"
#include "dcn10_hubbub.h" #include "dcn10_hubbub.h"
#include "dcn10_cm_common.h" #include "dcn10_cm_common.h"
#include "dcn10_clk_mgr.h"
static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...) static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...)
{ {
@ -463,19 +464,22 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize) static unsigned int dcn10_get_clock_states(struct dc *dc, char *pBuf, unsigned int bufSize)
{ {
unsigned int chars_printed = 0; unsigned int chars_printed = 0;
unsigned int remaining_buffer = bufSize;
chars_printed = snprintf_count(pBuf, bufSize, "dcfclk_khz,dcfclk_deep_sleep_khz,dispclk_khz," chars_printed = snprintf_count(pBuf, bufSize, "dcfclk,dcfclk_deep_sleep,dispclk,"
"dppclk_khz,max_supported_dppclk_khz,fclk_khz,socclk_khz\n" "dppclk,fclk,socclk\n"
"%d,%d,%d,%d,%d,%d,%d\n", "%d,%d,%d,%d,%d,%d\n",
dc->current_state->bw.dcn.clk.dcfclk_khz, dc->current_state->bw.dcn.clk.dcfclk_khz,
dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz, dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.clk.dispclk_khz, dc->current_state->bw.dcn.clk.dispclk_khz,
dc->current_state->bw.dcn.clk.dppclk_khz, dc->current_state->bw.dcn.clk.dppclk_khz,
dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,
dc->current_state->bw.dcn.clk.fclk_khz, dc->current_state->bw.dcn.clk.fclk_khz,
dc->current_state->bw.dcn.clk.socclk_khz); dc->current_state->bw.dcn.clk.socclk_khz);
return chars_printed; remaining_buffer -= chars_printed;
pBuf += chars_printed;
return bufSize - remaining_buffer;
} }
static void dcn10_clear_otpc_underflow(struct dc *dc) static void dcn10_clear_otpc_underflow(struct dc *dc)
@ -538,16 +542,16 @@ void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigne
* Bit 0 - 15: Hardware block mask * Bit 0 - 15: Hardware block mask
* Bit 15: 1 = Invariant Only, 0 = All * Bit 15: 1 = Invariant Only, 0 = All
*/ */
const unsigned int DC_HW_STATE_MASK_HUBBUB = 0x1; const unsigned int DC_HW_STATE_MASK_HUBBUB = 0x1;
const unsigned int DC_HW_STATE_MASK_HUBP = 0x2; const unsigned int DC_HW_STATE_MASK_HUBP = 0x2;
const unsigned int DC_HW_STATE_MASK_RQ = 0x4; const unsigned int DC_HW_STATE_MASK_RQ = 0x4;
const unsigned int DC_HW_STATE_MASK_DLG = 0x8; const unsigned int DC_HW_STATE_MASK_DLG = 0x8;
const unsigned int DC_HW_STATE_MASK_TTU = 0x10; const unsigned int DC_HW_STATE_MASK_TTU = 0x10;
const unsigned int DC_HW_STATE_MASK_CM = 0x20; const unsigned int DC_HW_STATE_MASK_CM = 0x20;
const unsigned int DC_HW_STATE_MASK_MPCC = 0x40; const unsigned int DC_HW_STATE_MASK_MPCC = 0x40;
const unsigned int DC_HW_STATE_MASK_OTG = 0x80; const unsigned int DC_HW_STATE_MASK_OTG = 0x80;
const unsigned int DC_HW_STATE_MASK_CLOCKS = 0x100; const unsigned int DC_HW_STATE_MASK_CLOCKS = 0x100;
const unsigned int DC_HW_STATE_INVAR_ONLY = 0x8000; const unsigned int DC_HW_STATE_INVAR_ONLY = 0x8000;
unsigned int chars_printed = 0; unsigned int chars_printed = 0;
unsigned int remaining_buf_size = bufSize; unsigned int remaining_buf_size = bufSize;
@ -603,6 +607,9 @@ void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigne
remaining_buf_size -= chars_printed; remaining_buf_size -= chars_printed;
} }
if ((mask & DC_HW_STATE_MASK_CLOCKS) && remaining_buf_size > 0) if ((mask & DC_HW_STATE_MASK_CLOCKS) && remaining_buf_size > 0) {
chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size); chars_printed = dcn10_get_clock_states(dc, pBuf, remaining_buf_size);
pBuf += chars_printed;
remaining_buf_size -= chars_printed;
}
} }

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -202,7 +202,6 @@ enum dcn10_clk_src_array_id {
#define MMHUB_SR(reg_name)\ #define MMHUB_SR(reg_name)\
.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name mm ## reg_name
/* macros to expend register list macro defined in HW object header file /* macros to expend register list macro defined in HW object header file
* end *********************/ * end *********************/
@ -436,7 +435,6 @@ static const struct dcn_optc_mask tg_mask = {
TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
}; };
static const struct bios_registers bios_regs = { static const struct bios_registers bios_regs = {
NBIO_SR(BIOS_SCRATCH_0), NBIO_SR(BIOS_SCRATCH_0),
NBIO_SR(BIOS_SCRATCH_3), NBIO_SR(BIOS_SCRATCH_3),
@ -497,7 +495,6 @@ static const struct dce110_clk_src_mask cs_mask = {
CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
}; };
static const struct resource_caps res_cap = { static const struct resource_caps res_cap = {
.num_timing_generator = 4, .num_timing_generator = 4,
.num_opp = 4, .num_opp = 4,
@ -1277,7 +1274,6 @@ static bool construct(
goto fail; goto fail;
} }
} }
pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); pool->base.clk_mgr = dcn1_clk_mgr_create(ctx);
if (pool->base.clk_mgr == NULL) { if (pool->base.clk_mgr == NULL) {
dm_error("DC: failed to create display clock!\n"); dm_error("DC: failed to create display clock!\n");

2
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
View File

@ -102,7 +102,7 @@ struct pp_smu_funcs_rv {
*/ */
void (*set_display_count)(struct pp_smu *pp, int count); void (*set_display_count)(struct pp_smu *pp, int count);
/* which SMU message? are reader and writer WM separate SMU msg? */ /* reader and writer WM's are sent together as part of one table*/
/* /*
* PPSMC_MSG_SetDriverDramAddrHigh * PPSMC_MSG_SetDriverDramAddrHigh
* PPSMC_MSG_SetDriverDramAddrLow * PPSMC_MSG_SetDriverDramAddrLow