drm/bridge/sii8620: add support for burst eMSC transmissions
Burst transmissions are used in MHL3 mode negotiation. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-8-git-send-email-a.hajda@samsung.com
This commit is contained in:
Andrzej Hajda
Archit Taneja
parent
981b3f3724
commit
e19e9c692f
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@ -9,6 +9,8 @@
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* published by the Free Software Foundation.
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*/
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#include <asm/unaligned.h>
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#include <drm/bridge/mhl.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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@ -28,7 +30,8 @@
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#include "sil-sii8620.h"
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#define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
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#define SII8620_BURST_BUF_LEN 288
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#define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
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enum sii8620_mode {
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CM_DISCONNECTED,
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@ -71,6 +74,15 @@ struct sii8620 {
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unsigned int gen2_write_burst:1;
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enum sii8620_mt_state mt_state;
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struct list_head mt_queue;
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struct {
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int r_size;
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int r_count;
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int rx_ack;
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int rx_count;
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u8 rx_buf[32];
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int tx_count;
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u8 tx_buf[32];
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} burst;
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};
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struct sii8620_mt_msg;
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@ -511,6 +523,134 @@ static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
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sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
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}
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static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
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{
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u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
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int size = len + 2;
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if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
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dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
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ctx->error = -EINVAL;
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return NULL;
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}
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ctx->burst.tx_count += size;
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buf[1] = len;
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return buf + 2;
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}
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static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
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{
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u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
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int size = len + 1;
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if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
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dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
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ctx->error = -EINVAL;
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return NULL;
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}
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ctx->burst.rx_count += size;
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buf[0] = len;
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return buf + 1;
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}
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static void sii8620_burst_send(struct sii8620 *ctx)
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{
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int tx_left = ctx->burst.tx_count;
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u8 *d = ctx->burst.tx_buf;
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while (tx_left > 0) {
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int len = d[1] + 2;
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if (ctx->burst.r_count + len > ctx->burst.r_size)
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break;
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d[0] = min(ctx->burst.rx_ack, 255);
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ctx->burst.rx_ack -= d[0];
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sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
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ctx->burst.r_count += len;
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tx_left -= len;
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d += len;
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}
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ctx->burst.tx_count = tx_left;
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while (ctx->burst.rx_ack > 0) {
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u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
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if (ctx->burst.r_count + 2 > ctx->burst.r_size)
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break;
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ctx->burst.rx_ack -= b[0];
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sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
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ctx->burst.r_count += 2;
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}
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}
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static void sii8620_burst_receive(struct sii8620 *ctx)
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{
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u8 buf[3], *d;
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int count;
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sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
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count = get_unaligned_le16(buf);
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while (count > 0) {
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int len = min(count, 3);
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sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
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count -= len;
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ctx->burst.rx_ack += len - 1;
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ctx->burst.r_count -= buf[1];
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if (ctx->burst.r_count < 0)
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ctx->burst.r_count = 0;
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if (len < 3 || !buf[2])
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continue;
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len = buf[2];
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d = sii8620_burst_get_rx_buf(ctx, len);
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if (!d)
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continue;
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sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
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count -= len;
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ctx->burst.rx_ack += len;
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}
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}
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static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
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{
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struct mhl_burst_blk_rcv_buffer_info *d =
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sii8620_burst_get_tx_buf(ctx, sizeof(*d));
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if (!d)
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return;
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d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
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d->size = cpu_to_le16(size);
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}
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static void sii8620_burst_rx_all(struct sii8620 *ctx)
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{
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u8 *d = ctx->burst.rx_buf;
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int count = ctx->burst.rx_count;
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while (count-- > 0) {
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int len = *d++;
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int id = get_unaligned_be16(&d[0]);
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switch (id) {
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case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
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ctx->burst.r_size = get_unaligned_le16(&d[2]);
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break;
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default:
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break;
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}
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count -= len;
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d += len;
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}
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ctx->burst.rx_count = 0;
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}
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static void sii8620_fetch_edid(struct sii8620 *ctx)
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{
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u8 lm_ddc, ddc_cmd, int3, cbus;
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@ -1417,6 +1557,19 @@ static void sii8620_irq_coc(struct sii8620 *ctx)
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{
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u8 stat = sii8620_readb(ctx, REG_COC_INTR);
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if (stat & BIT_COC_CALIBRATION_DONE) {
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u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
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cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
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if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
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sii8620_write_seq_static(ctx,
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REG_COC_CTLB, 0,
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REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
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| BIT_TDM_INTR_SYNC_WAIT
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);
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}
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}
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sii8620_write(ctx, REG_COC_INTR, stat);
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}
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@ -1507,6 +1660,41 @@ static void sii8620_irq_infr(struct sii8620 *ctx)
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sii8620_start_video(ctx);
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}
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static void sii8620_irq_tdm(struct sii8620 *ctx)
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{
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u8 stat = sii8620_readb(ctx, REG_TRXINTH);
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u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
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if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
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ctx->mode = CM_ECBUS_S;
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ctx->burst.rx_ack = 0;
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ctx->burst.r_size = SII8620_BURST_BUF_LEN;
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sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
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sii8620_mt_read_devcap(ctx, true);
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} else {
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sii8620_write_seq_static(ctx,
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REG_MHL_PLL_CTL2, 0,
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REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
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);
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}
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sii8620_write(ctx, REG_TRXINTH, stat);
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}
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static void sii8620_irq_block(struct sii8620 *ctx)
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{
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u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
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if (stat & BIT_EMSCINTR_SPI_DVLD) {
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u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
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if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
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sii8620_burst_receive(ctx);
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}
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sii8620_write(ctx, REG_EMSCINTR, stat);
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}
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/* endian agnostic, non-volatile version of test_bit */
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static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
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{
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@ -1522,8 +1710,10 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
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{ BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
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{ BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
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{ BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
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{ BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
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{ BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
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{ BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
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{ BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
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{ BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
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{ BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
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{ BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
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@ -1539,7 +1729,9 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
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if (sii8620_test_bit(irq_vec[i].bit, stats))
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irq_vec[i].handler(ctx);
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sii8620_burst_rx_all(ctx);
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sii8620_mt_work(ctx);
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sii8620_burst_send(ctx);
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ret = sii8620_clear_error(ctx);
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if (ret) {
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@ -403,12 +403,16 @@
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/* TDM RX Status 2nd, default value: 0x00 */
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#define REG_TRXSTA2 0x015c
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#define MSK_TDM_SYNCHRONIZED 0xc0
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#define VAL_TDM_SYNCHRONIZED 0x80
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/* TDM RX INT Low, default value: 0x00 */
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#define REG_TRXINTL 0x0163
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/* TDM RX INT High, default value: 0x00 */
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#define REG_TRXINTH 0x0164
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#define BIT_TDM_INTR_SYNC_DATA BIT(0)
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#define BIT_TDM_INTR_SYNC_WAIT BIT(1)
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/* TDM RX INTMASK High, default value: 0x00 */
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#define REG_TRXINTMH 0x0166
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