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ASoC: amd: pte offset related dma driver changes 

Added pte offset variable in audio_substream_data structure.
Added Stoney related PTE offset macros in acp header file.
Modified hw_params callback to assign the pte offset value
based on asic_type.
PTE Offset macros used to calculate no of PTE entries
need to be programmed when memory allocated for audio buffer.
Depending upon allocated audio buffer size, PTE offset values
will change.
Compared to CZ, Stoney has SRAM memory limitation i.e 48k
It is required to define separate PTE Offset macros for
Stoney.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Mukunda, Vijendar 2018-05-08 10:17:47 +05:30 committed by Mark Brown
parent a4ae3af59b
commit e188c525b9
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 24 additions and 7 deletions
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26
sound/soc/amd/acp-pcm-dma.c
View File

@ -320,13 +320,11 @@ static void config_acp_dma(void __iomem *acp_mmio,
struct audio_substream_data *rtd,
u32 asic_type)
{
u32 pte_offset, sram_bank;
u32 sram_bank;
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
pte_offset = ACP_PLAYBACK_PTE_OFFSET;
if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK)
sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS;
} else {
pte_offset = ACP_CAPTURE_PTE_OFFSET;
else {
switch (asic_type) {
case CHIP_STONEY:
sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS;
@ -336,10 +334,10 @@ static void config_acp_dma(void __iomem *acp_mmio,
}
}
acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
pte_offset);
rtd->pte_offset);
/* Configure System memory <-> ACP SRAM DMA descriptors */
set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
rtd->direction, pte_offset,
rtd->direction, rtd->pte_offset,
rtd->ch1, sram_bank,
rtd->dma_dscr_idx_1, asic_type);
/* Configure ACP SRAM <-> I2S DMA descriptors */
@ -788,6 +786,13 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
break;
default:
rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
}
rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
rtd->destination = TO_ACP_I2S_1;
@ -797,6 +802,13 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
rtd->byte_cnt_low_reg_offset = mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
} else {
switch (adata->asic_type) {
case CHIP_STONEY:
rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
break;
default:
rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
}
rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
rtd->destination = FROM_ACP_I2S_1;

5
sound/soc/amd/acp.h
View File

@ -10,6 +10,10 @@
#define ACP_PLAYBACK_PTE_OFFSET 10
#define ACP_CAPTURE_PTE_OFFSET 0
/* Playback and Capture Offset for Stoney */
#define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
#define ACP_ST_CAPTURE_PTE_OFFSET 0x00
#define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
#define ACP_ONION_CNTL_DEFAULT 0x00000FB4
@ -90,6 +94,7 @@ struct audio_substream_data {
u16 destination;
u16 dma_dscr_idx_1;
u16 dma_dscr_idx_2;
u32 pte_offset;
u32 byte_cnt_high_reg_offset;
u32 byte_cnt_low_reg_offset;
uint64_t size;