drm/i915: Clean up PCI config register handling
Do not use magic numbers, do not prefix stuff with "PCI_", do not declare registers in implementation files. Also move the PCI registers under correct comment in i915_reg.h. v2: - Consistently use BSM (not BDSM or other variants from PRM) (Chris) - Also include register address to help identify the register (Chris) v3: - Refer to register value as *_val instead of *_reg (Chris) v4: - Make style checker happy Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Joonas Lahtinen
parent
44a7102484
commit
e10fa551ae
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@ -257,13 +257,6 @@ static int i915_get_bridge_dev(struct drm_device *dev)
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return 0;
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}
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#define MCHBAR_I915 0x44
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#define MCHBAR_I965 0x48
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#define MCHBAR_SIZE (4*4096)
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#define DEVEN_REG 0x54
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#define DEVEN_MCHBAR_EN (1 << 28)
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/* Allocate space for the MCH regs if needed, return nonzero on error */
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static int
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intel_alloc_mchbar_resource(struct drm_device *dev)
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@ -325,7 +318,7 @@ intel_setup_mchbar(struct drm_device *dev)
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dev_priv->mchbar_need_disable = false;
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if (IS_I915G(dev) || IS_I915GM(dev)) {
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pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
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pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
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enabled = !!(temp & DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
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@ -343,7 +336,7 @@ intel_setup_mchbar(struct drm_device *dev)
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/* Space is allocated or reserved, so enable it. */
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if (IS_I915G(dev) || IS_I915GM(dev)) {
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pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
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pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
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temp | DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
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@ -356,17 +349,24 @@ intel_teardown_mchbar(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp;
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if (dev_priv->mchbar_need_disable) {
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if (IS_I915G(dev) || IS_I915GM(dev)) {
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pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
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temp &= ~DEVEN_MCHBAR_EN;
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pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
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u32 deven_val;
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pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
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&deven_val);
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deven_val &= ~DEVEN_MCHBAR_EN;
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pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
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deven_val);
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} else {
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
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temp &= ~1;
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pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
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u32 mchbar_val;
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
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&mchbar_val);
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mchbar_val &= ~1;
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pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
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mchbar_val);
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}
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}
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@ -95,9 +95,9 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
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u32 base;
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/* Almost universally we can find the Graphics Base of Stolen Memory
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* at offset 0x5c in the igfx configuration space. On a few (desktop)
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* machines this is also mirrored in the bridge device at different
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* locations, or in the MCHBAR.
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* at register BSM (0x5c) in the igfx configuration space. On a few
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* (desktop) machines this is also mirrored in the bridge device at
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* different locations, or in the MCHBAR.
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*
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* On 865 we just check the TOUD register.
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*
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@ -107,9 +107,11 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
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*/
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base = 0;
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if (INTEL_INFO(dev)->gen >= 3) {
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/* Read Graphics Base of Stolen Memory directly */
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pci_read_config_dword(dev->pdev, 0x5c, &base);
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base &= ~((1<<20) - 1);
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u32 bsm;
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pci_read_config_dword(dev->pdev, BSM, &bsm);
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base = bsm & BSM_MASK;
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} else if (IS_I865G(dev)) {
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u16 toud = 0;
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@ -79,6 +79,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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/* PCI config space */
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#define MCHBAR_I915 0x44
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#define MCHBAR_I965 0x48
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#define MCHBAR_SIZE (4 * 4096)
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#define DEVEN 0x54
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#define DEVEN_MCHBAR_EN (1 << 28)
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#define BSM 0x5c
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#define BSM_MASK (0xFFFF << 20)
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#define HPLLCC 0xc0 /* 85x only */
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#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
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#define GC_CLOCK_133_200 (0 << 0)
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@ -90,6 +100,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define GC_CLOCK_166_266 (6 << 0)
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#define GC_CLOCK_166_250 (7 << 0)
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#define I915_GDRST 0xc0 /* PCI config register */
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#define GRDOM_FULL (0 << 2)
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#define GRDOM_RENDER (1 << 2)
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#define GRDOM_MEDIA (3 << 2)
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#define GRDOM_MASK (3 << 2)
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#define GRDOM_RESET_STATUS (1 << 1)
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#define GRDOM_RESET_ENABLE (1 << 0)
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#define GCDGMBUS 0xcc
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#define GCFGC2 0xda
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#define GCFGC 0xf0 /* 915+ only */
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#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
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@ -121,18 +141,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
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#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
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#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
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#define GCDGMBUS 0xcc
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#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
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#define ASLE 0xe4
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#define ASLS 0xfc
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#define SWSCI 0xe8
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#define SWSCI_SCISEL (1 << 15)
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#define SWSCI_GSSCIE (1 << 0)
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#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
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/* Graphics reset regs */
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#define I915_GDRST 0xc0 /* PCI config register */
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#define GRDOM_FULL (0<<2)
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#define GRDOM_RENDER (1<<2)
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#define GRDOM_MEDIA (3<<2)
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#define GRDOM_MASK (3<<2)
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#define GRDOM_RESET_STATUS (1<<1)
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#define GRDOM_RESET_ENABLE (1<<0)
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#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
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#define ILK_GRDOM_FULL (0<<1)
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@ -34,12 +34,6 @@
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#include "i915_drv.h"
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#include "intel_drv.h"
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#define PCI_ASLE 0xe4
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#define PCI_ASLS 0xfc
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#define PCI_SWSCI 0xe8
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#define PCI_SWSCI_SCISEL (1 << 15)
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#define PCI_SWSCI_GSSCIE (1 << 0)
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#define OPREGION_HEADER_OFFSET 0
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#define OPREGION_ACPI_OFFSET 0x100
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#define ACPI_CLID 0x01ac /* current lid state indicator */
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@ -251,7 +245,7 @@ static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct opregion_swsci *swsci = dev_priv->opregion.swsci;
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u32 main_function, sub_function, scic;
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u16 pci_swsci;
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u16 swsci_val;
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u32 dslp;
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if (!swsci)
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@ -299,16 +293,16 @@ static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out)
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swsci->scic = scic;
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/* Ensure SCI event is selected and event trigger is cleared. */
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pci_read_config_word(dev->pdev, PCI_SWSCI, &pci_swsci);
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if (!(pci_swsci & PCI_SWSCI_SCISEL) || (pci_swsci & PCI_SWSCI_GSSCIE)) {
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pci_swsci |= PCI_SWSCI_SCISEL;
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pci_swsci &= ~PCI_SWSCI_GSSCIE;
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pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);
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pci_read_config_word(dev->pdev, SWSCI, &swsci_val);
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if (!(swsci_val & SWSCI_SCISEL) || (swsci_val & SWSCI_GSSCIE)) {
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swsci_val |= SWSCI_SCISEL;
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swsci_val &= ~SWSCI_GSSCIE;
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pci_write_config_word(dev->pdev, SWSCI, swsci_val);
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}
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/* Use event trigger to tell bios to check the mail. */
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pci_swsci |= PCI_SWSCI_GSSCIE;
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pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);
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swsci_val |= SWSCI_GSSCIE;
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pci_write_config_word(dev->pdev, SWSCI, swsci_val);
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/* Poll for the result. */
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#define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0)
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@ -939,7 +933,7 @@ int intel_opregion_setup(struct drm_device *dev)
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BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100);
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BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400);
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pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
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pci_read_config_dword(dev->pdev, ASLS, &asls);
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DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);
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if (asls == 0) {
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DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n");
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@ -504,7 +504,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
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if (panel->backlight.combination_mode) {
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u8 lbpc;
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pci_read_config_byte(dev_priv->dev->pdev, PCI_LBPC, &lbpc);
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pci_read_config_byte(dev_priv->dev->pdev, LBPC, &lbpc);
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val *= lbpc;
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}
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@ -592,7 +592,7 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
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lbpc = level * 0xfe / panel->backlight.max + 1;
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level /= lbpc;
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pci_write_config_byte(dev_priv->dev->pdev, PCI_LBPC, lbpc);
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pci_write_config_byte(dev_priv->dev->pdev, LBPC, lbpc);
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}
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if (IS_GEN4(dev_priv)) {
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