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drm/amd/powerplay: Fix Vega10 power profile switching 

Clock index 0 is a valid index that is needed to restore the default
graphics power profile. Use ~0 to indicate a failure to find a clock
index. This fixes the clocks getting stuck in the compute power
profile after running a compute application on Vega10.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Felix Kuehling 2017-05-15 04:08:28 -04:00 committed by Alex Deucher
parent 2d2e5e7e53
commit e0ec450636
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
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@ -4583,7 +4583,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request)
{
struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
uint32_t sclk_idx = 0, mclk_idx = 0;
uint32_t sclk_idx = ~0, mclk_idx = ~0;
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
return -EINVAL;
@ -4591,7 +4591,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
vega10_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
request->min_sclk, request->min_mclk);
if (sclk_idx) {
if (sclk_idx != ~0) {
if (!data->registry_data.sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter(
@ -4602,7 +4602,7 @@ static int vega10_set_power_profile_state(struct pp_hwmgr *hwmgr,
return -EINVAL);
}
if (mclk_idx) {
if (mclk_idx != ~0) {
if (!data->registry_data.mclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
!smum_send_msg_to_smc_with_parameter(