Merge branch 'renesas-r8a7740' into renesas-armadillo
* renesas-r8a7740: ARM: shmobile: use common DMAEngine definitions on r8a7740 ARM: shmobile: r8a7740: add DMAEngine support for USB ARM: shmobile: r8a7740: add DMAEngine support for SDHI ARM: shmobile: r8a7740: add DMAEngine support for FSI ARM: shmobile: add common DMAEngine definitions ARM: shmobile: add common extra gpio functions
This commit is contained in:
Rafael J. Wysocki
commit
e01fa821b8
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@ -463,6 +463,7 @@ enum {
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MSTP230,
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MSTP222,
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MSTP218, MSTP217, MSTP216, MSTP214,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323, MSTP320,
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@ -485,6 +486,10 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
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[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
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[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
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[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
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[MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
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[MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
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[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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@ -563,7 +568,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
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CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
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CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
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@ -0,0 +1,84 @@
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/*
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* SH-ARM CPU-specific DMA definitions, used by both DMA drivers
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*
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* Copyright (C) 2012 Renesas Solutions Corp
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*
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DMA_REGISTER_H
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#define DMA_REGISTER_H
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/*
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* Direct Memory Access Controller
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*/
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_512BIT = 5,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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static const unsigned int dma_ts_shift[] = {
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_64BIT] = 3,
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[XMIT_SZ_128BIT] = 4,
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[XMIT_SZ_256BIT] = 5,
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[XMIT_SZ_512BIT] = 6,
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};
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#define TS_LOW_BIT 0x3 /* --xx */
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#define TS_HI_BIT 0xc /* xx-- */
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#define TS_LOW_SHIFT (3)
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#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#define TS_INDEX2VAL(i) \
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((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
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(((i) & TS_HI_BIT) << TS_HI_SHIFT))
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#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
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#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
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/*
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* USB High-Speed DMAC
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*/
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/* Transmit sizes and respective CHCR register values */
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enum {
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USBTS_XMIT_SZ_8BYTE = 0,
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USBTS_XMIT_SZ_16BYTE = 1,
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USBTS_XMIT_SZ_32BYTE = 2,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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static const unsigned int dma_usbts_shift[] = {
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[USBTS_XMIT_SZ_8BYTE] = 3,
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[USBTS_XMIT_SZ_16BYTE] = 4,
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[USBTS_XMIT_SZ_32BYTE] = 5,
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};
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#define USBTS_LOW_BIT 0x3 /* --xx */
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#define USBTS_HI_BIT 0x0 /* ---- */
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#define USBTS_LOW_SHIFT 6
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#define USBTS_HI_SHIFT 0
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#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
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#endif /* DMA_REGISTER_H */
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@ -13,6 +13,7 @@
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/sh_pfc.h>
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#include <linux/io.h>
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#ifdef CONFIG_GPIOLIB
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@ -27,4 +28,35 @@ static inline int irq_to_gpio(unsigned int irq)
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#endif /* CONFIG_GPIOLIB */
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/*
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* FIXME !!
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*
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* current gpio frame work doesn't have
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* the method to control only pull up/down/free.
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* this function should be replaced by correct gpio function
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*/
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static inline void __init gpio_direction_none(u32 addr)
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{
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__raw_writeb(0x00, addr);
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}
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static inline void __init gpio_request_pullup(u32 addr)
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{
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u8 data = __raw_readb(addr);
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data &= 0x0F;
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data |= 0xC0;
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__raw_writeb(data, addr);
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}
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static inline void __init gpio_request_pulldown(u32 addr)
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{
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u8 data = __raw_readb(addr);
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data &= 0x0F;
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data |= 0xA0;
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__raw_writeb(data, addr);
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}
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#endif /* __ASM_ARCH_GPIO_H */
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@ -588,4 +588,20 @@ enum {
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GPIO_FN_TRACEAUD_FROM_MEMC,
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};
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/* DMA slave IDs */
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enum {
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SHDMA_SLAVE_INVALID,
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SHDMA_SLAVE_SDHI0_RX,
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SHDMA_SLAVE_SDHI0_TX,
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SHDMA_SLAVE_SDHI1_RX,
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SHDMA_SLAVE_SDHI1_TX,
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SHDMA_SLAVE_SDHI2_RX,
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SHDMA_SLAVE_SDHI2_TX,
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SHDMA_SLAVE_FSIA_RX,
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SHDMA_SLAVE_FSIA_TX,
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SHDMA_SLAVE_FSIB_TX,
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SHDMA_SLAVE_USBHS_TX,
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SHDMA_SLAVE_USBHS_RX,
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};
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#endif /* __ASM_R8A7740_H__ */
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@ -24,7 +24,10 @@
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <linux/dma-mapping.h>
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#include <mach/dma-register.h>
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#include <mach/r8a7740.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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@ -276,6 +279,272 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
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&cmt10_device,
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};
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/* DMA */
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static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SDHI0_TX,
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.addr = 0xe6850030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc1,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_RX,
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.addr = 0xe6850030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xc2,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_TX,
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.addr = 0xe6860030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc9,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_RX,
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.addr = 0xe6860030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xca,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_TX,
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.addr = 0xe6870030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xcd,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_RX,
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.addr = 0xe6870030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xce,
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}, {
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.slave_id = SHDMA_SLAVE_FSIA_TX,
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.addr = 0xfe1f0024,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xb1,
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}, {
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.slave_id = SHDMA_SLAVE_FSIA_RX,
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.addr = 0xfe1f0020,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xb2,
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}, {
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.slave_id = SHDMA_SLAVE_FSIB_TX,
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.addr = 0xfe1f0064,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xb5,
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},
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};
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#define DMA_CHANNEL(a, b, c) \
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{ \
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.offset = a, \
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.dmars = b, \
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.dmars_bit = c, \
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.chclr_offset = (0x220 - 0x20) + a \
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}
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static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
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DMA_CHANNEL(0x00, 0, 0),
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DMA_CHANNEL(0x10, 0, 8),
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DMA_CHANNEL(0x20, 4, 0),
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DMA_CHANNEL(0x30, 4, 8),
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DMA_CHANNEL(0x50, 8, 0),
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DMA_CHANNEL(0x60, 8, 8),
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};
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static struct sh_dmae_pdata dma_platform_data = {
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.slave = r8a7740_dmae_slaves,
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.slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
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.channel = r8a7740_dmae_channels,
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.channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
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.ts_low_shift = TS_LOW_SHIFT,
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.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
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.ts_high_shift = TS_HI_SHIFT,
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.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
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.ts_shift = dma_ts_shift,
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.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
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.dmaor_init = DMAOR_DME,
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.chclr_present = 1,
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae0_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe008020,
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.end = 0xfe00828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe009000,
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.end = 0xfe00900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x20c0),
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.end = evt2irq(0x20c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2000),
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.end = evt2irq(0x20a0),
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.flags = IORESOURCE_IRQ,
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},
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae1_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe018020,
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.end = 0xfe01828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe019000,
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.end = 0xfe01900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x21c0),
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.end = evt2irq(0x21c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2100),
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.end = evt2irq(0x21a0),
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.flags = IORESOURCE_IRQ,
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},
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae2_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe028020,
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.end = 0xfe02828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe029000,
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.end = 0xfe02900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x22c0),
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.end = evt2irq(0x22c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2200),
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.end = evt2irq(0x22a0),
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.flags = IORESOURCE_IRQ,
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},
|
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};
|
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|
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static struct platform_device dma0_device = {
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.name = "sh-dma-engine",
|
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.id = 0,
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.resource = r8a7740_dmae0_resources,
|
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.num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
|
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.dev = {
|
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.platform_data = &dma_platform_data,
|
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},
|
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};
|
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|
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static struct platform_device dma1_device = {
|
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.name = "sh-dma-engine",
|
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.id = 1,
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.resource = r8a7740_dmae1_resources,
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.num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
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.dev = {
|
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.platform_data = &dma_platform_data,
|
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},
|
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};
|
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|
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static struct platform_device dma2_device = {
|
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.name = "sh-dma-engine",
|
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.id = 2,
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.resource = r8a7740_dmae2_resources,
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.num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
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.dev = {
|
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.platform_data = &dma_platform_data,
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},
|
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};
|
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|
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/* USB-DMAC */
|
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static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
|
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{
|
||||
.offset = 0,
|
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}, {
|
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.offset = 0x20,
|
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},
|
||||
};
|
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|
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static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
|
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{
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.slave_id = SHDMA_SLAVE_USBHS_TX,
|
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.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
|
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}, {
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.slave_id = SHDMA_SLAVE_USBHS_RX,
|
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.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
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},
|
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};
|
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|
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static struct sh_dmae_pdata usb_dma_platform_data = {
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.slave = r8a7740_usb_dma_slaves,
|
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.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
|
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.channel = r8a7740_usb_dma_channels,
|
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.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
|
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.ts_low_shift = USBTS_LOW_SHIFT,
|
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.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
|
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.ts_high_shift = USBTS_HI_SHIFT,
|
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.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
|
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.ts_shift = dma_usbts_shift,
|
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.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chcr_offset = 0x14,
|
||||
.chcr_ie_bit = 1 << 5,
|
||||
.dmaor_is_32bit = 1,
|
||||
.needs_tend_set = 1,
|
||||
.no_dmars = 1,
|
||||
.slave_only = 1,
|
||||
};
|
||||
|
||||
static struct resource r8a7740_usb_dma_resources[] = {
|
||||
{
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xe68a0020,
|
||||
.end = 0xe68a0064 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* VCR/SWR/DMICR */
|
||||
.start = 0xe68a0000,
|
||||
.end = 0xe68a0014 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels */
|
||||
.start = evt2irq(0x0a00),
|
||||
.end = evt2irq(0x0a00),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device usb_dma_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 3,
|
||||
.resource = r8a7740_usb_dma_resources,
|
||||
.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
|
||||
.dev = {
|
||||
.platform_data = &usb_dma_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
static struct resource i2c0_resources[] = {
|
||||
[0] = {
|
||||
|
|
@ -322,6 +591,10 @@ static struct platform_device i2c1_device = {
|
|||
static struct platform_device *r8a7740_late_devices[] __initdata = {
|
||||
&i2c0_device,
|
||||
&i2c1_device,
|
||||
&dma0_device,
|
||||
&dma1_device,
|
||||
&dma2_device,
|
||||
&usb_dma_device,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue