m68k: Remove five unused headers
There are five entirely unused headers in arch/m68k/include/asm. Nothing includes these headers. And a few tests found no hits for the things they provide (which makes sense). MC68332.h, mac_mouse.h, and mcfmbus.h are all unused since at least v2.6.12-rc2 (I didn't bother looking further back than that). apollodma.h is unused since v2.6.19: commit2ed0ce5b57("m68k/Apollo: Remove obsolete arch/m68k/apollo/dma.c") removed the last file interested in that header. And everything interested in <asm/sbus.h> was removed in the v2.6.28 release cycle. The last occurrence of "sbus.h" was deleted with commit0c0db98b50("sparc: Remove Documentation/sparc/sbus_drivers.txt"). I'm not sure whether anything relevant for m68k was included in v2.6.27, but it doesn't really matter. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Greg Ungerer<gerg@uclinux.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
This commit is contained in:
Paul Bolle
Geert Uytterhoeven
parent
7df0d27f3d
commit
dffc5837d8
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@ -1,152 +0,0 @@
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/* include/asm-m68knommu/MC68332.h: '332 control registers
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*
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* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
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*
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*/
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#ifndef _MC68332_H_
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#define _MC68332_H_
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#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
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#define WORD_REF(addr) (*((volatile unsigned short*)addr))
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#define PORTE_ADDR 0xfffa11
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#define PORTE BYTE_REF(PORTE_ADDR)
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#define DDRE_ADDR 0xfffa15
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#define DDRE BYTE_REF(DDRE_ADDR)
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#define PEPAR_ADDR 0xfffa17
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#define PEPAR BYTE_REF(PEPAR_ADDR)
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#define PORTF_ADDR 0xfffa19
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#define PORTF BYTE_REF(PORTF_ADDR)
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#define DDRF_ADDR 0xfffa1d
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#define DDRF BYTE_REF(DDRF_ADDR)
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#define PFPAR_ADDR 0xfffa1f
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#define PFPAR BYTE_REF(PFPAR_ADDR)
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#define PORTQS_ADDR 0xfffc15
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#define PORTQS BYTE_REF(PORTQS_ADDR)
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#define DDRQS_ADDR 0xfffc17
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#define DDRQS BYTE_REF(DDRQS_ADDR)
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#define PQSPAR_ADDR 0xfffc16
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#define PQSPAR BYTE_REF(PQSPAR_ADDR)
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#define CSPAR0_ADDR 0xFFFA44
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#define CSPAR0 WORD_REF(CSPAR0_ADDR)
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#define CSPAR1_ADDR 0xFFFA46
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#define CSPAR1 WORD_REF(CSPAR1_ADDR)
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#define CSARBT_ADDR 0xFFFA48
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#define CSARBT WORD_REF(CSARBT_ADDR)
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#define CSOPBT_ADDR 0xFFFA4A
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#define CSOPBT WORD_REF(CSOPBT_ADDR)
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#define CSBAR0_ADDR 0xFFFA4C
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#define CSBAR0 WORD_REF(CSBAR0_ADDR)
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#define CSOR0_ADDR 0xFFFA4E
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#define CSOR0 WORD_REF(CSOR0_ADDR)
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#define CSBAR1_ADDR 0xFFFA50
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#define CSBAR1 WORD_REF(CSBAR1_ADDR)
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#define CSOR1_ADDR 0xFFFA52
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#define CSOR1 WORD_REF(CSOR1_ADDR)
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#define CSBAR2_ADDR 0xFFFA54
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#define CSBAR2 WORD_REF(CSBAR2_ADDR)
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#define CSOR2_ADDR 0xFFFA56
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#define CSOR2 WORD_REF(CSOR2_ADDR)
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#define CSBAR3_ADDR 0xFFFA58
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#define CSBAR3 WORD_REF(CSBAR3_ADDR)
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#define CSOR3_ADDR 0xFFFA5A
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#define CSOR3 WORD_REF(CSOR3_ADDR)
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#define CSBAR4_ADDR 0xFFFA5C
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#define CSBAR4 WORD_REF(CSBAR4_ADDR)
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#define CSOR4_ADDR 0xFFFA5E
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#define CSOR4 WORD_REF(CSOR4_ADDR)
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#define CSBAR5_ADDR 0xFFFA60
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#define CSBAR5 WORD_REF(CSBAR5_ADDR)
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#define CSOR5_ADDR 0xFFFA62
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#define CSOR5 WORD_REF(CSOR5_ADDR)
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#define CSBAR6_ADDR 0xFFFA64
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#define CSBAR6 WORD_REF(CSBAR6_ADDR)
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#define CSOR6_ADDR 0xFFFA66
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#define CSOR6 WORD_REF(CSOR6_ADDR)
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#define CSBAR7_ADDR 0xFFFA68
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#define CSBAR7 WORD_REF(CSBAR7_ADDR)
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#define CSOR7_ADDR 0xFFFA6A
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#define CSOR7 WORD_REF(CSOR7_ADDR)
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#define CSBAR8_ADDR 0xFFFA6C
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#define CSBAR8 WORD_REF(CSBAR8_ADDR)
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#define CSOR8_ADDR 0xFFFA6E
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#define CSOR8 WORD_REF(CSOR8_ADDR)
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#define CSBAR9_ADDR 0xFFFA70
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#define CSBAR9 WORD_REF(CSBAR9_ADDR)
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#define CSOR9_ADDR 0xFFFA72
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#define CSOR9 WORD_REF(CSOR9_ADDR)
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#define CSBAR10_ADDR 0xFFFA74
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#define CSBAR10 WORD_REF(CSBAR10_ADDR)
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#define CSOR10_ADDR 0xFFFA76
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#define CSOR10 WORD_REF(CSOR10_ADDR)
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#define CSOR_MODE_ASYNC 0x0000
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#define CSOR_MODE_SYNC 0x8000
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#define CSOR_MODE_MASK 0x8000
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#define CSOR_BYTE_DISABLE 0x0000
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#define CSOR_BYTE_UPPER 0x4000
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#define CSOR_BYTE_LOWER 0x2000
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#define CSOR_BYTE_BOTH 0x6000
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#define CSOR_BYTE_MASK 0x6000
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#define CSOR_RW_RSVD 0x0000
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#define CSOR_RW_READ 0x0800
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#define CSOR_RW_WRITE 0x1000
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#define CSOR_RW_BOTH 0x1800
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#define CSOR_RW_MASK 0x1800
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#define CSOR_STROBE_DS 0x0400
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#define CSOR_STROBE_AS 0x0000
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#define CSOR_STROBE_MASK 0x0400
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#define CSOR_DSACK_WAIT(x) (wait << 6)
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#define CSOR_DSACK_FTERM (14 << 6)
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#define CSOR_DSACK_EXTERNAL (15 << 6)
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#define CSOR_DSACK_MASK 0x03c0
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#define CSOR_SPACE_CPU 0x0000
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#define CSOR_SPACE_USER 0x0010
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#define CSOR_SPACE_SU 0x0020
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#define CSOR_SPACE_BOTH 0x0030
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#define CSOR_SPACE_MASK 0x0030
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#define CSOR_IPL_ALL 0x0000
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#define CSOR_IPL_PRIORITY(x) (x << 1)
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#define CSOR_IPL_MASK 0x000e
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#define CSOR_AVEC_ON 0x0001
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#define CSOR_AVEC_OFF 0x0000
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#define CSOR_AVEC_MASK 0x0001
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#define CSBAR_ADDR(x) ((addr >> 11) << 3)
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#define CSBAR_ADDR_MASK 0xfff8
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#define CSBAR_BLKSIZE_2K 0x0000
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#define CSBAR_BLKSIZE_8K 0x0001
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#define CSBAR_BLKSIZE_16K 0x0002
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#define CSBAR_BLKSIZE_64K 0x0003
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#define CSBAR_BLKSIZE_128K 0x0004
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#define CSBAR_BLKSIZE_256K 0x0005
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#define CSBAR_BLKSIZE_512K 0x0006
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#define CSBAR_BLKSIZE_1M 0x0007
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#define CSBAR_BLKSIZE_MASK 0x0007
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#define CSPAR_DISC 0
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#define CSPAR_ALT 1
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#define CSPAR_CS8 2
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#define CSPAR_CS16 3
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#define CSPAR_MASK 3
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#define CSPAR0_CSBOOT(x) (x << 0)
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#define CSPAR0_CS0(x) (x << 2)
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#define CSPAR0_CS1(x) (x << 4)
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#define CSPAR0_CS2(x) (x << 6)
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#define CSPAR0_CS3(x) (x << 8)
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#define CSPAR0_CS4(x) (x << 10)
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#define CSPAR0_CS5(x) (x << 12)
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#define CSPAR1_CS6(x) (x << 0)
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#define CSPAR1_CS7(x) (x << 2)
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#define CSPAR1_CS8(x) (x << 4)
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#define CSPAR1_CS9(x) (x << 6)
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#define CSPAR1_CS10(x) (x << 8)
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#endif
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@ -1,248 +0,0 @@
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/*
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* linux/include/asm/dma.h: Defines for using and allocating dma channels.
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* Written by Hennus Bergman, 1992.
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* High DMA channel support & info by Hannu Savolainen
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* and John Boyd, Nov. 1992.
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*/
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#ifndef _ASM_APOLLO_DMA_H
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#define _ASM_APOLLO_DMA_H
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#include <asm/apollohw.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
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#define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE)))
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/*
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* NOTES about DMA transfers:
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*
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* controller 1: channels 0-3, byte operations, ports 00-1F
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* controller 2: channels 4-7, word operations, ports C0-DF
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*
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* - ALL registers are 8 bits only, regardless of transfer size
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* - channel 4 is not used - cascades 1 into 2.
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* - channels 0-3 are byte - addresses/counts are for physical bytes
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* - channels 5-7 are word - addresses/counts are for physical words
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* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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* - transfer count loaded to registers is 1 less than actual count
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* - controller 2 offsets are all even (2x offsets for controller 1)
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* - page registers for 5-7 don't use data bit 0, represent 128K pages
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* - page registers for 0-3 use bit 0, represent 64K pages
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*
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* DMA transfers are limited to the lower 16MB of _physical_ memory.
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* Note that addresses loaded into registers must be _physical_ addresses,
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* not logical addresses (which may differ if paging is active).
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*
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* Address mapping for channels 0-3:
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*
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* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* | ... | | ... | | ... |
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* P7 ... P0 A7 ... A0 A7 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Address mapping for channels 5-7:
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*
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* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
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* | ... | \ \ ... \ \ \ ... \ \
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* | ... | \ \ ... \ \ \ ... \ (not used)
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* | ... | \ \ ... \ \ \ ... \
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* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
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* | Page | Addr MSB | Addr LSB | (DMA registers)
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*
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* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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* the hardware level, so odd-byte transfers aren't possible).
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*
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* Transfer count (_not # bytes_) is limited to 64K, represented as actual
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* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
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* and up to 128K bytes may be transferred on channels 5-7 in one operation.
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*
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*/
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#define MAX_DMA_CHANNELS 8
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/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
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#define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
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#define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
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#define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
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#define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
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#define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
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#define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
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#define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
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#define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
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#define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
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#define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
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#define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
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#define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
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#define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
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#define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
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#define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
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#define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
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#define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
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#define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
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#define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
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#define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
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#define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
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#define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
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#define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
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#define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
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#define DMA_CNT_1 (IO_DMA1_BASE+0x03)
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#define DMA_CNT_2 (IO_DMA1_BASE+0x05)
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#define DMA_CNT_3 (IO_DMA1_BASE+0x07)
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#define DMA_CNT_4 (IO_DMA2_BASE+0x02)
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#define DMA_CNT_5 (IO_DMA2_BASE+0x06)
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#define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
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#define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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#define DMA_AUTOINIT 0x10
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#define DMA_8BIT 0
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#define DMA_16BIT 1
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#define DMA_BUSMASTER 2
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* enable/disable a specific DMA channel */
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static __inline__ void enable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr, DMA1_MASK_REG);
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else
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dma_outb(dmanr & 3, DMA2_MASK_REG);
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}
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static __inline__ void disable_dma(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(dmanr | 4, DMA1_MASK_REG);
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else
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dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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* Use this once to initialize the FF to a known state.
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* After that, keep track of it. :-)
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* --- In order to do that, the DMA routines below should ---
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* --- only be used while holding the DMA lock ! ---
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*/
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static __inline__ void clear_dma_ff(unsigned int dmanr)
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{
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if (dmanr<=3)
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dma_outb(0, DMA1_CLEAR_FF_REG);
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else
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dma_outb(0, DMA2_CLEAR_FF_REG);
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}
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/* set mode (above) for a specific DMA channel */
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
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{
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if (dmanr<=3)
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dma_outb(mode | dmanr, DMA1_MODE_REG);
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else
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dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
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}
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/* Set transfer address & page bits for specific DMA channel.
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* Assumes dma flipflop is clear.
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*/
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
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{
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if (dmanr <= 3) {
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dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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} else {
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dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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}
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}
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/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
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* a specific DMA channel.
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* You must ensure the parameters are valid.
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* NOTE: from a manual: "the number of transfers is one more
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* than the initial word count"! This is taken into account.
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* Assumes dma flip-flop is clear.
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* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
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*/
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
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{
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count--;
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if (dmanr <= 3) {
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dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
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} else {
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dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
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dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Get DMA residue count. After a DMA transfer, this
|
||||
* should return zero. Reading this while a DMA transfer is
|
||||
* still in progress will return unpredictable results.
|
||||
* If called before the channel has been used, it may return 1.
|
||||
* Otherwise, it returns the number of _bytes_ left to transfer.
|
||||
*
|
||||
* Assumes DMA flip-flop is clear.
|
||||
*/
|
||||
static __inline__ int get_dma_residue(unsigned int dmanr)
|
||||
{
|
||||
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
|
||||
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
|
||||
|
||||
/* using short to get 16-bit wrap around */
|
||||
unsigned short count;
|
||||
|
||||
count = 1 + dma_inb(io_port);
|
||||
count += dma_inb(io_port) << 8;
|
||||
|
||||
return (dmanr<=3)? count : (count<<1);
|
||||
}
|
||||
|
||||
|
||||
/* These are in kernel/dma.c: */
|
||||
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
|
||||
extern void free_dma(unsigned int dmanr); /* release it again */
|
||||
|
||||
/* These are in arch/m68k/apollo/dma.c: */
|
||||
extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
|
||||
extern void dma_unmap_page(unsigned short dma_addr);
|
||||
|
||||
#endif /* _ASM_APOLLO_DMA_H */
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
#ifndef _ASM_MAC_MOUSE_H
|
||||
#define _ASM_MAC_MOUSE_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-m68k/mac_mouse.h
|
||||
* header file for Macintosh ADB mouse driver
|
||||
* 27-10-97 Michael Schmitz
|
||||
* copied from:
|
||||
* header file for Atari Mouse driver
|
||||
* by Robert de Vries (robert@and.nl) on 19Jul93
|
||||
*/
|
||||
|
||||
struct mouse_status {
|
||||
char buttons;
|
||||
short dx;
|
||||
short dy;
|
||||
int ready;
|
||||
int active;
|
||||
wait_queue_head_t wait;
|
||||
struct fasync_struct *fasyncptr;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,77 +0,0 @@
|
|||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* mcfmbus.h -- Coldfire MBUS support defines.
|
||||
*
|
||||
* (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de)
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
|
||||
#ifndef mcfmbus_h
|
||||
#define mcfmbus_h
|
||||
|
||||
|
||||
#define MCFMBUS_BASE 0x280
|
||||
#define MCFMBUS_IRQ_VECTOR 0x19
|
||||
#define MCFMBUS_IRQ 0x1
|
||||
#define MCFMBUS_CLK 0x3f
|
||||
#define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/
|
||||
#define MCFMBUS_ADDRESS 0x01
|
||||
|
||||
|
||||
/*
|
||||
* Define the 5307 MBUS register set addresses
|
||||
*/
|
||||
|
||||
#define MCFMBUS_MADR 0x00
|
||||
#define MCFMBUS_MFDR 0x04
|
||||
#define MCFMBUS_MBCR 0x08
|
||||
#define MCFMBUS_MBSR 0x0C
|
||||
#define MCFMBUS_MBDR 0x10
|
||||
|
||||
|
||||
#define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/
|
||||
|
||||
#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/
|
||||
|
||||
/*
|
||||
* Define bit flags in Control Register
|
||||
*/
|
||||
|
||||
#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */
|
||||
#define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
|
||||
#define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */
|
||||
#define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */
|
||||
#define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
|
||||
#define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */
|
||||
|
||||
/*
|
||||
* Define bit flags in Status Register
|
||||
*/
|
||||
|
||||
#define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */
|
||||
#define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */
|
||||
#define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */
|
||||
#define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */
|
||||
#define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */
|
||||
#define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */
|
||||
#define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */
|
||||
|
||||
/*
|
||||
* Define bit flags in DATA I/O Register
|
||||
*/
|
||||
|
||||
#define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */
|
||||
|
||||
#define MBUSIOCSCLOCK 1
|
||||
#define MBUSIOCGCLOCK 2
|
||||
#define MBUSIOCSADDR 3
|
||||
#define MBUSIOCGADDR 4
|
||||
#define MBUSIOCSSLADDR 5
|
||||
#define MBUSIOCGSLADDR 6
|
||||
#define MBUSIOCSSUBADDR 7
|
||||
#define MBUSIOCGSUBADDR 8
|
||||
|
||||
#endif
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/*
|
||||
* some sbus structures and macros to make usage of sbus drivers possible
|
||||
*/
|
||||
|
||||
#ifndef __M68K_SBUS_H
|
||||
#define __M68K_SBUS_H
|
||||
|
||||
struct sbus_dev {
|
||||
struct {
|
||||
unsigned int which_io;
|
||||
unsigned int phys_addr;
|
||||
} reg_addrs[1];
|
||||
};
|
||||
|
||||
/* sbus IO functions stolen from include/asm-sparc/io.h for the serial driver */
|
||||
/* No SBUS on the Sun3, kludge -- sam */
|
||||
|
||||
static inline void _sbus_writeb(unsigned char val, unsigned long addr)
|
||||
{
|
||||
*(volatile unsigned char *)addr = val;
|
||||
}
|
||||
|
||||
static inline unsigned char _sbus_readb(unsigned long addr)
|
||||
{
|
||||
return *(volatile unsigned char *)addr;
|
||||
}
|
||||
|
||||
static inline void _sbus_writel(unsigned long val, unsigned long addr)
|
||||
{
|
||||
*(volatile unsigned long *)addr = val;
|
||||
|
||||
}
|
||||
|
||||
extern inline unsigned long _sbus_readl(unsigned long addr)
|
||||
{
|
||||
return *(volatile unsigned long *)addr;
|
||||
}
|
||||
|
||||
|
||||
#define sbus_readb(a) _sbus_readb((unsigned long)a)
|
||||
#define sbus_writeb(v, a) _sbus_writeb(v, (unsigned long)a)
|
||||
#define sbus_readl(a) _sbus_readl((unsigned long)a)
|
||||
#define sbus_writel(v, a) _sbus_writel(v, (unsigned long)a)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue