drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Liu
Alex Deucher
parent
b8f10585cb
commit
dfd57dbf44
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@ -159,7 +159,8 @@ amdgpu-y += \
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amdgpu_jpeg.o \
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jpeg_v1_0.o \
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jpeg_v2_0.o \
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jpeg_v2_5.o
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jpeg_v2_5.o \
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jpeg_v3_0.o
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# add ATHUB block
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amdgpu-y += \
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@ -0,0 +1,484 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_jpeg.h"
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#include "amdgpu_pm.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "jpeg_v2_0.h"
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#include "vcn/vcn_3_0_0_offset.h"
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#include "vcn/vcn_3_0_0_sh_mask.h"
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#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
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#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
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static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
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static int jpeg_v3_0_set_powergating_state(void *handle,
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enum amd_powergating_state state);
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/**
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* jpeg_v3_0_early_init - set function pointers
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*
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* @handle: amdgpu_device pointer
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*
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* Set ring and irq function pointers
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*/
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static int jpeg_v3_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->asic_type == CHIP_SIENNA_CICHLID) {
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u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
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if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
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return -ENOENT;
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}
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adev->jpeg.num_jpeg_inst = 1;
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jpeg_v3_0_set_dec_ring_funcs(adev);
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jpeg_v3_0_set_irq_funcs(adev);
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return 0;
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}
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/**
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* jpeg_v3_0_sw_init - sw init for JPEG block
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*
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* @handle: amdgpu_device pointer
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*
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* Load firmware and sw initialization
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*/
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static int jpeg_v3_0_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring;
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int r;
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/* JPEG TRAP */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
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if (r)
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return r;
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r = amdgpu_jpeg_sw_init(adev);
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if (r)
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return r;
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r = amdgpu_jpeg_resume(adev);
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if (r)
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return r;
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ring = &adev->jpeg.inst->ring_dec;
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ring->use_doorbell = true;
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
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sprintf(ring->name, "jpeg_dec");
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r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
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AMDGPU_RING_PRIO_DEFAULT);
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if (r)
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return r;
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adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
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adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
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return 0;
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}
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/**
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* jpeg_v3_0_sw_fini - sw fini for JPEG block
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*
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* @handle: amdgpu_device pointer
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*
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* JPEG suspend and free up sw allocation
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*/
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static int jpeg_v3_0_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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r = amdgpu_jpeg_suspend(adev);
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if (r)
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return r;
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r = amdgpu_jpeg_sw_fini(adev);
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return r;
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}
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/**
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* jpeg_v3_0_hw_init - start and test JPEG block
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*
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* @handle: amdgpu_device pointer
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*
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*/
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static int jpeg_v3_0_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
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int r;
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
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r = amdgpu_ring_test_helper(ring);
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if (r)
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return r;
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DRM_INFO("JPEG decode initialized successfully.\n");
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return 0;
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}
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/**
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* jpeg_v3_0_hw_fini - stop the hardware block
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*
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* @handle: amdgpu_device pointer
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*
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* Stop the JPEG block, mark ring as not ready any more
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*/
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static int jpeg_v3_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring;
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ring = &adev->jpeg.inst->ring_dec;
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if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
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jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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ring->sched.ready = false;
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return 0;
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}
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/**
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* jpeg_v3_0_suspend - suspend JPEG block
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*
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* @handle: amdgpu_device pointer
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*
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* HW fini and suspend JPEG block
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*/
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static int jpeg_v3_0_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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r = jpeg_v3_0_hw_fini(adev);
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if (r)
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return r;
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r = amdgpu_jpeg_suspend(adev);
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return r;
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}
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/**
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* jpeg_v3_0_resume - resume JPEG block
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*
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* @handle: amdgpu_device pointer
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*
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* Resume firmware and hw init JPEG block
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*/
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static int jpeg_v3_0_resume(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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r = amdgpu_jpeg_resume(adev);
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if (r)
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return r;
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r = jpeg_v3_0_hw_init(adev);
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return r;
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}
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/**
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* jpeg_v3_0_start - start JPEG block
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*
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* @adev: amdgpu_device pointer
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*
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* Setup and start the JPEG block
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*/
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static int jpeg_v3_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_jpeg(adev, true);
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/* MJPEG global tiling registers */
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WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
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adev->gfx.config.gb_addr_config);
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/* enable JMI channel */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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/* enable System Interrupt for JRBC */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
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JPEG_SYS_INT_EN__DJRBC_MASK,
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~JPEG_SYS_INT_EN__DJRBC_MASK);
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WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
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WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
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ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
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return 0;
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}
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/**
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* jpeg_v3_0_stop - stop JPEG block
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*
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* @adev: amdgpu_device pointer
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*
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* stop the JPEG block
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*/
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static int jpeg_v3_0_stop(struct amdgpu_device *adev)
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{
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/* reset JMI */
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WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
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UVD_JMI_CNTL__SOFT_RESET_MASK,
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~UVD_JMI_CNTL__SOFT_RESET_MASK);
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_jpeg(adev, false);
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return 0;
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}
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/**
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* jpeg_v3_0_dec_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
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}
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/**
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* jpeg_v3_0_dec_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring->use_doorbell)
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return adev->wb.wb[ring->wptr_offs];
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else
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return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
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}
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/**
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* jpeg_v3_0_dec_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring->use_doorbell) {
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adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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} else {
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WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
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}
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}
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static bool jpeg_v3_0_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 1;
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ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
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return ret;
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}
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static int jpeg_v3_0_wait_for_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret = 0;
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SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
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UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
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if (ret)
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return ret;
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return ret;
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}
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static int jpeg_v3_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int jpeg_v3_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret;
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if(state == adev->jpeg.cur_state)
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return 0;
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if (state == AMD_PG_STATE_GATE)
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ret = jpeg_v3_0_stop(adev);
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else
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ret = jpeg_v3_0_start(adev);
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if(!ret)
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adev->jpeg.cur_state = state;
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return ret;
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}
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static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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return 0;
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}
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static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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DRM_DEBUG("IH: JPEG TRAP\n");
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switch (entry->src_id) {
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case VCN_2_0__SRCID__JPEG_DECODE:
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amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
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break;
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default:
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DRM_ERROR("Unhandled interrupt: %d %d\n",
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entry->src_id, entry->src_data[0]);
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break;
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}
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return 0;
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}
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static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
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.name = "jpeg_v3_0",
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.early_init = jpeg_v3_0_early_init,
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.late_init = NULL,
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.sw_init = jpeg_v3_0_sw_init,
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.sw_fini = jpeg_v3_0_sw_fini,
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.hw_init = jpeg_v3_0_hw_init,
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.hw_fini = jpeg_v3_0_hw_fini,
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.suspend = jpeg_v3_0_suspend,
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.resume = jpeg_v3_0_resume,
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.is_idle = jpeg_v3_0_is_idle,
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.wait_for_idle = jpeg_v3_0_wait_for_idle,
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.check_soft_reset = NULL,
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.pre_soft_reset = NULL,
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.soft_reset = NULL,
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.post_soft_reset = NULL,
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.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
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.set_powergating_state = jpeg_v3_0_set_powergating_state,
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};
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static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_JPEG,
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.align_mask = 0xf,
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.vmhub = AMDGPU_MMHUB_0,
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.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
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.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
|
||||
.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
|
||||
.emit_frame_size =
|
||||
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
|
||||
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
|
||||
8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
|
||||
18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
|
||||
8 + 16,
|
||||
.emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
|
||||
.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
|
||||
.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
|
||||
.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
|
||||
.test_ring = amdgpu_jpeg_dec_ring_test_ring,
|
||||
.test_ib = amdgpu_jpeg_dec_ring_test_ib,
|
||||
.insert_nop = jpeg_v2_0_dec_ring_nop,
|
||||
.insert_start = jpeg_v2_0_dec_ring_insert_start,
|
||||
.insert_end = jpeg_v2_0_dec_ring_insert_end,
|
||||
.pad_ib = amdgpu_ring_generic_pad_ib,
|
||||
.begin_use = amdgpu_jpeg_ring_begin_use,
|
||||
.end_use = amdgpu_jpeg_ring_end_use,
|
||||
.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
|
||||
.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
|
||||
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
|
||||
};
|
||||
|
||||
static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
|
||||
DRM_INFO("JPEG decode is enabled in VM mode\n");
|
||||
}
|
||||
|
||||
static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
|
||||
.set = jpeg_v3_0_set_interrupt_state,
|
||||
.process = jpeg_v3_0_process_interrupt,
|
||||
};
|
||||
|
||||
static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->jpeg.inst->irq.num_types = 1;
|
||||
adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
|
||||
}
|
||||
|
||||
const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_JPEG,
|
||||
.major = 3,
|
||||
.minor = 0,
|
||||
.rev = 0,
|
||||
.funcs = &jpeg_v3_0_ip_funcs,
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __JPEG_V3_0_H__
|
||||
#define __JPEG_V3_0_H__
|
||||
|
||||
extern const struct amdgpu_ip_block_version jpeg_v3_0_ip_block;
|
||||
|
||||
#endif /* __JPEG_V3_0_H__ */
|
||||
Loading…
Reference in New Issue