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drm/amd/display: add mpc to dtn log 

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-01-24 14:28:30 -05:00 committed by Alex Deucher
parent a12c3b7d4e
commit dfd01f2999
4 changed files with 60 additions and 8 deletions
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31
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -121,20 +121,19 @@ void dcn10_log_hw_state(struct dc *dc)
dcn10_log_hubbub_state(dc);
DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
"rotation \t mirror \t sw_mode \t "
"dcc_en \t blank_en \t ttu_dis \t underflow \t "
"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
DTN_INFO("HUBP: format addr_hi width height "
"rotation mirror sw_mode "
"dcc_en blank_en ttu_dis underflow "
"min_ttu_vblank qos_low_wm qos_high_wm\n");
for (i = 0; i < pool->pipe_count; i++) {
struct hubp *hubp = pool->hubps[i];
struct dcn_hubp_state s;
hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
"%xh \t %xh \t %xh \t "
"%d \t %d \t %d \t %xh \t",
DTN_INFO("[%-2d]: %5xh %6xh %5d %6d "
"%7xh %5xh %6xh "
"%6d %8d %7d %8xh \t",
hubp->inst,
s.pixel_format,
s.inuse_addr_hi,
@ -153,6 +152,22 @@ void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("\n");
}
DTN_INFO("\n");
for (i = 0; i < pool->pipe_count; i++) {
struct output_pixel_processor *opp = pool->opps[i];
struct mpcc *mpcc = opp->mpc_tree_params.opp_list;
struct mpcc_state s = {0};
while (mpcc) {
ASSERT(opp->mpc_tree_params.opp_id == opp->inst);
pool->mpc->funcs->read_mpcc_state(pool->mpc, mpcc->mpcc_id, &s);
DTN_INFO("[OPP%d - MPCC%d]: DPP%d MPCCBOT%x MODE:%d ALPHA_MODE:%d PREMULT:%d OVERLAP_ONLY:%d\n",
s.opp_id, mpcc->mpcc_id, s.dpp_id, s.bot_mpcc_id,
s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only);
mpcc = mpcc->mpcc_bot;
ASSERT(!mpcc || mpcc->mpcc_id == s.bot_mpcc_id);
}
}
DTN_INFO("\n");
DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");

17
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
View File

@ -409,7 +409,24 @@ void mpc1_init_mpcc_list_from_hw(
}
}
void mpc1_read_mpcc_state(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->pre_multiplied_alpha);
}
const struct mpc_funcs dcn10_mpc_funcs = {
.read_mpcc_state = mpc1_read_mpcc_state,
.insert_plane = mpc1_insert_plane,
.remove_mpcc = mpc1_remove_mpcc,
.mpc_init = mpc1_mpc_init,

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
View File

@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp(
struct mpc_tree *tree,
int dpp_id);
void mpc1_read_mpcc_state(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s);
#endif

15
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
View File

@ -105,7 +105,22 @@ struct mpc {
struct mpcc mpcc_array[MAX_MPCC];
};
struct mpcc_state {
uint32_t opp_id;
uint32_t dpp_id;
uint32_t bot_mpcc_id;
uint32_t mode;
uint32_t alpha_mode;
uint32_t pre_multiplied_alpha;
uint32_t overlap_only;
};
struct mpc_funcs {
void (*read_mpcc_state)(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s);
/*
* Insert DPP into MPC tree based on specified blending position.
* Only used for planes that are part of blending chain for OPP output