SPI NOR Changes
Core changes:
- Add support of octal mode I/O transfer
- Add a bunch of SPI NOR entries to the flash_info table
SPI NOR controller driver changes:
- cadence-quadspi:
* Add support for Octal SPI controller
* write upto 8-bytes data in STIG mode
- mtk-quadspi:
* rename config to a common one
* add SNOR_HWCAPS_READ to spi_nor_hwcaps mask
MAINTAINERS:
- Add Tudor as SPI-NOR co-maintainer
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJcblqiAAoJEGXtNgF+CLcA01oQAI8obPo2l+DJrv3X7EcLViwb
7kIGWQjKKXxoA8KZ8t3XRpQIFg/J+TX1OPo75/ZeLIp2ikuvDRBFkX38RudI7lbn
cU1qLZFHcSPFGk8FlcwWmVEErgEGLif8ytCfyqlVFYwysVnam+UAmCvNAn3p3DIg
qkHtyd4gjoOw2lO+3f/UZlBGE/b4GIAO6EKZWpJdEd71eomgT8yqjqcSfBm2LQ3o
cpWsNhXUZMOvAVB3l1R/0O3n3gSuXYll8CrZQZU2rETGTMykfpZ/tLgTUl9WKTlk
RjjiSKaGebhanL1cM2M7kXPSk4Hm8bpvO64yEoMauFITsMvYkyVe2EAHspNmdBV7
SoLHrlk10C56wNKbl2PNOduz7MdawiaFmNy0Pp2EC7eJ9h03YbI/ORhi+oDg2Zhc
5Pdda5yJ/KVpheDA+9AvJtHVzTF8FOAC1qP+fS+IEmwGzG1yQxKjZz4QAH58OfV1
k5+JgExBimMDvtESoYyXQqMPo1FnWhLkRoVg7/tK3jMEPJO8Y/3j6KH8qyXFrDqZ
IiFbI8xQ3uXNFgbtjUWD9Nhd0UZEkCJi+P7niqMvaCcX/Uga7ob54Vvgp3EKDXDT
lp0mUPjnpL5CbL4XW7NUY1Yic3bvtkxBQDR6O4+urTrSwkLxqiqCdDzZCrFIrrPj
gPlsWD3CR4exwd0Ar8sg
=tTBK
-----END PGP SIGNATURE-----
Merge tag 'spi-nor/for-5.1' of git://git.infradead.org/linux-mtd into mtd/next
SPI NOR Changes
Core changes:
- Add support of octal mode I/O transfer
- Add a bunch of SPI NOR entries to the flash_info table
SPI NOR controller driver changes:
- cadence-quadspi:
* Add support for Octal SPI controller
* write upto 8-bytes data in STIG mode
- mtk-quadspi:
* rename config to a common one
* add SNOR_HWCAPS_READ to spi_nor_hwcaps mask
MAINTAINERS:
- Add Tudor as SPI-NOR co-maintainer
This commit is contained in:
Boris Brezillon
commit
dfbd39956a
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@ -4,6 +4,7 @@ Required properties:
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- compatible : should be one of the following:
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Generic default - "cdns,qspi-nor".
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For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
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For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
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- reg : Contains two entries, each of which is a tuple consisting of a
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physical address and length. The first entry is the address and
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length of the controller register set. The second entry is the
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@ -1,4 +1,4 @@
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* Serial NOR flash controller for MTK MT81xx (and similar)
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* Serial NOR flash controller for MediaTek SoCs
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Required properties:
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- compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
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@ -10,6 +10,7 @@ Required properties:
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"mediatek,mt2712-nor", "mediatek,mt8173-nor"
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"mediatek,mt7622-nor", "mediatek,mt8173-nor"
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"mediatek,mt7623-nor", "mediatek,mt8173-nor"
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"mediatek,mt7629-nor", "mediatek,mt8173-nor"
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"mediatek,mt8173-nor"
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- reg: physical base address and length of the controller's register
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- clocks: the phandle of the clocks needed by the nor controller
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@ -14303,6 +14303,7 @@ F: arch/arm/mach-spear/
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SPI NOR SUBSYSTEM
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M: Marek Vasut <marek.vasut@gmail.com>
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M: Tudor Ambarus <tudor.ambarus@microchip.com>
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L: linux-mtd@lists.infradead.org
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W: http://www.linux-mtd.infradead.org/
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Q: http://patchwork.ozlabs.org/project/linux-mtd/list/
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@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
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spi_mem_set_drvdata(spimem, flash);
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flash->spimem = spimem;
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if (spi->mode & SPI_RX_QUAD) {
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if (spi->mode & SPI_RX_OCTAL) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
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if (spi->mode & SPI_TX_OCTAL)
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hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
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SNOR_HWCAPS_PP_1_1_8 |
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SNOR_HWCAPS_PP_1_8_8);
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} else if (spi->mode & SPI_RX_QUAD) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
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if (spi->mode & SPI_TX_QUAD)
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@ -7,14 +7,6 @@ menuconfig MTD_SPI_NOR
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if MTD_SPI_NOR
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config MTD_MT81xx_NOR
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tristate "Mediatek MT81xx SPI NOR flash controller"
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depends on HAS_IOMEM
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help
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This enables access to SPI NOR flash, using MT81xx SPI NOR flash
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controller. This controller does not support generic SPI BUS, it only
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supports SPI NOR Flash.
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config MTD_SPI_NOR_USE_4K_SECTORS
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bool "Use small 4096 B erase sectors"
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default y
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@ -66,6 +58,14 @@ config SPI_HISI_SFC
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help
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This enables support for hisilicon SPI-NOR flash controller.
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config SPI_MTK_QUADSPI
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tristate "MediaTek Quad SPI controller"
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depends on HAS_IOMEM
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help
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This enables support for the Quad SPI controller in master mode.
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This controller does not support generic SPI. It only supports
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SPI NOR.
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config SPI_NXP_SPIFI
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tristate "NXP SPI Flash Interface (SPIFI)"
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depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
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@ -4,7 +4,7 @@ obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
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obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
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obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
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obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
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obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
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obj-$(CONFIG_SPI_MTK_QUADSPI) += mtk-quadspi.o
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obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
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obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
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obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
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@ -44,6 +44,12 @@
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/* Quirks */
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#define CQSPI_NEEDS_WR_DELAY BIT(0)
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/* Capabilities mask */
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#define CQSPI_BASE_HWCAPS_MASK \
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(SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | \
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SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_READ_1_1_4 | \
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SNOR_HWCAPS_PP)
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struct cqspi_st;
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struct cqspi_flash_pdata {
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@ -93,6 +99,11 @@ struct cqspi_st {
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struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
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};
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struct cqspi_driver_platdata {
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u32 hwcaps_mask;
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u8 quirks;
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};
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/* Operation timeout value */
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#define CQSPI_TIMEOUT_MS 500
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#define CQSPI_READ_TIMEOUT_MS 10
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@ -101,6 +112,7 @@ struct cqspi_st {
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#define CQSPI_INST_TYPE_SINGLE 0
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#define CQSPI_INST_TYPE_DUAL 1
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#define CQSPI_INST_TYPE_QUAD 2
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#define CQSPI_INST_TYPE_OCTAL 3
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#define CQSPI_DUMMY_CLKS_PER_BYTE 8
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#define CQSPI_DUMMY_BYTES_MAX 4
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@ -418,9 +430,10 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
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void __iomem *reg_base = cqspi->iobase;
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unsigned int reg;
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unsigned int data;
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u32 write_len;
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int ret;
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if (n_tx > 4 || (n_tx && !txbuf)) {
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if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
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dev_err(nor->dev,
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"Invalid input argument, cmdlen %d txbuf 0x%p\n",
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n_tx, txbuf);
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@ -433,10 +446,18 @@ static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
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reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
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<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
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data = 0;
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memcpy(&data, txbuf, n_tx);
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write_len = (n_tx > 4) ? 4 : n_tx;
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memcpy(&data, txbuf, write_len);
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txbuf += write_len;
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writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
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}
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if (n_tx > 4) {
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data = 0;
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write_len = n_tx - 4;
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memcpy(&data, txbuf, write_len);
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writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
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}
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}
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ret = cqspi_exec_flash_cmd(cqspi, reg);
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return ret;
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}
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@ -911,6 +932,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
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case SNOR_PROTO_1_1_4:
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f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
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break;
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case SNOR_PROTO_1_1_8:
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f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
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break;
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default:
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return -EINVAL;
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}
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@ -1213,21 +1237,23 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
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static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
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{
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const struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ |
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SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_READ_1_1_2 |
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SNOR_HWCAPS_READ_1_1_4 |
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SNOR_HWCAPS_PP,
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};
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struct platform_device *pdev = cqspi->pdev;
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struct device *dev = &pdev->dev;
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const struct cqspi_driver_platdata *ddata;
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struct spi_nor_hwcaps hwcaps;
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struct cqspi_flash_pdata *f_pdata;
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struct spi_nor *nor;
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struct mtd_info *mtd;
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unsigned int cs;
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int i, ret;
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ddata = of_device_get_match_data(dev);
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if (!ddata) {
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dev_err(dev, "Couldn't find driver data\n");
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return -EINVAL;
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}
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hwcaps.mask = ddata->hwcaps_mask;
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/* Get flash device data */
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for_each_available_child_of_node(dev->of_node, np) {
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ret = of_property_read_u32(np, "reg", &cs);
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@ -1310,7 +1336,7 @@ static int cqspi_probe(struct platform_device *pdev)
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struct cqspi_st *cqspi;
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struct resource *res;
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struct resource *res_ahb;
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unsigned long data;
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const struct cqspi_driver_platdata *ddata;
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int ret;
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int irq;
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@ -1377,8 +1403,8 @@ static int cqspi_probe(struct platform_device *pdev)
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}
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cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
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data = (unsigned long)of_device_get_match_data(dev);
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if (data & CQSPI_NEEDS_WR_DELAY)
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ddata = of_device_get_match_data(dev);
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if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
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cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
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cqspi->master_ref_clk_hz);
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@ -1460,14 +1486,32 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
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#define CQSPI_DEV_PM_OPS NULL
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#endif
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static const struct cqspi_driver_platdata cdns_qspi = {
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.hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
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};
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static const struct cqspi_driver_platdata k2g_qspi = {
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.hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
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.quirks = CQSPI_NEEDS_WR_DELAY,
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};
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static const struct cqspi_driver_platdata am654_ospi = {
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.hwcaps_mask = CQSPI_BASE_HWCAPS_MASK | SNOR_HWCAPS_READ_1_1_8,
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.quirks = CQSPI_NEEDS_WR_DELAY,
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};
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static const struct of_device_id cqspi_dt_ids[] = {
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{
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.compatible = "cdns,qspi-nor",
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.data = (void *)0,
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.data = &cdns_qspi,
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},
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{
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.compatible = "ti,k2g-qspi",
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.data = (void *)CQSPI_NEEDS_WR_DELAY,
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.data = &k2g_qspi,
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},
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{
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.compatible = "ti,am654-ospi",
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.data = &am654_ospi,
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},
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{ /* end of table */ }
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};
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|
|
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@ -431,7 +431,8 @@ static int mtk_nor_init(struct mtk_nor *mtk_nor,
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struct device_node *flash_node)
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{
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const struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ_FAST |
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.mask = SNOR_HWCAPS_READ |
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SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_READ_1_1_2 |
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SNOR_HWCAPS_PP,
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};
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|
|
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@ -68,7 +68,7 @@ enum spi_nor_read_command_index {
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octo SPI */
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/* Octal SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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|
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@ -85,7 +85,7 @@ enum spi_nor_pp_command_index {
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octo SPI */
|
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/* Octal SPI */
|
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SNOR_CMD_PP_1_1_8,
|
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SNOR_CMD_PP_1_8_8,
|
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SNOR_CMD_PP_8_8_8,
|
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|
|
@ -278,6 +278,7 @@ struct flash_info {
|
|||
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
|
||||
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
|
||||
#define USE_CLSR BIT(14) /* use CLSR command */
|
||||
#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
|
||||
|
||||
/* Part specific fixup hooks. */
|
||||
const struct spi_nor_fixups *fixups;
|
||||
|
|
@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
|
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{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
|
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{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
|
||||
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
|
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{ SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
|
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{ SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
|
||||
|
||||
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
|
||||
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
|
||||
|
|
@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
|
|||
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
|
||||
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
|
||||
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
|
||||
{ SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
|
||||
{ SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
|
||||
};
|
||||
|
||||
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
|
||||
|
|
@ -1740,7 +1745,11 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
||||
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
||||
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16,
|
||||
SECT_4K | SPI_NOR_DUAL_READ) },
|
||||
{ "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
|
||||
{ "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128,
|
||||
SECT_4K | SPI_NOR_DUAL_READ) },
|
||||
{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
|
||||
{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
|
||||
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
||||
|
|
@ -1836,6 +1845,8 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
|
||||
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
|
||||
{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
|
||||
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
|
||||
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
||||
|
|
@ -1847,6 +1858,8 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
|
||||
.fixups = &mx25l25635_fixups },
|
||||
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
|
||||
{ "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
|
||||
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
|
|
@ -1872,7 +1885,8 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
/* Micron */
|
||||
{
|
||||
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
|
||||
SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
|
||||
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
|
||||
SPI_NOR_4B_OPCODES)
|
||||
},
|
||||
|
||||
/* PMC */
|
||||
|
|
@ -1885,13 +1899,17 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
*/
|
||||
{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
|
||||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
|
||||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
|
||||
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
|
||||
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
|
||||
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
|
||||
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
|
||||
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
|
||||
|
|
@ -3591,6 +3609,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
|
|||
SNOR_PROTO_1_1_4);
|
||||
}
|
||||
|
||||
if (info->flags & SPI_NOR_OCTAL_READ) {
|
||||
params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
|
||||
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
|
||||
0, 8, SPINOR_OP_READ_1_1_8,
|
||||
SNOR_PROTO_1_1_8);
|
||||
}
|
||||
|
||||
/* Page Program settings. */
|
||||
params->hwcaps.mask |= SNOR_HWCAPS_PP;
|
||||
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
|
||||
|
|
|
|||
|
|
@ -46,9 +46,13 @@
|
|||
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
|
||||
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
|
||||
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
|
||||
#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
|
||||
#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
|
||||
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
|
||||
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
|
||||
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
|
||||
#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
|
||||
#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
|
||||
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
|
||||
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
|
||||
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
|
||||
|
|
@ -69,9 +73,13 @@
|
|||
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
|
||||
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
|
||||
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
|
||||
#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
|
||||
#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
|
||||
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
|
||||
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
|
||||
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
|
||||
#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
|
||||
#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
|
||||
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
|
||||
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
|
||||
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
|
||||
|
|
@ -458,7 +466,7 @@ struct spi_nor_hwcaps {
|
|||
/*
|
||||
*(Fast) Read capabilities.
|
||||
* MUST be ordered by priority: the higher bit position, the higher priority.
|
||||
* As a matter of performances, it is relevant to use Octo SPI protocols first,
|
||||
* As a matter of performances, it is relevant to use Octal SPI protocols first,
|
||||
* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
|
||||
* (Slow) Read.
|
||||
*/
|
||||
|
|
@ -479,7 +487,7 @@ struct spi_nor_hwcaps {
|
|||
#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
|
||||
#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
|
||||
|
||||
#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
|
||||
#define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
|
||||
#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
|
||||
#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
|
||||
#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
|
||||
|
|
@ -488,7 +496,7 @@ struct spi_nor_hwcaps {
|
|||
/*
|
||||
* Page Program capabilities.
|
||||
* MUST be ordered by priority: the higher bit position, the higher priority.
|
||||
* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
|
||||
* Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
|
||||
* legacy SPI 1-1-1 protocol.
|
||||
* Note that Dual Page Programs are not supported because there is no existing
|
||||
* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
|
||||
|
|
@ -502,7 +510,7 @@ struct spi_nor_hwcaps {
|
|||
#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
|
||||
#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
|
||||
|
||||
#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
|
||||
#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
|
||||
#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
|
||||
#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
|
||||
#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
|
||||
|
|
|
|||
Loading…
Reference in New Issue