dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
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title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
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maintainers:
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maintainers:
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- Melody Olvera <quic_molvera@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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- Imran Shaik <quic_imrashai@quicinc.com>
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description: |
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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Qualcomm global clock control module which supports the clocks, resets and
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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/*
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
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#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
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#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
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#define GCC_PCIE_0_PIPE_CLK_SRC 129
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#define GCC_PCIE_0_PIPE_CLK_SRC 129
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#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
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#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
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#define GCC_GPLL1_OUT_EVEN 131
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#define GCC_DDRSS_ECPRI_GSI_CLK 132
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/* GCC resets */
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/* GCC resets */
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#define GCC_ECPRI_CC_BCR 0
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#define GCC_ECPRI_CC_BCR 0
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