Merge series "ASoC: remove cppchecks warnings on lm49453 and da732x" from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
There are the last two patches in the cleanups, this time I am not sure what the code does and what the proper fix might be. Feedback welcome. Pierre-Louis Bossart (2): ASoC: lm49453: fix useless assignment before return ASoC: da732x: simplify code sound/soc/codecs/da732x.c | 17 ++++++----------- sound/soc/codecs/da732x.h | 12 ++++-------- sound/soc/codecs/lm49453.c | 2 -- 3 files changed, 10 insertions(+), 21 deletions(-) -- 2.25.1
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df421a3a6f
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@ -168,30 +168,25 @@ static const struct reg_default da732x_reg_cache[] = {
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static inline int da732x_get_input_div(struct snd_soc_component *component, int sysclk)
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{
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int val;
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int ret;
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if (sysclk < DA732X_MCLK_10MHZ) {
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val = DA732X_MCLK_RET_0_10MHZ;
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ret = DA732X_MCLK_VAL_0_10MHZ;
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val = DA732X_MCLK_VAL_0_10MHZ;
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} else if ((sysclk >= DA732X_MCLK_10MHZ) &&
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(sysclk < DA732X_MCLK_20MHZ)) {
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val = DA732X_MCLK_RET_10_20MHZ;
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ret = DA732X_MCLK_VAL_10_20MHZ;
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val = DA732X_MCLK_VAL_10_20MHZ;
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} else if ((sysclk >= DA732X_MCLK_20MHZ) &&
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(sysclk < DA732X_MCLK_40MHZ)) {
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val = DA732X_MCLK_RET_20_40MHZ;
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ret = DA732X_MCLK_VAL_20_40MHZ;
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val = DA732X_MCLK_VAL_20_40MHZ;
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} else if ((sysclk >= DA732X_MCLK_40MHZ) &&
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(sysclk <= DA732X_MCLK_54MHZ)) {
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val = DA732X_MCLK_RET_40_54MHZ;
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ret = DA732X_MCLK_VAL_40_54MHZ;
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val = DA732X_MCLK_VAL_40_54MHZ;
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} else {
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return -EINVAL;
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}
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snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val);
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return ret;
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return val;
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}
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static void da732x_set_charge_pump(struct snd_soc_component *component, int state)
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@ -1158,7 +1153,7 @@ static int da732x_set_dai_pll(struct snd_soc_component *component, int pll_id,
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if (indiv < 0)
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return indiv;
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fref = (da732x->sysclk / indiv);
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fref = da732x->sysclk / BIT(indiv);
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div_hi = freq_out / fref;
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frac_div = (u64)(freq_out % fref) * 8192ULL;
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do_div(frac_div, fref);
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@ -48,14 +48,10 @@
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#define DA732X_MCLK_20MHZ 20000000
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#define DA732X_MCLK_40MHZ 40000000
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#define DA732X_MCLK_54MHZ 54000000
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#define DA732X_MCLK_RET_0_10MHZ 0
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#define DA732X_MCLK_VAL_0_10MHZ 1
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#define DA732X_MCLK_RET_10_20MHZ 1
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#define DA732X_MCLK_VAL_10_20MHZ 2
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#define DA732X_MCLK_RET_20_40MHZ 2
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#define DA732X_MCLK_VAL_20_40MHZ 4
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#define DA732X_MCLK_RET_40_54MHZ 3
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#define DA732X_MCLK_VAL_40_54MHZ 8
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#define DA732X_MCLK_VAL_0_10MHZ 0
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#define DA732X_MCLK_VAL_10_20MHZ 1
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#define DA732X_MCLK_VAL_20_40MHZ 2
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#define DA732X_MCLK_VAL_40_54MHZ 3
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#define DA732X_DAI_ID1 0
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#define DA732X_DAI_ID2 1
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#define DA732X_SRCCLK_PLL 0
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@ -1206,8 +1206,6 @@ static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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break;
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case 48000:
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case 32576:
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/* fll clk slection */
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pll_clk = BIT(4);
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return 0;
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default:
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return -EINVAL;
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