ARM: OMAP: add SoSSI clock
This is needed, so that disabling the SoSSI clock during idle can be prevented. Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -49,6 +49,15 @@ static void omap1_uart_recalc(struct clk * clk)
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clk->rate = 12000000;
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}
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static void omap1_sossi_recalc(struct clk *clk)
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{
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u32 div = omap_readl(MOD_CONF_CTRL_1);
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div = (div >> 17) & 0x7;
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div++;
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clk->rate = clk->parent->rate / div;
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}
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static int omap1_clk_enable_dsp_domain(struct clk *clk)
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{
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int retval;
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@ -396,6 +405,31 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
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return 0;
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}
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static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
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{
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u32 l;
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int div;
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unsigned long p_rate;
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p_rate = clk->parent->rate;
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/* Round towards slower frequency */
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div = (p_rate + rate - 1) / rate;
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div--;
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if (div < 0 || div > 7)
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return -EINVAL;
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l = omap_readl(MOD_CONF_CTRL_1);
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l &= ~(7 << 17);
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l |= div << 17;
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omap_writel(l, MOD_CONF_CTRL_1);
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clk->rate = p_rate / (div + 1);
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if (unlikely(clk->flags & RATE_PROPAGATES))
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propagate_rate(clk);
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return 0;
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}
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static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
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{
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return 96000000 / calc_ext_dsor(rate);
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@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk);
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static void omap1_clk_disable_generic(struct clk * clk);
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static void omap1_ckctl_recalc(struct clk * clk);
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static void omap1_watchdog_recalc(struct clk * clk);
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static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
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static void omap1_sossi_recalc(struct clk *clk);
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static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
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static int omap1_clk_enable_dsp_domain(struct clk * clk);
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static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
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@ -170,7 +172,8 @@ static struct arm_idlect1_clk ck_dpll1out = {
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.clk = {
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.name = "ck_dpll1out",
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
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ENABLE_REG_32BIT | RATE_PROPAGATES,
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.enable_reg = (void __iomem *)ARM_IDLECT2,
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.enable_bit = EN_CKOUT_ARM,
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.recalc = &followparent_recalc,
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@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = {
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.idlect_shift = 12,
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};
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static struct clk sossi_ck = {
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.name = "ck_sossi",
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.parent = &ck_dpll1out.clk,
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.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
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ENABLE_REG_32BIT,
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.enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
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.enable_bit = 16,
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.recalc = &omap1_sossi_recalc,
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.set_rate = &omap1_set_sossi_rate,
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.enable = &omap1_clk_enable_generic,
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.disable = &omap1_clk_disable_generic,
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};
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static struct clk arm_ck = {
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.name = "arm_ck",
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.parent = &ck_dpll1,
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@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = {
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&ck_dpll1,
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/* CK_GEN1 clocks */
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&ck_dpll1out.clk,
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&sossi_ck,
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&arm_ck,
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&armper_ck.clk,
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&arm_gpio_ck,
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