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drm/i915: Fix current tiling check for relaxed fencing 

As we may bind an object with the correct alignment, but with an invalid
size, it may pass the current checks on whether the object may be reused
with a fence.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-11-15 05:25:58 +00:00
parent 5e78330126
commit df15315899
1 changed files with 14 additions and 8 deletions
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22
drivers/gpu/drm/i915/i915_gem_tiling.c
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@ -245,6 +245,17 @@ i915_gem_object_fence_ok(struct drm_gem_object *obj, int tiling_mode)
if (INTEL_INFO(obj->dev)->gen >= 4)
return true;
if (!obj_priv->gtt_space)
return true;
if (INTEL_INFO(obj->dev)->gen == 3) {
if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
return false;
} else {
if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
return false;
}
/*
* Previous chips need to be aligned to the size of the smallest
* fence register that can contain the object.
@ -257,16 +268,11 @@ i915_gem_object_fence_ok(struct drm_gem_object *obj, int tiling_mode)
while (size < obj_priv->base.size)
size <<= 1;
if (obj_priv->gtt_offset & (size - 1))
if (obj_priv->gtt_space->size != size)
return false;
if (INTEL_INFO(obj->dev)->gen == 3) {
if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
return false;
} else {
if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
return false;
}
if (obj_priv->gtt_offset & (size - 1))
return false;
return true;
}