Merge branch 'stmmac-eam'
Thierry Reding says: ==================== net: stmmac: Enhanced addressing mode for DWMAC 4.10 The DWMAC 4.10 supports the same enhanced addressing mode as later generations. Parse this capability from the hardware feature registers and set the EAME (Enhanced Addressing Mode Enable) bit when necessary. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
df1025fc27
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@ -205,6 +205,7 @@ enum power_event {
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#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
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#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
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#define GMAC_HW_FEAT_AVSEL BIT(20)
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#define GMAC_HW_FEAT_AVSEL BIT(20)
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#define GMAC_HW_TSOEN BIT(18)
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#define GMAC_HW_TSOEN BIT(18)
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#define GMAC_HW_ADDR64 GENMASK(15, 14)
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#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
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#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
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#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
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#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
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@ -431,8 +431,8 @@ static void dwmac4_get_addr(struct dma_desc *p, unsigned int *addr)
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static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
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static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
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{
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{
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p->des0 = cpu_to_le32(addr);
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p->des0 = cpu_to_le32(lower_32_bits(addr));
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p->des1 = 0;
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p->des1 = cpu_to_le32(upper_32_bits(addr));
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}
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}
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static void dwmac4_clear(struct dma_desc *p)
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static void dwmac4_clear(struct dma_desc *p)
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@ -79,6 +79,10 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
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value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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writel(upper_32_bits(dma_rx_phy),
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ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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}
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}
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@ -97,6 +101,10 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
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writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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writel(upper_32_bits(dma_tx_phy),
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ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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}
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}
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@ -132,6 +140,9 @@ static void dwmac4_dma_init(void __iomem *ioaddr,
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if (dma_cfg->aal)
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if (dma_cfg->aal)
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value |= DMA_SYS_BUS_AAL;
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value |= DMA_SYS_BUS_AAL;
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if (dma_cfg->eame)
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value |= DMA_SYS_BUS_EAME;
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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}
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}
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@ -356,6 +367,23 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
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dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
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dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
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dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
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switch (dma_cap->addr64) {
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case 0:
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dma_cap->addr64 = 32;
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break;
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case 1:
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dma_cap->addr64 = 40;
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break;
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case 2:
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dma_cap->addr64 = 48;
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break;
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default:
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dma_cap->addr64 = 32;
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break;
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}
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/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
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/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
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* shifting and store the sizes in bytes.
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* shifting and store the sizes in bytes.
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*/
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*/
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@ -65,6 +65,7 @@
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#define DMA_SYS_BUS_MB BIT(14)
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#define DMA_SYS_BUS_MB BIT(14)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_SYS_BUS_AAL BIT(12)
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#define DMA_SYS_BUS_AAL BIT(12)
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#define DMA_SYS_BUS_EAME BIT(11)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN64 BIT(5)
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@ -91,7 +92,9 @@
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#define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x)
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#define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x)
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#define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4)
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#define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4)
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#define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8)
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#define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8)
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#define DMA_CHAN_TX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x10)
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#define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14)
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#define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14)
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#define DMA_CHAN_RX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x18)
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#define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c)
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#define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c)
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#define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20)
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#define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20)
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#define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)
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#define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)
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@ -27,7 +27,10 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,
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if (dma_cfg->aal)
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if (dma_cfg->aal)
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value |= XGMAC_AAL;
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value |= XGMAC_AAL;
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writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE);
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if (dma_cfg->eame)
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value |= XGMAC_EAME;
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writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
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}
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}
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static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
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static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
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@ -4514,6 +4514,13 @@ int stmmac_dvr_probe(struct device *device,
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if (!ret) {
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if (!ret) {
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dev_info(priv->device, "Using %d bits DMA width\n",
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dev_info(priv->device, "Using %d bits DMA width\n",
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priv->dma_cap.addr64);
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priv->dma_cap.addr64);
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/*
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* If more than 32 bits can be addressed, make sure to
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* enable enhanced addressing mode.
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*/
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if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
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priv->plat->dma_cfg->eame = true;
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} else {
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} else {
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ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
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ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
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if (ret) {
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if (ret) {
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@ -92,6 +92,7 @@ struct stmmac_dma_cfg {
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int fixed_burst;
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int fixed_burst;
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int mixed_burst;
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int mixed_burst;
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bool aal;
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bool aal;
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bool eame;
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};
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};
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#define AXI_BLEN 7
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#define AXI_BLEN 7
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