From 49a9b0be292c095ac28bd81c1011d14e8437b72d Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:05 +0100 Subject: [PATCH 1/8] ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 102 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 102 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 6a7383f24c7c..651aeb5ef439 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -122,6 +122,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; From c0d1c266a1cc1b7256ade6ad7d92ecb1a9f4895b Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:15 +0100 Subject: [PATCH 2/8] ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 104 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 104 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 272e2e2fc58f..4e27587667bf 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -117,6 +117,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; From 797090dfca7fbdd69752425693eda19b28cb5db5 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:27 +0100 Subject: [PATCH 3/8] ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 2120 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 2120 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index f048b4ee4d52..ff049ee862eb 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -174,6 +174,11 @@ clock-frequency = <400000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + /* Controller for rear fan #1 of 3 (Protechnic * MGT4012XB-O20, 8000RPM) near eSATA port */ g762_fan1: g762@3e { From 0ad82cd81b00d9a7c6d183ef955947b5bc5eef9e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 17 Dec 2013 21:21:52 +0100 Subject: [PATCH 4/8] Phy: Add DT nodes on kirkwood and Dove for the SATA PHY Add nodes for the two SATA PHYs on kirkwood. Add node for the one SATA PHY on Dove. Add pHandles to the PHYs in the sata nodes. Signed-off-by: Andrew Lunn Acked-by: Kishon Vijay Abraham I Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 11 +++++++++++ arch/arm/boot/dts/kirkwood-6281.dtsi | 2 ++ arch/arm/boot/dts/kirkwood-6282.dtsi | 2 ++ arch/arm/boot/dts/kirkwood.dtsi | 18 ++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 852db2860015..8de1031233ae 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -336,10 +336,21 @@ reg = <0xa0000 0x2400>; interrupts = <62>; clocks = <&gate_clk 3>; + phys = <&sata_phy0>; + phy-names = "port0"; nr-ports = <1>; status = "disabled"; }; + sata_phy0: sata-phy@a2000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0xa2000 0x0334>; + clocks = <&gate_clk 3>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + audio0: audio-controller@b0000 { compatible = "marvell,dove-audio"; reg = <0xb0000 0x2210>; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index e4e1968dfca8..416d96e1302f 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -89,6 +89,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index f010c21220bf..a4fec0432168 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -117,6 +117,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 1da94c187085..81e6c409284e 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -284,5 +284,23 @@ /* set phy-handle property in board file */ }; }; + + sata_phy0: sata-phy@82000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x82000 0x0334>; + clocks = <&gate_clk 14>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + + sata_phy1: sata-phy@84000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x84000 0x0334>; + clocks = <&gate_clk 15>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; }; }; From d8e0a2b65a78f97901fb9a1da08a79f50d7fc25a Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Sun, 22 Dec 2013 17:16:36 +0000 Subject: [PATCH 5/8] ARM: kirkwood: 6282: sort DT nodes by address We recently sorted the nodes in dove, orion5x, kirkwood, and armada 370/xp. However, I missed this file. -6281 is fine. Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6282.dtsi | 35 ++++++++++++++-------------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index a4fec0432168..2902e0d7971d 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -104,6 +104,12 @@ }; }; + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; @@ -111,6 +117,17 @@ clocks = <&gate_clk 7>; }; + i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + status = "disabled"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; @@ -135,23 +152,5 @@ cap-mmc-highspeed; status = "disabled"; }; - - thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - status = "disabled"; - }; - }; }; From 72c3e2295c1955b9d188dbaf910bc67a4dc2e3e5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 23 Dec 2013 09:48:10 +0100 Subject: [PATCH 6/8] ARM: mvebu: fix register length for Armada XP PMSU The per-CPU PMSU registers documented in the datasheet start at 0x22100 and the last register for CPU3 is at 0x22428. However, the DT informations use <0x22100 0x430>, which makes the region end at 0x22530 and not 0x22430. Moreover, looking at the datasheet, we can see that the registers for CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have been used per CPU. Therefore, this commit reduces the length of the PMSU per-CPU register area from the incorrect 0x430 bytes to a more logical 0x400 bytes. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 4919fb82ac62..b8b84a22f0f3 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -113,7 +113,7 @@ armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x430>, <0x20800 0x20>; + reg = <0x22100 0x400>, <0x20800 0x20>; }; eth2: ethernet@30000 { From e38cd3ae6e6f2bd5d376bc146d9f129402b82158 Mon Sep 17 00:00:00 2001 From: Maxime Hadjinlian Date: Tue, 24 Dec 2013 13:53:18 +0100 Subject: [PATCH 7/8] ARM: Kirkwood: Add 6192 DTSI file This file is mainly a copy of kirkwood-6281.dtsi. The pinctrl seems to be the same. These platforms differs only with their CPU, memory capabilities and the number of GPIO available (36 on 6192, 50 on 6281). Signed-off-by: Maxime Hadjinlian Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 107 +++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-6192.dtsi diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi new file mode 100644 index 000000000000..3916937d6818 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -0,0 +1,107 @@ +/ { + mbus { + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f6192-pinctrl"; + reg = <0x10000 0x20>; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", + "mpp19"; + marvell,function = "nand"; + }; + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; From 2cc64b5655da65bbb6a760a722b5ab1f53f92cf7 Mon Sep 17 00:00:00 2001 From: Maxime Hadjinlian Date: Tue, 24 Dec 2013 13:53:19 +0100 Subject: [PATCH 8/8] ARM: Kirkwood: DT board setup for LaPlug This patch adds DT board setup for the LaCie NAS LaPlug. Chipset list: - CPU MARVELL 88FR131 800Mhz - SDRAM memory: 128MB DDR2-800 400Mhz - 1 Ethernet Gigabit port (PHY MARVELL 88E1318) - 1 Mini PCI-Express port - 1 NAND 512 MB - 1 push button - 2 LEDs (red and blue) - 4 USB Ports Signed-off-by: Maxime Hadjinlian Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-laplug.dts | 175 ++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-laplug.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adcc6067eb13..09067804035f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ kirkwood-km_kirkwood.dtb \ + kirkwood-laplug.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts new file mode 100644 index 000000000000..c9e82eff9bf2 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2013 Maxime Hadjinlian + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "LaCie LaPlug"; + compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + i2c@11000 { + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "at,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + }; + + pinctrl: pinctrl@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button@1{ + label = "Power push button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "laplug_v2:red:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-power { + label = "laplug_v2:blue:power"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power_back1: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power Back 1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + usb_power_back2: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power Back 2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + + usb_power_front: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "USB Power Front"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + /* Total size : 512MB */ + status = "okay"; + pinctrl-0 = <&pmx_nand>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; /* 16MB */ + }; + + partition@1100000 { + label = "rootfs"; + reg = <0x1100000 0x1EF00000>; /* 495MB */ + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +};