MIPS: ralink: mt7620: Improve clock frequency detection
The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Gabor Juhos
Ralf Baechle
parent
2b9dbb15a9
commit
ded1e9d727
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@ -20,6 +20,8 @@
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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@ -29,20 +31,42 @@
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#define MT7620A_CHIP_NAME0 0x3637544d
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#define MT7620A_CHIP_NAME1 0x20203032
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#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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#define CHIP_REV_VER_MASK 0xf
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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#define CPLL_SW_CONFIG_SHIFT 31
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#define CPLL_SW_CONFIG_MASK 0x1
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#define CPLL_CPU_CLK_SHIFT 24
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#define CPLL_CPU_CLK_MASK 0x1
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#define CPLL_MULT_RATIO_SHIFT 16
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#define CPLL_MULT_RATIO 0x7
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#define CPLL_DIV_RATIO_SHIFT 10
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#define CPLL_DIV_RATIO 0x3
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#define CLKCFG0_PERI_CLK_SEL BIT(4)
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#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
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#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
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#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
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#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
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#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
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#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
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#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
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#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
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#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
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#define CPLL_CFG0_SW_CFG BIT(31)
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#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
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#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
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#define CPLL_CFG0_LC_CURFCK BIT(15)
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#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
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#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
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#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
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#define CPLL_CFG1_CPU_AUX1 BIT(25)
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#define CPLL_CFG1_CPU_AUX0 BIT(24)
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#define SYSCFG0_DRAM_TYPE_MASK 0x3
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#define SYSCFG0_DRAM_TYPE_SHIFT 4
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@ -23,9 +23,6 @@
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/* does the board have sdram or ddram */
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static int dram_type;
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/* the pll dividers */
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static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
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static struct ralink_pinmux_grp mode_mux[] = {
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{
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.name = "i2c",
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@ -140,34 +137,187 @@ struct ralink_pinmux rt_gpio_pinmux = {
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.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
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};
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static __init u32
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mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
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{
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u64 t;
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t = ref_rate;
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t *= mul;
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do_div(t, div);
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return t;
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}
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#define MHZ(x) ((x) * 1000 * 1000)
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static __init unsigned long
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mt7620_get_xtal_rate(void)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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if (reg & SYSCFG0_XTAL_FREQ_SEL)
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return MHZ(40);
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return MHZ(20);
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}
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static __init unsigned long
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mt7620_get_periph_rate(unsigned long xtal_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
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if (reg & CLKCFG0_PERI_CLK_SEL)
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return xtal_rate;
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return MHZ(40);
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}
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static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
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static __init unsigned long
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mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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if (reg & CPLL_CFG0_BYPASS_REF_CLK)
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return xtal_rate;
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if ((reg & CPLL_CFG0_SW_CFG) == 0)
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return MHZ(600);
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mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
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CPLL_CFG0_PLL_MULT_RATIO_MASK;
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mul += 24;
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if (reg & CPLL_CFG0_LC_CURFCK)
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mul *= 2;
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div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
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CPLL_CFG0_PLL_DIV_RATIO_MASK;
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WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
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return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
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}
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static __init unsigned long
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mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
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{
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u32 reg;
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reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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if (reg & CPLL_CFG1_CPU_AUX1)
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return xtal_rate;
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if (reg & CPLL_CFG1_CPU_AUX0)
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return MHZ(480);
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return cpu_pll_rate;
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}
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static __init unsigned long
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mt7620_get_cpu_rate(unsigned long pll_rate)
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{
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u32 reg;
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u32 mul;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
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div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
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CPU_SYS_CLKCFG_CPU_FDIV_MASK;
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return mt7620_calc_rate(pll_rate, mul, div);
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}
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static const u32 mt7620_ocp_dividers[16] __initconst = {
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[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
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[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
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[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
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[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
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[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
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};
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static __init unsigned long
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mt7620_get_dram_rate(unsigned long pll_rate)
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{
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if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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return pll_rate / 4;
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return pll_rate / 3;
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}
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static __init unsigned long
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mt7620_get_sys_rate(unsigned long cpu_rate)
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{
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u32 reg;
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u32 ocp_ratio;
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u32 div;
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reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
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ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
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CPU_SYS_CLKCFG_OCP_RATIO_MASK;
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if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
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return cpu_rate;
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div = mt7620_ocp_dividers[ocp_ratio];
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if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
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return cpu_rate;
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return cpu_rate / div;
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}
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate;
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u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
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u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
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u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
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u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
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unsigned long xtal_rate;
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unsigned long cpu_pll_rate;
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unsigned long pll_rate;
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unsigned long cpu_rate;
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unsigned long sys_rate;
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unsigned long dram_rate;
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unsigned long periph_rate;
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if (cpu_clk) {
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cpu_rate = 480000000;
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} else if (!swconfig) {
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cpu_rate = 600000000;
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} else {
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u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
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u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
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xtal_rate = mt7620_get_xtal_rate();
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cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
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}
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cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
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pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
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if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
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sys_rate = cpu_rate / 4;
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else
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sys_rate = cpu_rate / 3;
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cpu_rate = mt7620_get_cpu_rate(pll_rate);
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dram_rate = mt7620_get_dram_rate(pll_rate);
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sys_rate = mt7620_get_sys_rate(cpu_rate);
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periph_rate = mt7620_get_periph_rate(xtal_rate);
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#define RFMT(label) label ":%lu.%03luMHz "
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
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RINT(xtal_rate), RFRAC(xtal_rate),
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RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
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RINT(pll_rate), RFRAC(pll_rate));
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pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
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RINT(cpu_rate), RFRAC(cpu_rate),
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RINT(dram_rate), RFRAC(dram_rate),
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RINT(sys_rate), RFRAC(sys_rate),
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RINT(periph_rate), RFRAC(periph_rate));
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#undef RFRAC
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#undef RINT
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#undef RFMT
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", 40000000);
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ralink_clk_add("10000500.uart", 40000000);
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ralink_clk_add("10000c00.uartlite", 40000000);
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000500.uart", periph_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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}
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void __init ralink_of_remap(void)
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