gpio: pci-idio-16: Fix PCI BAR index
The PCI BAR0 and BAR1 for the PCI-IDIO-16 hold information for the PLX
9052 bridge chip on the device. The PCI BAR2 holds the necessary base
address for I/O control of the PCI-IDIO-16. This patch corrects the PCI
BAR index mismatch for the PCI-IDIO-16 GPIO driver.
Fixes: 02e74fc040
("gpio: Add GPIO support for the ACCES PCI-IDIO-16")
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
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@ -265,6 +265,7 @@ static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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struct device *const dev = &pdev->dev;
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struct idio_16_gpio *idio16gpio;
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int err;
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const size_t pci_bar_index = 2;
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const char *const name = pci_name(pdev);
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idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
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@ -277,13 +278,13 @@ static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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return err;
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}
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err = pcim_iomap_regions(pdev, 0x1, name);
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err = pcim_iomap_regions(pdev, BIT(pci_bar_index), name);
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if (err) {
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dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
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return err;
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}
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idio16gpio->reg = pcim_iomap_table(pdev)[0];
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idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
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/* Deactivate input filters */
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iowrite8(0, &idio16gpio->reg->filter_ctl);
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