UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

x86/oprofile: replace CTRL_SET_*ACTIVE macros 

The patch replaces all CTRL_SET_*ACTIVE macros. 64 bit MSR functions
and 64 bit counter values are used now. The code uses bit masks from
<asm/intel_arch_perfmon.h>.

Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter 2009-05-25 18:11:52 +02:00
parent 42399adb23
commit dea3766ca0
3 changed files with 16 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/x86/oprofile/op_model_amd.c
View File

@ -262,13 +262,13 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
static void op_amd_start(struct op_msrs const * const msrs)
{
unsigned int low, high;
u64 val;
int i;
for (i = 0 ; i < NUM_COUNTERS ; ++i) {
if (reset_value[i]) {
rdmsr(msrs->controls[i].addr, low, high);
CTRL_SET_ACTIVE(low);
wrmsr(msrs->controls[i].addr, low, high);
rdmsrl(msrs->controls[i].addr, val);
val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
wrmsrl(msrs->controls[i].addr, val);
}
}
@ -277,7 +277,7 @@ static void op_amd_start(struct op_msrs const * const msrs)
static void op_amd_stop(struct op_msrs const * const msrs)
{
unsigned int low, high;
u64 val;
int i;
/*
@ -287,9 +287,9 @@ static void op_amd_stop(struct op_msrs const * const msrs)
for (i = 0 ; i < NUM_COUNTERS ; ++i) {
if (!reset_value[i])
continue;
rdmsr(msrs->controls[i].addr, low, high);
CTRL_SET_INACTIVE(low);
wrmsr(msrs->controls[i].addr, low, high);
rdmsrl(msrs->controls[i].addr, val);
val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
wrmsrl(msrs->controls[i].addr, val);
}
op_amd_stop_ibs();

16
arch/x86/oprofile/op_model_ppro.c
View File

@ -145,16 +145,16 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
static void ppro_start(struct op_msrs const * const msrs)
{
unsigned int low, high;
u64 val;
int i;
if (!reset_value)
return;
for (i = 0; i < num_counters; ++i) {
if (reset_value[i]) {
rdmsr(msrs->controls[i].addr, low, high);
CTRL_SET_ACTIVE(low);
wrmsr(msrs->controls[i].addr, low, high);
rdmsrl(msrs->controls[i].addr, val);
val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
wrmsrl(msrs->controls[i].addr, val);
}
}
}
@ -162,7 +162,7 @@ static void ppro_start(struct op_msrs const * const msrs)
static void ppro_stop(struct op_msrs const * const msrs)
{
unsigned int low, high;
u64 val;
int i;
if (!reset_value)
@ -170,9 +170,9 @@ static void ppro_stop(struct op_msrs const * const msrs)
for (i = 0; i < num_counters; ++i) {
if (!reset_value[i])
continue;
rdmsr(msrs->controls[i].addr, low, high);
CTRL_SET_INACTIVE(low);
wrmsr(msrs->controls[i].addr, low, high);
rdmsrl(msrs->controls[i].addr, val);
val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
wrmsrl(msrs->controls[i].addr, val);
}
}

2
arch/x86/oprofile/op_x86_model.h
View File

@ -17,8 +17,6 @@
#define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0)
#define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0)
#define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE)
#define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE)
struct op_saved_msr {
unsigned int high;