gma500: polish for completion of this phase
Give the driver its own proper DRM name, clean up copyright headers and so forth Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
5b7aa16007
commit
de64ac92c4
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@ -86,7 +86,7 @@ static const struct mrst_limit_t *mrst_limit(struct drm_crtc *crtc)
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{
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const struct mrst_limit_t *limit = NULL;
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struct drm_device *dev = crtc->dev;
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DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
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struct drm_psb_private *dev_priv = dev->dev_private;
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if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
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|| psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
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@ -296,7 +296,7 @@ static int mrst_crtc_mode_set(struct drm_crtc *crtc,
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{
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struct drm_device *dev = crtc->dev;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
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struct drm_psb_private *dev_priv = dev->dev_private;
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int pipe = psb_intel_crtc->pipe;
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int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
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int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
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@ -46,7 +46,7 @@ static void mrst_lvds_set_power(struct drm_device *dev,
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struct psb_intel_output *output, bool on)
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{
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u32 pp_status;
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DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
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struct drm_psb_private *dev_priv = dev->dev_private;
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PSB_DEBUG_ENTRY("\n");
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if (!gma_power_begin(dev, true))
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@ -1,5 +1,5 @@
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -396,8 +396,3 @@ int psbfb_sync(struct fb_info *info)
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out:
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return (busy) ? -EBUSY : 0;
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}
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/*
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info->fix.accel = FB_ACCEL_I830;
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info->flags = FBINFO_DEFAULT;
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*/
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@ -1,7 +1,7 @@
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/*
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* psb backlight interface
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* GMA500 Backlight Interface
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*
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* Copyright (c) 2009, Intel Corporation.
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* Copyright (c) 2009-2011, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -1,5 +1,5 @@
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
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* All Rights Reserved.
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@ -22,84 +22,8 @@
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#ifndef _PSB_DRM_H_
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#define _PSB_DRM_H_
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#if defined(__linux__) && !defined(__KERNEL__)
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#include<stdint.h>
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#include <linux/types.h>
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#include "drm_mode.h"
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#endif
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#define DRM_PSB_SAREA_MAJOR 0
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#define DRM_PSB_SAREA_MINOR 2
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#define PSB_FIXED_SHIFT 16
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#define PSB_NUM_PIPE 3
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/*
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* Public memory types.
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*/
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typedef s32 psb_fixed;
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typedef u32 psb_ufixed;
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static inline s32 psb_int_to_fixed(int a)
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{
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return a * (1 << PSB_FIXED_SHIFT);
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}
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static inline u32 psb_unsigned_to_ufixed(unsigned int a)
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{
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return a << PSB_FIXED_SHIFT;
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}
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/*Status of the command sent to the gfx device.*/
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typedef enum {
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DRM_CMD_SUCCESS,
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DRM_CMD_FAILED,
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DRM_CMD_HANG
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} drm_cmd_status_t;
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struct drm_psb_scanout {
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u32 buffer_id; /* DRM buffer object ID */
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u32 rotation; /* Rotation as in RR_rotation definitions */
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u32 stride; /* Buffer stride in bytes */
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u32 depth; /* Buffer depth in bits (NOT) bpp */
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u32 width; /* Buffer width in pixels */
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u32 height; /* Buffer height in lines */
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s32 transform[3][3]; /* Buffer composite transform */
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/* (scaling, rot, reflect) */
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};
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#define DRM_PSB_SAREA_OWNERS 16
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#define DRM_PSB_SAREA_OWNER_2D 0
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#define DRM_PSB_SAREA_OWNER_3D 1
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#define DRM_PSB_SAREA_SCANOUTS 3
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struct drm_psb_sarea {
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/* Track changes of this data structure */
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u32 major;
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u32 minor;
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/* Last context to touch part of hw */
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u32 ctx_owners[DRM_PSB_SAREA_OWNERS];
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/* Definition of front- and rotated buffers */
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u32 num_scanouts;
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struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
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int planeA_x;
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int planeA_y;
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int planeA_w;
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int planeA_h;
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int planeB_x;
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int planeB_y;
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int planeB_w;
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int planeB_h;
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/* Number of active scanouts */
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u32 num_active_scanouts;
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};
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#define PSB_GPU_ACCESS_READ (1ULL << 32)
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#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
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#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
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@ -223,20 +147,14 @@ struct drm_psb_register_rw_arg {
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#define DRM_PSB_KMS_OFF 0x00
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#define DRM_PSB_KMS_ON 0x01
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#define DRM_PSB_VT_LEAVE 0x02
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#define DRM_PSB_VT_ENTER 0x03
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#define DRM_PSB_EXTENSION 0x06
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#define DRM_PSB_SIZES 0x07
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#define DRM_PSB_FUSE_REG 0x08
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#define DRM_PSB_VBT 0x09
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#define DRM_PSB_DC_STATE 0x0A
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#define DRM_PSB_ADB 0x0B
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#define DRM_PSB_MODE_OPERATION 0x0C
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#define DRM_PSB_STOLEN_MEMORY 0x0D
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#define DRM_PSB_REGISTER_RW 0x0E
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#define DRM_PSB_GTT_MAP 0x0F
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#define DRM_PSB_GTT_UNMAP 0x10
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#define DRM_PSB_GETPAGEADDRS 0x11
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/**
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* NOTE: Add new commands here, but increment
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* the values below and increment their
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@ -249,10 +167,6 @@ struct drm_psb_register_rw_arg {
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#define DRM_PVR_RESERVED4 0x15
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#define DRM_PVR_RESERVED5 0x16
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#define DRM_PSB_HIST_ENABLE 0x17
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#define DRM_PSB_HIST_STATUS 0x18
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#define DRM_PSB_UPDATE_GUARD 0x19
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#define DRM_PSB_INIT_COMM 0x1A
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#define DRM_PSB_DPST 0x1B
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#define DRM_PSB_GAMMA 0x1C
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#define DRM_PSB_DPST_BL 0x1D
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@ -1,5 +1,5 @@
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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* Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
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* All Rights Reserved.
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@ -1462,6 +1462,6 @@ static void __exit psb_exit(void)
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late_initcall(psb_init);
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module_exit(psb_exit);
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MODULE_AUTHOR(DRIVER_AUTHOR);
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MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL");
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@ -1,5 +1,5 @@
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/**************************************************************************
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* Copyright (c) 2007-2008, Intel Corporation.
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -32,40 +32,32 @@
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#include "psb_powermgmt.h"
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#include "mrst.h"
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/*Append new drm mode definition here, align with libdrm definition*/
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/* Append new drm mode definition here, align with libdrm definition */
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#define DRM_MODE_SCALE_NO_SCALE 2
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enum {
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CHIP_PSB_8108 = 0,
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CHIP_PSB_8109 = 1,
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CHIP_MRST_4100 = 2,
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CHIP_PSB_8108 = 0, /* Poulsbo */
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CHIP_PSB_8109 = 1, /* Poulsbo */
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CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
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};
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#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
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/*
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*Hardware bugfixes
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* Driver definitions
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*/
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#define DRIVER_NAME "pvrsrvkm"
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#define DRIVER_DESC "drm driver for the Intel GMA500"
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#define DRIVER_AUTHOR "Intel Corporation"
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#define DRIVER_NAME "gma500"
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#define DRIVER_DESC "DRM driver for the Intel GMA500"
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#define PSB_DRM_DRIVER_DATE "2009-03-10"
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#define PSB_DRM_DRIVER_MAJOR 8
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#define PSB_DRM_DRIVER_MINOR 1
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#define PSB_DRM_DRIVER_DATE "2011-06-06"
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#define PSB_DRM_DRIVER_MAJOR 1
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#define PSB_DRM_DRIVER_MINOR 0
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#define PSB_DRM_DRIVER_PATCHLEVEL 0
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/*
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*TTM driver private offsets.
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* Hardware offsets
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*/
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#define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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#define PSB_OBJECT_HASH_ORDER 13
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#define PSB_FILE_OBJECT_HASH_ORDER 12
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#define PSB_BO_HASH_ORDER 12
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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@ -73,42 +65,52 @@ enum {
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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/*
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* PCI resource identifiers
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*/
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#define PSB_MMIO_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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/*
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* PCI configuration
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*/
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#define PSB_GMCH_CTRL 0x52
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#define PSB_BSM 0x5C
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#define _PSB_GMCH_ENABLED 0x4
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#define PSB_PGETBL_CTL 0x2020
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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/* To get rid of */
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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#define PSB_NUM_VALIDATE_BUFFERS 2048
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/*
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*Flags for external memory type field.
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* SGX side MMU definitions (these can probably go)
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*/
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/*
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* Flags for external memory type field.
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*/
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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/*
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*PTE's and PDE's
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* PTE's and PDE's
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*/
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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/*
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* Cache control
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*/
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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/*
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*VDC registers and bits
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* VDC registers and bits
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*/
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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@ -278,7 +280,7 @@ struct drm_psb_private {
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int display_count;
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/*
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*Modesetting
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* Modesetting
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*/
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struct psb_intel_mode_device mode_dev;
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@ -287,12 +289,8 @@ struct drm_psb_private {
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uint32_t num_pipe;
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/*
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*Memory managers
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* OSPM info (Power management base) (can go ?)
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*/
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/*
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*OSPM info
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*/
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uint32_t ospm_base;
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/*
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@ -304,11 +302,11 @@ struct drm_psb_private {
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u32 fuse_reg_value;
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u32 video_device_fuse;
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/* pci revision id for B0:D2:F0 */
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/* PCI revision ID for B0:D2:F0 */
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uint8_t platform_rev_id;
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/*
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*LVDS info
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* LVDS info
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*/
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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@ -316,10 +314,10 @@ struct drm_psb_private {
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struct drm_display_mode *lfp_lvds_vbt_mode;
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struct drm_display_mode *sdvo_lvds_vbt_mode;
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struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
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struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
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struct psb_intel_i2c_chan *lvds_i2c_bus;
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/* Feature bits from the VBIOS*/
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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@ -332,7 +330,7 @@ struct drm_psb_private {
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unsigned int core_freq;
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uint32_t iLVDS_enable;
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/*runtime PM state*/
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/* Runtime PM state */
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int rpm_enabled;
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/* Moorestown specific */
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@ -350,7 +348,7 @@ struct drm_psb_private {
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uint32_t dspcntr2;
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/*
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*Register state
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* Register state
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*/
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uint32_t saveDSPACNTR;
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uint32_t saveDSPBCNTR;
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@ -468,7 +466,7 @@ struct drm_psb_private {
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u32 lid_last_state;
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/*
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*Watchdog
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* Watchdog
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*/
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uint32_t apm_reg;
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@ -497,7 +495,7 @@ static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
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}
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/*
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*MMU stuff.
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* MMU stuff.
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*/
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extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
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@ -525,7 +523,7 @@ extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
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unsigned long *pfn);
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/*
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*Enable / disable MMU for different requestors.
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* Enable / disable MMU for different requestors.
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*/
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@ -598,7 +596,7 @@ extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
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unsigned size);
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/*
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*psb_reset.c
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* psb_reset.c
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*/
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extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
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@ -710,7 +708,6 @@ extern int drm_idle_check_interval;
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/*
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*Utilities
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*/
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#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
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static inline u32 MRST_MSG_READ32(uint port, uint offset)
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{
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@ -1,5 +1,5 @@
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/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -56,7 +56,6 @@ void *psbfb_vdc_reg(struct drm_device *dev)
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dev_priv = (struct drm_psb_private *) dev->dev_private;
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return dev_priv->vdc_reg;
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}
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/*EXPORT_SYMBOL(psbfb_vdc_reg); */
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static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green,
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unsigned blue, unsigned transp,
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|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2008, Intel Corporation
|
||||
* Copyright (c) 2008-2011, Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -41,7 +41,6 @@ struct psb_fbdev {
|
|||
struct psb_framebuffer pfb;
|
||||
};
|
||||
|
||||
|
||||
#define to_psb_fb(x) container_of(x, struct psb_framebuffer, base)
|
||||
|
||||
extern int psb_intel_connector_clones(struct drm_device *dev, int type_mask);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
/* This wants cleaning up with respect to the psb_dev and un-needed stuff */
|
||||
struct psb_gtt {
|
||||
struct drm_device *dev;
|
||||
uint32_t gatt_start;
|
||||
|
|
@ -41,9 +42,9 @@ extern void psb_gtt_takedown(struct drm_device *dev);
|
|||
|
||||
/* Each gtt_range describes an allocation in the GTT area */
|
||||
struct gtt_range {
|
||||
struct resource resource;
|
||||
u32 offset;
|
||||
struct kref kref;
|
||||
struct resource resource; /* Resource for our allocation */
|
||||
u32 offset; /* GTT offset of our object */
|
||||
struct kref kref; /* Can probably go FIXME - GEM kref will do */
|
||||
struct drm_gem_object gem; /* GEM high level stuff */
|
||||
int in_gart; /* Currently in the GART (ref ct) */
|
||||
bool stolen; /* Backed from stolen RAM */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -25,11 +25,6 @@
|
|||
#include <drm/drm_crtc_helper.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
/*
|
||||
* MOORESTOWN defines
|
||||
*/
|
||||
#define DELAY_TIME1 2000 /* 1000 = 1ms */
|
||||
|
||||
/*
|
||||
* Display related stuff
|
||||
*/
|
||||
|
|
@ -61,16 +56,10 @@
|
|||
#define INTEL_DVO_CHIP_TMDS 2
|
||||
#define INTEL_DVO_CHIP_TVOUT 4
|
||||
|
||||
enum mipi_panel_type {
|
||||
NSC_800X480 = 1,
|
||||
LGE_480X1024 = 2,
|
||||
TPO_864X480 = 3
|
||||
};
|
||||
|
||||
/**
|
||||
/*
|
||||
* Hold information useally put on the device driver privates here,
|
||||
* since it needs to be shared across multiple of devices drivers privates.
|
||||
*/
|
||||
*/
|
||||
struct psb_intel_mode_device {
|
||||
|
||||
/*
|
||||
|
|
@ -79,7 +68,7 @@ struct psb_intel_mode_device {
|
|||
size_t(*bo_offset) (struct drm_device *dev, void *bo);
|
||||
|
||||
/*
|
||||
* Cursor
|
||||
* Cursor (Can go ?)
|
||||
*/
|
||||
int cursor_needs_physical;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/**************************************************************************
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -34,10 +34,6 @@ int psb_irq_postinstall(struct drm_device *dev);
|
|||
void psb_irq_uninstall(struct drm_device *dev);
|
||||
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
||||
|
||||
void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
|
||||
int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
|
||||
void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev);
|
||||
int psb_irq_disable_dpst(struct drm_device *dev);
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev);
|
||||
|
|
@ -46,4 +42,4 @@ int psb_enable_vblank(struct drm_device *dev, int pipe);
|
|||
void psb_disable_vblank(struct drm_device *dev, int pipe);
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe);
|
||||
|
||||
#endif //_SYSIRQ_H_
|
||||
#endif /* _SYSIRQ_H_ */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/**************************************************************************
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/**************************************************************************
|
||||
* Copyright (c) 2009, Intel Corporation.
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
|
|
|||
|
|
@ -573,7 +573,7 @@
|
|||
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR)// 0x000fc00c
|
||||
// Display SSS register bits are different in A0 vs. B0
|
||||
/* Display SSS register bits are different in A0 vs. B0 */
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
|
||||
|
|
|
|||
Loading…
Reference in New Issue