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ASoC: wm8900: Fix the mask defines 

Now we have done bitwise NOT against the mask bits for the defines of
WM8900_REG_CLOCKING1_BCLK_MASK,
WM8900_REG_CLOCKING1_OPCLK_MASK and WM8900_LRC_MASK.

But we don't have the bitwise NOT against the mask bits for the defines of
WM8900_REG_CLOCKING2_DAC_CLKDIV,
WM8900_REG_CLOCKING2_ADC_CLKDIV and WM8900_REG_DACCTRL_AIF_LRCLKRATE.

It is error prone to mix the inconsistent meaning for different mask defines.
So lets make the defines for each mask to be corresponding to the bits
defines in datasheet. Don't add extra "bitwise NOT" to the defines.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Axel Lin 2011-10-16 23:29:12 +08:00 committed by Mark Brown
parent 151b75995a
commit de5035b1dd
1 changed files with 7 additions and 7 deletions
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14
sound/soc/codecs/wm8900.c
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@ -110,8 +110,8 @@
#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
@ -135,7 +135,7 @@
#define WM8900_REG_HPCTL1_HP_SHORT 0x08
#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
#define WM8900_LRC_MASK 0xfc00
#define WM8900_LRC_MASK 0x03ff
struct wm8900_priv {
enum snd_soc_control_type control_type;
@ -824,22 +824,22 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
case WM8900_BCLK_DIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
snd_soc_write(codec, WM8900_REG_CLOCKING1,
div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
div | (reg & ~WM8900_REG_CLOCKING1_BCLK_MASK));
break;
case WM8900_OPCLK_DIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
snd_soc_write(codec, WM8900_REG_CLOCKING1,
div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
div | (reg & ~WM8900_REG_CLOCKING1_OPCLK_MASK));
break;
case WM8900_DAC_LRCLK:
reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
snd_soc_write(codec, WM8900_REG_AUDIO4,
div | (reg & WM8900_LRC_MASK));
div | (reg & ~WM8900_LRC_MASK));
break;
case WM8900_ADC_LRCLK:
reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
snd_soc_write(codec, WM8900_REG_AUDIO3,
div | (reg & WM8900_LRC_MASK));
div | (reg & ~WM8900_LRC_MASK));
break;
case WM8900_DAC_CLKDIV:
reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);