Merge branch irq/qcom-mpm into irq/irqchip-next
* irq/qcom-mpm: : . : Add support for Qualcomm's MPM wakeup controller, courtesy : of Shawn Guo. : . irqchip: Add Qualcomm MPM controller driver dt-bindings: interrupt-controller: Add Qualcomm MPM support Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
commit
de26a74243
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@ -0,0 +1,96 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcom MPM Interrupt Controller
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description:
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Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
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MSM Power Manager (MPM) that is in always-on domain. In addition to managing
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resources during sleep, the hardware also has an interrupt controller that
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monitors the interrupts when the system is asleep, wakes up the APSS when
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one of these interrupts occur and replays it to GIC interrupt controller
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after GIC becomes operational.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- const: qcom,mpm
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reg:
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maxItems: 1
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description:
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Specifies the base address and size of vMPM registers in RPM MSG RAM.
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interrupts:
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maxItems: 1
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description:
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Specify the IRQ used by RPM to wakeup APSS.
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mboxes:
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maxItems: 1
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description:
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Specify the mailbox used to notify RPM for writing vMPM registers.
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the MPM pin number for the interrupt, and the second
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is the trigger type.
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qcom,mpm-pin-count:
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description:
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Specify the total MPM pin count that a SoC supports.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mpm-pin-map:
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description:
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A set of MPM pin numbers and the corresponding GIC SPIs.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: MPM pin number
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- description: GIC SPI number for the MPM pin
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required:
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- compatible
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- reg
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- interrupts
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- mboxes
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- interrupt-controller
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- '#interrupt-cells'
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- qcom,mpm-pin-count
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- qcom,mpm-pin-map
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mpm: interrupt-controller@45f01b8 {
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compatible = "qcom,mpm";
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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reg = <0x45f01b8 0x1000>;
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mboxes = <&apcs_glb 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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qcom,mpm-pin-count = <96>;
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qcom,mpm-pin-map = <2 275>,
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<5 296>,
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<12 422>,
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<24 79>,
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<86 183>,
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<90 260>,
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<91 260>;
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};
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@ -430,6 +430,14 @@ config QCOM_PDC
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Power Domain Controller driver to manage and configure wakeup
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IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
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config QCOM_MPM
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tristate "QCOM MPM"
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depends on ARCH_QCOM
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select IRQ_DOMAIN_HIERARCHY
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help
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MSM Power Manager driver to manage and configure wakeup
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IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
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config CSKY_MPINTC
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bool
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depends on CSKY
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@ -94,6 +94,7 @@ obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
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obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
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obj-$(CONFIG_NDS32) += irq-ativic32.o
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obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
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obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o
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obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
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obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
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obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
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@ -0,0 +1,461 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, Linaro Limited
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* Copyright (c) 2010-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/mailbox_client.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/soc/qcom/irq.h>
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#include <linux/spinlock.h>
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/*
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* This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller,
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* which is commonly found on Qualcomm SoCs built on the RPM architecture.
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* Sitting in always-on domain, MPM monitors the wakeup interrupts when SoC is
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* asleep, and wakes up the AP when one of those interrupts occurs. This driver
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* doesn't directly access physical MPM registers though. Instead, the access
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* is bridged via a piece of internal memory (SRAM) that is accessible to both
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* AP and RPM. This piece of memory is called 'vMPM' in the driver.
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*
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* When SoC is awake, the vMPM is owned by AP and the register setup by this
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* driver all happens on vMPM. When AP is about to get power collapsed, the
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* driver sends a mailbox notification to RPM, which will take over the vMPM
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* ownership and dump vMPM into physical MPM registers. On wakeup, AP is woken
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* up by a MPM pin/interrupt, and RPM will copy STATUS registers into vMPM.
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* Then AP start owning vMPM again.
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*
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* vMPM register map:
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*
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* 31 0
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* +--------------------------------+
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* | TIMER0 | 0x00
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* +--------------------------------+
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* | TIMER1 | 0x04
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* +--------------------------------+
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* | ENABLE0 | 0x08
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* +--------------------------------+
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* | ... | ...
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* +--------------------------------+
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* | ENABLEn |
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* +--------------------------------+
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* | FALLING_EDGE0 |
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* +--------------------------------+
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* | ... |
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* +--------------------------------+
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* | STATUSn |
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* +--------------------------------+
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*
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* n = DIV_ROUND_UP(pin_cnt, 32)
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*
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*/
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#define MPM_REG_ENABLE 0
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#define MPM_REG_FALLING_EDGE 1
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#define MPM_REG_RISING_EDGE 2
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#define MPM_REG_POLARITY 3
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#define MPM_REG_STATUS 4
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/* MPM pin map to GIC hwirq */
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struct mpm_gic_map {
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int pin;
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irq_hw_number_t hwirq;
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};
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struct qcom_mpm_priv {
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void __iomem *base;
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raw_spinlock_t lock;
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struct mbox_client mbox_client;
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struct mbox_chan *mbox_chan;
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struct mpm_gic_map *maps;
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unsigned int map_cnt;
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unsigned int reg_stride;
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struct irq_domain *domain;
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struct generic_pm_domain genpd;
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};
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static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, unsigned int reg,
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unsigned int index)
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{
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unsigned int offset = (reg * priv->reg_stride + index + 2) * 4;
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return readl_relaxed(priv->base + offset);
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}
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static void qcom_mpm_write(struct qcom_mpm_priv *priv, unsigned int reg,
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unsigned int index, u32 val)
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{
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unsigned int offset = (reg * priv->reg_stride + index + 2) * 4;
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writel_relaxed(val, priv->base + offset);
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/* Ensure the write is completed */
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wmb();
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}
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static void qcom_mpm_enable_irq(struct irq_data *d, bool en)
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{
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struct qcom_mpm_priv *priv = d->chip_data;
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int pin = d->hwirq;
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unsigned int index = pin / 32;
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unsigned int shift = pin % 32;
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unsigned long flags, val;
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raw_spin_lock_irqsave(&priv->lock, flags);
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val = qcom_mpm_read(priv, MPM_REG_ENABLE, index);
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__assign_bit(shift, &val, en);
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qcom_mpm_write(priv, MPM_REG_ENABLE, index, val);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void qcom_mpm_mask(struct irq_data *d)
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{
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qcom_mpm_enable_irq(d, false);
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if (d->parent_data)
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irq_chip_mask_parent(d);
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}
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static void qcom_mpm_unmask(struct irq_data *d)
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{
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qcom_mpm_enable_irq(d, true);
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if (d->parent_data)
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irq_chip_unmask_parent(d);
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}
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static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, unsigned int reg,
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unsigned int index, unsigned int shift)
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{
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unsigned long flags, val;
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raw_spin_lock_irqsave(&priv->lock, flags);
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val = qcom_mpm_read(priv, reg, index);
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__assign_bit(shift, &val, set);
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qcom_mpm_write(priv, reg, index, val);
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raw_spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int qcom_mpm_set_type(struct irq_data *d, unsigned int type)
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{
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struct qcom_mpm_priv *priv = d->chip_data;
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int pin = d->hwirq;
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unsigned int index = pin / 32;
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unsigned int shift = pin % 32;
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if (type & IRQ_TYPE_EDGE_RISING)
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mpm_set_type(priv, true, MPM_REG_RISING_EDGE, index, shift);
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else
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mpm_set_type(priv, false, MPM_REG_RISING_EDGE, index, shift);
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if (type & IRQ_TYPE_EDGE_FALLING)
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mpm_set_type(priv, true, MPM_REG_FALLING_EDGE, index, shift);
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else
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mpm_set_type(priv, false, MPM_REG_FALLING_EDGE, index, shift);
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if (type & IRQ_TYPE_LEVEL_HIGH)
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mpm_set_type(priv, true, MPM_REG_POLARITY, index, shift);
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else
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mpm_set_type(priv, false, MPM_REG_POLARITY, index, shift);
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if (!d->parent_data)
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return 0;
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if (type & IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_RISING;
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if (type & IRQ_TYPE_LEVEL_MASK)
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type = IRQ_TYPE_LEVEL_HIGH;
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return irq_chip_set_type_parent(d, type);
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}
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static struct irq_chip qcom_mpm_chip = {
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.name = "mpm",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = qcom_mpm_mask,
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.irq_unmask = qcom_mpm_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = qcom_mpm_set_type,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SKIP_SET_WAKE,
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};
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static struct mpm_gic_map *get_mpm_gic_map(struct qcom_mpm_priv *priv, int pin)
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{
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struct mpm_gic_map *maps = priv->maps;
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int i;
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for (i = 0; i < priv->map_cnt; i++) {
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if (maps[i].pin == pin)
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return &maps[i];
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}
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return NULL;
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}
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static int qcom_mpm_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct qcom_mpm_priv *priv = domain->host_data;
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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struct mpm_gic_map *map;
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irq_hw_number_t pin;
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unsigned int type;
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int ret;
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ret = irq_domain_translate_twocell(domain, fwspec, &pin, &type);
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if (ret)
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return ret;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, pin,
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&qcom_mpm_chip, priv);
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if (ret)
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return ret;
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map = get_mpm_gic_map(priv, pin);
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if (map == NULL)
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return irq_domain_disconnect_hierarchy(domain->parent, virq);
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if (type & IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_RISING;
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if (type & IRQ_TYPE_LEVEL_MASK)
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type = IRQ_TYPE_LEVEL_HIGH;
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 3;
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parent_fwspec.param[0] = 0;
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parent_fwspec.param[1] = map->hwirq;
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parent_fwspec.param[2] = type;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
|
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&parent_fwspec);
|
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}
|
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|
||||
static const struct irq_domain_ops qcom_mpm_ops = {
|
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.alloc = qcom_mpm_alloc,
|
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.free = irq_domain_free_irqs_common,
|
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.translate = irq_domain_translate_twocell,
|
||||
};
|
||||
|
||||
/* Triggered by RPM when system resumes from deep sleep */
|
||||
static irqreturn_t qcom_mpm_handler(int irq, void *dev_id)
|
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{
|
||||
struct qcom_mpm_priv *priv = dev_id;
|
||||
unsigned long enable, pending;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
unsigned long flags;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < priv->reg_stride; i++) {
|
||||
raw_spin_lock_irqsave(&priv->lock, flags);
|
||||
enable = qcom_mpm_read(priv, MPM_REG_ENABLE, i);
|
||||
pending = qcom_mpm_read(priv, MPM_REG_STATUS, i);
|
||||
pending &= enable;
|
||||
raw_spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
for_each_set_bit(j, &pending, 32) {
|
||||
unsigned int pin = 32 * i + j;
|
||||
struct irq_desc *desc = irq_resolve_mapping(priv->domain, pin);
|
||||
struct irq_data *d = &desc->irq_data;
|
||||
|
||||
if (!irqd_is_level_type(d))
|
||||
irq_set_irqchip_state(d->irq,
|
||||
IRQCHIP_STATE_PENDING, true);
|
||||
ret = IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mpm_pd_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct qcom_mpm_priv *priv = container_of(genpd, struct qcom_mpm_priv,
|
||||
genpd);
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < priv->reg_stride; i++)
|
||||
qcom_mpm_write(priv, MPM_REG_STATUS, i, 0);
|
||||
|
||||
/* Notify RPM to write vMPM into HW */
|
||||
ret = mbox_send_message(priv->mbox_chan, NULL);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool gic_hwirq_is_mapped(struct mpm_gic_map *maps, int cnt, u32 hwirq)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < cnt; i++)
|
||||
if (maps[i].hwirq == hwirq)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
|
||||
{
|
||||
struct platform_device *pdev = of_find_device_by_node(np);
|
||||
struct device *dev = &pdev->dev;
|
||||
struct irq_domain *parent_domain;
|
||||
struct generic_pm_domain *genpd;
|
||||
struct qcom_mpm_priv *priv;
|
||||
unsigned int pin_cnt;
|
||||
int i, irq;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_property_read_u32(np, "qcom,mpm-pin-count", &pin_cnt);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to read qcom,mpm-pin-count: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->reg_stride = DIV_ROUND_UP(pin_cnt, 32);
|
||||
|
||||
ret = of_property_count_u32_elems(np, "qcom,mpm-pin-map");
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to read qcom,mpm-pin-map: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret % 2) {
|
||||
dev_err(dev, "invalid qcom,mpm-pin-map\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->map_cnt = ret / 2;
|
||||
priv->maps = devm_kcalloc(dev, priv->map_cnt, sizeof(*priv->maps),
|
||||
GFP_KERNEL);
|
||||
if (!priv->maps)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < priv->map_cnt; i++) {
|
||||
u32 pin, hwirq;
|
||||
|
||||
of_property_read_u32_index(np, "qcom,mpm-pin-map", i * 2, &pin);
|
||||
of_property_read_u32_index(np, "qcom,mpm-pin-map", i * 2 + 1, &hwirq);
|
||||
|
||||
if (gic_hwirq_is_mapped(priv->maps, i, hwirq)) {
|
||||
dev_warn(dev, "failed to map pin %d as GIC hwirq %d is already mapped\n",
|
||||
pin, hwirq);
|
||||
continue;
|
||||
}
|
||||
|
||||
priv->maps[i].pin = pin;
|
||||
priv->maps[i].hwirq = hwirq;
|
||||
}
|
||||
|
||||
raw_spin_lock_init(&priv->lock);
|
||||
|
||||
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (!priv->base)
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
for (i = 0; i < priv->reg_stride; i++) {
|
||||
qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);
|
||||
qcom_mpm_write(priv, MPM_REG_FALLING_EDGE, i, 0);
|
||||
qcom_mpm_write(priv, MPM_REG_RISING_EDGE, i, 0);
|
||||
qcom_mpm_write(priv, MPM_REG_POLARITY, i, 0);
|
||||
qcom_mpm_write(priv, MPM_REG_STATUS, i, 0);
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
genpd = &priv->genpd;
|
||||
genpd->flags = GENPD_FLAG_IRQ_SAFE;
|
||||
genpd->power_off = mpm_pd_power_off;
|
||||
|
||||
genpd->name = devm_kasprintf(dev, GFP_KERNEL, "%s", dev_name(dev));
|
||||
if (!genpd->name)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = pm_genpd_init(genpd, NULL, false);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to init genpd: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_genpd_add_provider_simple(np, genpd);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to add genpd provider: %d\n", ret);
|
||||
goto remove_genpd;
|
||||
}
|
||||
|
||||
priv->mbox_client.dev = dev;
|
||||
priv->mbox_chan = mbox_request_channel(&priv->mbox_client, 0);
|
||||
if (IS_ERR(priv->mbox_chan)) {
|
||||
ret = PTR_ERR(priv->mbox_chan);
|
||||
dev_err(dev, "failed to acquire IPC channel: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
parent_domain = irq_find_host(parent);
|
||||
if (!parent_domain) {
|
||||
dev_err(dev, "failed to find MPM parent domain\n");
|
||||
ret = -ENXIO;
|
||||
goto free_mbox;
|
||||
}
|
||||
|
||||
priv->domain = irq_domain_create_hierarchy(parent_domain,
|
||||
IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP, pin_cnt,
|
||||
of_node_to_fwnode(np), &qcom_mpm_ops, priv);
|
||||
if (!priv->domain) {
|
||||
dev_err(dev, "failed to create MPM domain\n");
|
||||
ret = -ENOMEM;
|
||||
goto free_mbox;
|
||||
}
|
||||
|
||||
irq_domain_update_bus_token(priv->domain, DOMAIN_BUS_WAKEUP);
|
||||
|
||||
ret = devm_request_irq(dev, irq, qcom_mpm_handler, IRQF_NO_SUSPEND,
|
||||
"qcom_mpm", priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq: %d\n", ret);
|
||||
goto remove_domain;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
remove_domain:
|
||||
irq_domain_remove(priv->domain);
|
||||
free_mbox:
|
||||
mbox_free_channel(priv->mbox_chan);
|
||||
remove_genpd:
|
||||
pm_genpd_remove(genpd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_mpm)
|
||||
IRQCHIP_MATCH("qcom,mpm", qcom_mpm_init)
|
||||
IRQCHIP_PLATFORM_DRIVER_END(qcom_mpm)
|
||||
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. MSM Power Manager");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue