RDMA/mlx5: Improve PI handover performance
In some loads, there is performance degradation when using KLM mkey instead of MTT mkey. This is because KLM descriptor access is via indirection that might require more HW resources and cycles. Using KLM descriptor is not necessary when there are no gaps at the data/metadata sg lists. As an optimization, use MTT mkey whenever it is possible. For that matter, allocate internal MTT mkey and choose the effective pi_mr for in transaction according to the required mapping scheme. The setup of the tested benchmark (using iSER ULP): - 2 servers with 24 cores (1 initiator and 1 target) - ConnectX-4/ConnectX-5 adapters - 24 target sessions with 1 LUN each - ramdisk backstore - PI active Performance results running fio (24 jobs, 128 iodepth) using write_generate=1 and read_verify=1 (w/w.o/baseline): bs IOPS(read) IOPS(write) ---- ---------- ---------- 512 1262.4K/1243.3K/1147.1K 1732.1K/1725.1K/1423.8K 4k 570902/571233/457874 773982/743293/642080 32k 72086/72388/71933 96164/71789/93249 Using write_generate=0 and read_verify=0 (w/w.o patch): bs IOPS(read) IOPS(write) ---- ---------- ---------- 512 1600.1K/1572.1K/1393.3K 1830.3K/1823.5K/1557.2K 4k 937272/921992/762934 815304/753772/646071 32k 77369/75052/72058 97435/73180/94612 Signed-off-by: Israel Rukshin <israelr@mellanox.com> Reviewed-by: Max Gurtovoy <maxg@mellanox.com> Suggested-by: Max Gurtovoy <maxg@mellanox.com> Suggested-by: Idan Burstein <idanb@mellanox.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Israel Rukshin
Jason Gunthorpe
parent
5c171cbe3a
commit
de0ae958de
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@ -605,7 +605,12 @@ struct mlx5_ib_mr {
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int access_flags; /* Needed for rereg MR */
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struct mlx5_ib_mr *parent;
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struct mlx5_ib_mr *pi_mr; /* Needed for IB_MR_TYPE_INTEGRITY */
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/* Needed for IB_MR_TYPE_INTEGRITY */
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struct mlx5_ib_mr *pi_mr;
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struct mlx5_ib_mr *klm_mr;
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struct mlx5_ib_mr *mtt_mr;
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u64 pi_iova;
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atomic_t num_leaf_free;
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wait_queue_head_t q_leaf_free;
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struct mlx5_async_work cb_work;
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@ -1641,8 +1641,10 @@ int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
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{
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struct mlx5_ib_mr *mmr = to_mmr(ibmr);
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if (ibmr->type == IB_MR_TYPE_INTEGRITY)
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dereg_mr(to_mdev(mmr->pi_mr->ibmr.device), mmr->pi_mr);
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if (ibmr->type == IB_MR_TYPE_INTEGRITY) {
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dereg_mr(to_mdev(mmr->mtt_mr->ibmr.device), mmr->mtt_mr);
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dereg_mr(to_mdev(mmr->klm_mr->ibmr.device), mmr->klm_mr);
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}
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dereg_mr(to_mdev(ibmr->device), mmr);
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@ -1650,7 +1652,8 @@ int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
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}
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static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd,
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u32 max_num_sg, u32 max_num_meta_sg)
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u32 max_num_sg, u32 max_num_meta_sg,
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int desc_size, int access_mode)
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{
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struct mlx5_ib_dev *dev = to_mdev(pd->device);
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int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
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@ -1673,16 +1676,17 @@ static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd,
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mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
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MLX5_SET(mkc, mkc, free, 1);
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MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
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if (access_mode == MLX5_MKC_ACCESS_MODE_MTT)
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MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
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MLX5_SET(mkc, mkc, qpn, 0xffffff);
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MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
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mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
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mr->access_mode = access_mode;
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err = mlx5_alloc_priv_descs(pd->device, mr,
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ndescs, sizeof(struct mlx5_klm));
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err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size);
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if (err)
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goto err_free_in;
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mr->desc_size = sizeof(struct mlx5_klm);
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mr->desc_size = desc_size;
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mr->max_descs = ndescs;
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MLX5_SET(mkc, mkc, access_mode_1_0, mr->access_mode & 0x3);
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@ -1786,12 +1790,22 @@ static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd,
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mr->sig->sig_err_exists = false;
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/* Next UMR, Arm SIGERR */
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++mr->sig->sigerr_count;
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mr->pi_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg,
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max_num_meta_sg);
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if (IS_ERR(mr->pi_mr)) {
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err = PTR_ERR(mr->pi_mr);
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mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg,
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max_num_meta_sg,
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sizeof(struct mlx5_klm),
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MLX5_MKC_ACCESS_MODE_KLMS);
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if (IS_ERR(mr->klm_mr)) {
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err = PTR_ERR(mr->klm_mr);
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goto err_destroy_psv;
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}
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mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg,
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max_num_meta_sg,
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sizeof(struct mlx5_mtt),
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MLX5_MKC_ACCESS_MODE_MTT);
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if (IS_ERR(mr->mtt_mr)) {
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err = PTR_ERR(mr->mtt_mr);
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goto err_free_klm_mr;
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}
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} else {
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mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
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err = -EINVAL;
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@ -1816,9 +1830,14 @@ static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd,
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return &mr->ibmr;
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err_free_pi_mr:
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if (mr->pi_mr) {
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dereg_mr(to_mdev(mr->pi_mr->ibmr.device), mr->pi_mr);
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mr->pi_mr = NULL;
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if (mr->mtt_mr) {
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dereg_mr(to_mdev(mr->mtt_mr->ibmr.device), mr->mtt_mr);
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mr->mtt_mr = NULL;
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}
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err_free_klm_mr:
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if (mr->klm_mr) {
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dereg_mr(to_mdev(mr->klm_mr->ibmr.device), mr->klm_mr);
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mr->klm_mr = NULL;
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}
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err_destroy_psv:
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if (mr->sig) {
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@ -2056,16 +2075,95 @@ static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
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return 0;
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}
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int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
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static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr)
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{
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struct mlx5_ib_mr *mr = to_mmr(ibmr);
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__be64 *descs;
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if (unlikely(mr->ndescs + mr->meta_ndescs == mr->max_descs))
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return -ENOMEM;
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descs = mr->descs;
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descs[mr->ndescs + mr->meta_ndescs++] =
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cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
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return 0;
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}
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static int
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mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
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int data_sg_nents, unsigned int *data_sg_offset,
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struct scatterlist *meta_sg, int meta_sg_nents,
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unsigned int *meta_sg_offset)
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{
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struct mlx5_ib_mr *mr = to_mmr(ibmr);
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struct mlx5_ib_mr *pi_mr = mr->pi_mr;
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struct mlx5_ib_mr *pi_mr = mr->mtt_mr;
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int n;
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u64 iova;
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WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY);
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pi_mr->ndescs = 0;
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pi_mr->meta_ndescs = 0;
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pi_mr->meta_length = 0;
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ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
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pi_mr->desc_size * pi_mr->max_descs,
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DMA_TO_DEVICE);
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pi_mr->ibmr.page_size = ibmr->page_size;
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n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset,
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mlx5_set_page);
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if (n != data_sg_nents)
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return n;
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iova = pi_mr->ibmr.iova;
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pi_mr->data_length = pi_mr->ibmr.length;
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pi_mr->ibmr.length = pi_mr->data_length;
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ibmr->length = pi_mr->data_length;
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if (meta_sg_nents) {
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u64 page_mask = ~((u64)ibmr->page_size - 1);
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n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents,
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meta_sg_offset, mlx5_set_page_pi);
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pi_mr->meta_length = pi_mr->ibmr.length;
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/*
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* PI address for the HW is the offset of the metadata address
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* relative to the first data page address.
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* It equals to first data page address + size of data pages +
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* metadata offset at the first metadata page
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*/
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pi_mr->pi_iova = (iova & page_mask) +
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pi_mr->ndescs * ibmr->page_size +
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(pi_mr->ibmr.iova & ~page_mask);
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/*
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* In order to use one MTT MR for data and metadata, we register
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* also the gaps between the end of the data and the start of
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* the metadata (the sig MR will verify that the HW will access
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* to right addresses). This mapping is safe because we use
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* internal mkey for the registration.
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*/
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pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova;
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pi_mr->ibmr.iova = iova;
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ibmr->length += pi_mr->meta_length;
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}
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ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
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pi_mr->desc_size * pi_mr->max_descs,
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DMA_TO_DEVICE);
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return n;
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}
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static int
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mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
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int data_sg_nents, unsigned int *data_sg_offset,
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struct scatterlist *meta_sg, int meta_sg_nents,
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unsigned int *meta_sg_offset)
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{
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struct mlx5_ib_mr *mr = to_mmr(ibmr);
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struct mlx5_ib_mr *pi_mr = mr->klm_mr;
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int n;
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pi_mr->ndescs = 0;
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pi_mr->meta_ndescs = 0;
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@ -2078,19 +2176,56 @@ int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
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n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset,
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meta_sg, meta_sg_nents, meta_sg_offset);
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/* This is zero-based memory region */
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pi_mr->ibmr.iova = 0;
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ibmr->length = pi_mr->ibmr.length;
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ibmr->iova = pi_mr->ibmr.iova;
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ibmr->sig_attrs->meta_length = pi_mr->meta_length;
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ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
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pi_mr->desc_size * pi_mr->max_descs,
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DMA_TO_DEVICE);
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/* This is zero-based memory region */
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pi_mr->ibmr.iova = 0;
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pi_mr->pi_iova = pi_mr->data_length;
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ibmr->length = pi_mr->ibmr.length;
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return n;
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}
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int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
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int data_sg_nents, unsigned int *data_sg_offset,
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struct scatterlist *meta_sg, int meta_sg_nents,
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unsigned int *meta_sg_offset)
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{
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struct mlx5_ib_mr *mr = to_mmr(ibmr);
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struct mlx5_ib_mr *pi_mr = mr->mtt_mr;
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int n;
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WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY);
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/*
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* As a performance optimization, if possible, there is no need to map
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* the sg lists to KLM descriptors. First try to map the sg lists to MTT
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* descriptors and fallback to KLM only in case of a failure.
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* It's more efficient for the HW to work with MTT descriptors
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* (especially in high load).
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* Use KLM (indirect access) only if it's mandatory.
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*/
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n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents,
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data_sg_offset, meta_sg, meta_sg_nents,
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meta_sg_offset);
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if (n == data_sg_nents + meta_sg_nents)
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goto out;
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pi_mr = mr->klm_mr;
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n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents,
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data_sg_offset, meta_sg, meta_sg_nents,
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meta_sg_offset);
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if (unlikely(n != data_sg_nents + meta_sg_nents))
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return -ENOMEM;
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out:
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/* This is zero-based memory region */
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ibmr->iova = 0;
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mr->pi_mr = pi_mr;
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ibmr->sig_attrs->meta_length = pi_mr->meta_length;
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return 0;
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}
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@ -4566,7 +4566,7 @@ static int set_sig_data_segment(const struct ib_send_wr *send_wr,
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if (pi_mr->meta_ndescs) {
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prot_len = pi_mr->meta_length;
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prot_key = pi_mr->ibmr.lkey;
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prot_va = pi_mr->ibmr.iova + data_len;
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prot_va = pi_mr->pi_iova;
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prot = true;
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}
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