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drm/i915: Use the engine class to get the context size 

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

v3: Rebased

v4: Restore the interface back to hiding the class lookup (Chris)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491905472-16189-1-git-send-email-oscar.mateo@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Daniele Ceraolo Spurio 2017-04-11 03:11:12 -07:00 committed by Chris Wilson
parent 5f9be05432
commit ddfb570c20
1 changed files with 19 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -1923,21 +1923,30 @@ populate_lr_context(struct i915_gem_context *ctx,
*/
uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
{
int ret = 0;
struct drm_i915_private *dev_priv = engine->i915;
int ret;
WARN_ON(INTEL_GEN(engine->i915) < 8);
WARN_ON(INTEL_GEN(dev_priv) < 8);
switch (engine->id) {
case RCS:
if (INTEL_GEN(engine->i915) >= 9)
switch (engine->class) {
case RENDER_CLASS:
switch (INTEL_GEN(dev_priv)) {
default:
MISSING_CASE(INTEL_GEN(dev_priv));
case 9:
ret = GEN9_LR_CONTEXT_RENDER_SIZE;
else
break;
case 8:
ret = GEN8_LR_CONTEXT_RENDER_SIZE;
break;
}
break;
case VCS:
case BCS:
case VECS:
case VCS2:
default:
MISSING_CASE(engine->class);
case VIDEO_DECODE_CLASS:
case VIDEO_ENHANCEMENT_CLASS:
case COPY_ENGINE_CLASS:
ret = GEN8_LR_CONTEXT_OTHER_SIZE;
break;
}