scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips
This patch adds UFS support for MediaTek SoC chips. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Stanley Chu
Martin K. Petersen
parent
1dfb86628d
commit
ddd90623ce
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@ -108,6 +108,20 @@ config SCSI_UFS_QCOM
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Select this if you have UFS controller on QCOM chipset.
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If unsure, say N.
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config SCSI_UFS_MEDIATEK
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tristate "Mediatek specific hooks to UFS controller platform driver"
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depends on SCSI_UFSHCD_PLATFORM && ARCH_MEDIATEK
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select PHY_MTK_UFS
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help
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This selects the Mediatek specific additions to UFSHCD platform driver.
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UFS host on Mediatek needs some vendor specific configuration before
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accessing the hardware which includes PHY configuration and vendor
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specific registers.
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Select this if you have UFS controller on Mediatek chipset.
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If unsure, say N.
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config SCSI_UFS_HISI
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tristate "Hisilicon specific hooks to UFS controller platform driver"
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depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM
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@ -10,3 +10,4 @@ ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o
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obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
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obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
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obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
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obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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@ -0,0 +1,367 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Authors:
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* Stanley Chu <stanley.chu@mediatek.com>
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* Peter Wang <peter.wang@mediatek.com>
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include "ufshcd.h"
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#include "ufshcd-pltfrm.h"
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#include "unipro.h"
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#include "ufs-mediatek.h"
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void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
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{
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u32 tmp;
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if (enable) {
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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tmp = tmp |
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(1 << RX_SYMBOL_CLK_GATE_EN) |
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(1 << SYS_CLK_GATE_EN) |
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(1 << TX_CLK_GATE_EN);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
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tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
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} else {
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
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(1 << SYS_CLK_GATE_EN) |
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(1 << TX_CLK_GATE_EN));
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
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tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
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}
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}
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int ufs_mtk_bind_mphy(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct device *dev = hba->dev;
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struct device_node *np = dev->of_node;
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int err = 0;
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host->mphy = devm_of_phy_get_by_index(dev, np, 0);
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if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
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/*
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* UFS driver might be probed before the phy driver does.
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* In that case we would like to return EPROBE_DEFER code.
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*/
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err = -EPROBE_DEFER;
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dev_info(dev,
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"%s: required phy hasn't probed yet. err = %d\n",
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__func__, err);
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} else if (IS_ERR(host->mphy)) {
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err = PTR_ERR(host->mphy);
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dev_info(dev, "%s: PHY get failed %d\n", __func__, err);
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}
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if (err)
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host->mphy = NULL;
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return err;
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}
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/**
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* ufs_mtk_setup_clocks - enables/disable clocks
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* @hba: host controller instance
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* @on: If true, enable clocks else disable them.
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* @status: PRE_CHANGE or POST_CHANGE notify
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*
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* Returns 0 on success, non-zero on failure.
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*/
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static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
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enum ufs_notify_change_status status)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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int ret;
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/*
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* In case ufs_mtk_init() is not yet done, simply ignore.
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* This ufs_mtk_setup_clocks() shall be called from
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* ufs_mtk_init() after init is done.
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*/
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if (!host)
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return 0;
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switch (status) {
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case PRE_CHANGE:
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if (!on)
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ret = phy_power_off(host->mphy);
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break;
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case POST_CHANGE:
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if (on)
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ret = phy_power_on(host->mphy);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/**
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* ufs_mtk_init - find other essential mmio bases
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* @hba: host controller instance
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*
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* Binds PHY with controller and powers up PHY enabling clocks
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* and regulators.
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*
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* Returns -EPROBE_DEFER if binding fails, returns negative error
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* on phy power up failure and returns zero on success.
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*/
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static int ufs_mtk_init(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host;
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struct device *dev = hba->dev;
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int err = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host) {
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err = -ENOMEM;
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dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
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goto out;
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}
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host->hba = hba;
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ufshcd_set_variant(hba, host);
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err = ufs_mtk_bind_mphy(hba);
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if (err)
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goto out_variant_clear;
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/*
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* ufshcd_vops_init() is invoked after
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* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
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* phy clock setup is skipped.
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*
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* Enable phy clocks specifically here.
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*/
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ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
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goto out;
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out_variant_clear:
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ufshcd_set_variant(hba, NULL);
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out:
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return err;
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}
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static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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struct ufs_dev_params host_cap;
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int ret;
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host_cap.tx_lanes = UFS_MTK_LIMIT_NUM_LANES_TX;
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host_cap.rx_lanes = UFS_MTK_LIMIT_NUM_LANES_RX;
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host_cap.hs_rx_gear = UFS_MTK_LIMIT_HSGEAR_RX;
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host_cap.hs_tx_gear = UFS_MTK_LIMIT_HSGEAR_TX;
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host_cap.pwm_rx_gear = UFS_MTK_LIMIT_PWMGEAR_RX;
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host_cap.pwm_tx_gear = UFS_MTK_LIMIT_PWMGEAR_TX;
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host_cap.rx_pwr_pwm = UFS_MTK_LIMIT_RX_PWR_PWM;
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host_cap.tx_pwr_pwm = UFS_MTK_LIMIT_TX_PWR_PWM;
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host_cap.rx_pwr_hs = UFS_MTK_LIMIT_RX_PWR_HS;
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host_cap.tx_pwr_hs = UFS_MTK_LIMIT_TX_PWR_HS;
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host_cap.hs_rate = UFS_MTK_LIMIT_HS_RATE;
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host_cap.desired_working_mode =
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UFS_MTK_LIMIT_DESIRED_MODE;
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ret = ufshcd_get_pwr_dev_param(&host_cap,
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dev_max_params,
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dev_req_params);
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if (ret) {
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pr_info("%s: failed to determine capabilities\n",
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__func__);
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}
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return ret;
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}
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static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status stage,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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int ret = 0;
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switch (stage) {
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case PRE_CHANGE:
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ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
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dev_req_params);
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break;
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case POST_CHANGE:
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int ufs_mtk_pre_link(struct ufs_hba *hba)
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{
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int ret;
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u32 tmp;
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/* disable deep stall */
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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if (ret)
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return ret;
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tmp &= ~(1 << 6);
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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return ret;
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}
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static int ufs_mtk_post_link(struct ufs_hba *hba)
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{
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/* disable device LCC */
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
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/* enable unipro clock gating feature */
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ufs_mtk_cfg_unipro_cg(hba, true);
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return 0;
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}
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static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status stage)
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{
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int ret = 0;
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switch (stage) {
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case PRE_CHANGE:
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ret = ufs_mtk_pre_link(hba);
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break;
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case POST_CHANGE:
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ret = ufs_mtk_post_link(hba);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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if (ufshcd_is_link_hibern8(hba))
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phy_power_off(host->mphy);
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return 0;
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}
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static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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if (ufshcd_is_link_hibern8(hba))
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phy_power_on(host->mphy);
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return 0;
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}
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/**
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* struct ufs_hba_mtk_vops - UFS MTK specific variant operations
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*
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* The variant operations configure the necessary controller and PHY
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* handshake during initialization.
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*/
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static struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
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.name = "mediatek.ufshci",
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.init = ufs_mtk_init,
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.setup_clocks = ufs_mtk_setup_clocks,
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.link_startup_notify = ufs_mtk_link_startup_notify,
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.pwr_change_notify = ufs_mtk_pwr_change_notify,
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.suspend = ufs_mtk_suspend,
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.resume = ufs_mtk_resume,
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};
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/**
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* ufs_mtk_probe - probe routine of the driver
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* @pdev: pointer to Platform device handle
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*
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* Return zero for success and non-zero for failure
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*/
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static int ufs_mtk_probe(struct platform_device *pdev)
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{
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int err;
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struct device *dev = &pdev->dev;
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/* perform generic probe */
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err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
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if (err)
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dev_info(dev, "probe failed %d\n", err);
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return err;
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}
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/**
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* ufs_mtk_remove - set driver_data of the device to NULL
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* @pdev: pointer to platform device handle
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*
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* Always return 0
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*/
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static int ufs_mtk_remove(struct platform_device *pdev)
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{
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struct ufs_hba *hba = platform_get_drvdata(pdev);
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pm_runtime_get_sync(&(pdev)->dev);
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ufshcd_remove(hba);
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return 0;
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}
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const struct of_device_id ufs_mtk_of_match[] = {
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{ .compatible = "mediatek,mt8183-ufshci"},
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{},
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};
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static const struct dev_pm_ops ufs_mtk_pm_ops = {
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.suspend = ufshcd_pltfrm_suspend,
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.resume = ufshcd_pltfrm_resume,
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.runtime_suspend = ufshcd_pltfrm_runtime_suspend,
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.runtime_resume = ufshcd_pltfrm_runtime_resume,
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.runtime_idle = ufshcd_pltfrm_runtime_idle,
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};
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static struct platform_driver ufs_mtk_pltform = {
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.probe = ufs_mtk_probe,
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.remove = ufs_mtk_remove,
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.shutdown = ufshcd_pltfrm_shutdown,
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.driver = {
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.name = "ufshcd-mtk",
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.owner = THIS_MODULE,
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.pm = &ufs_mtk_pm_ops,
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.of_match_table = ufs_mtk_of_match,
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},
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};
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module_platform_driver(ufs_mtk_pltform);
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@ -0,0 +1,53 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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/*
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* Vendor specific pre-defined parameters
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*/
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#define UFS_MTK_LIMIT_NUM_LANES_RX 1
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#define UFS_MTK_LIMIT_NUM_LANES_TX 1
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#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3
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#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3
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#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
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#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
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#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
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#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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struct ufs_mtk_host {
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struct ufs_hba *hba;
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struct phy *mphy;
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};
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#endif /* !_UFS_MEDIATEK_H */
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