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Staging: sxg: Commenting style fixes - Pending work 

This patch cleans up the comment. Converts the comments to C89 style.
Fixes comment related TODO item.

Signed-off-by: LinSysSoft Sahara Team <saharaproj@linsyssoft.com>
Signed-off-by: Christopher Harrer <charrer@alacritech.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mithlesh Thukral 2009-01-05 21:15:29 +05:30 committed by Greg Kroah-Hartman
parent 942798b462
commit ddd6f0a8c9
7 changed files with 1648 additions and 1566 deletions
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623
drivers/staging/sxg/sxg.c
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520
drivers/staging/sxg/sxg.h
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@ -43,78 +43,78 @@
#define __SXG_DRIVER_H__ #define __SXG_DRIVER_H__
#define p_net_device struct net_device * #define p_net_device struct net_device *
// struct sxg_stats - Probably move these to someplace where /*
// the slicstat (sxgstat?) program can get them. * struct sxg_stats - Probably move these to someplace where
* the slicstat (sxgstat?) program can get them.
*/
struct sxg_stats { struct sxg_stats {
// Xmt /* Xmt */
u32 XmtNBL; // Offload send NBL count u32 XmtNBL; /* Offload send NBL count */
u64 DumbXmtBytes; // Dumbnic send bytes u64 DumbXmtBytes; /* Dumbnic send bytes */
u64 SlowXmtBytes; // Slowpath send bytes u64 SlowXmtBytes; /* Slowpath send bytes */
u64 FastXmtBytes; // Fastpath send bytes u64 FastXmtBytes; /* Fastpath send bytes */
u64 DumbXmtPkts; // Dumbnic send packets u64 DumbXmtPkts; /* Dumbnic send packets */
u64 SlowXmtPkts; // Slowpath send packets u64 SlowXmtPkts; /* Slowpath send packets */
u64 FastXmtPkts; // Fastpath send packets u64 FastXmtPkts; /* Fastpath send packets */
u64 DumbXmtUcastPkts; // directed packets u64 DumbXmtUcastPkts; /* directed packets */
u64 DumbXmtMcastPkts; // Multicast packets u64 DumbXmtMcastPkts; /* Multicast packets */
u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV u64 DumbXmtBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT u64 DumbXmtUcastBytes; /* OID_GEN_DIRECTED_BYTES_XMIT */
u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT u64 DumbXmtMcastBytes; /* OID_GEN_MULTICAST_BYTES_XMIT */
u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT u64 DumbXmtBcastBytes; /* OID_GEN_BROADCAST_BYTES_XMIT */
u64 XmtErrors; // OID_GEN_XMIT_ERROR u64 XmtErrors; /* OID_GEN_XMIT_ERROR */
u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS u64 XmtDiscards; /* OID_GEN_XMIT_DISCARDS */
u64 XmtOk; // OID_GEN_XMIT_OK u64 XmtOk; /* OID_GEN_XMIT_OK */
u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH u64 XmtQLen; /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
u64 XmtZeroFull; // Transmit ring zero full u64 XmtZeroFull; /* Transmit ring zero full */
// Rcv /* Rcv */
u32 RcvNBL; // Offload recieve NBL count u32 RcvNBL; /* Offload recieve NBL count */
u64 DumbRcvBytes; // dumbnic recv bytes u64 DumbRcvBytes; /* dumbnic recv bytes */
u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV u64 DumbRcvUcastBytes; /* OID_GEN_DIRECTED_BYTES_RCV */
u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV u64 DumbRcvMcastBytes; /* OID_GEN_MULTICAST_BYTES_RCV */
u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV u64 DumbRcvBcastBytes; /* OID_GEN_BROADCAST_BYTES_RCV */
u64 SlowRcvBytes; // Slowpath recv bytes u64 SlowRcvBytes; /* Slowpath recv bytes */
u64 FastRcvBytes; // Fastpath recv bytes u64 FastRcvBytes; /* Fastpath recv bytes */
u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV u64 DumbRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
u64 DumbRcvTcpPkts; // See SxgCollectStats u64 DumbRcvTcpPkts; /* See SxgCollectStats */
u64 DumbRcvUcastPkts; // directed packets u64 DumbRcvUcastPkts; /* directed packets */
u64 DumbRcvMcastPkts; // Multicast packets u64 DumbRcvMcastPkts; /* Multicast packets */
u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV u64 DumbRcvBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV u64 SlowRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
u64 RcvErrors; // OID_GEN_RCV_ERROR u64 RcvErrors; /* OID_GEN_RCV_ERROR */
u64 RcvDiscards; // OID_GEN_RCV_DISCARDS u64 RcvDiscards; /* OID_GEN_RCV_DISCARDS */
u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER u64 RcvNoBuffer; /* OID_GEN_RCV_NO_BUFFER */
u64 PdqFull; // Processed Data Queue Full u64 PdqFull; /* Processed Data Queue Full */
u64 EventRingFull; // Event ring full u64 EventRingFull; /* Event ring full */
// Verbose stats /* Verbose stats */
u64 MaxSends; // Max sends outstanding u64 MaxSends; /* Max sends outstanding */
u64 NoSglBuf; // SGL buffer allocation failure u64 NoSglBuf; /* SGL buffer allocation failure */
u64 SglFail; // NDIS SGL failure u64 SglFail; /* NDIS SGL failure */
u64 SglAsync; // NDIS SGL failure u64 SglAsync; /* NDIS SGL failure */
u64 NoMem; // Memory allocation failure u64 NoMem; /* Memory allocation failure */
u64 NumInts; // Interrupts u64 NumInts; /* Interrupts */
u64 FalseInts; // Interrupt with ISR == 0 u64 FalseInts; /* Interrupt with ISR == 0 */
u64 XmtDrops; // No sahara DRAM buffer for xmt u64 XmtDrops; /* No sahara DRAM buffer for xmt */
// Sahara receive status /* Sahara receive status */
u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM u64 TransportCsum; /* SXG_RCV_STATUS_TRANSPORT_CSUM */
u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW u64 TransportUflow; /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN u64 TransportHdrLen; /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM: u64 NetworkCsum; /* SXG_RCV_STATUS_NETWORK_CSUM: */
u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW: u64 NetworkUflow; /* SXG_RCV_STATUS_NETWORK_UFLOW: */
u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN: u64 NetworkHdrLen; /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
u64 Parity; // SXG_RCV_STATUS_PARITY u64 Parity; /* SXG_RCV_STATUS_PARITY */
u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY: u64 LinkParity; /* SXG_RCV_STATUS_LINK_PARITY: */
u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY: u64 LinkEarly; /* SXG_RCV_STATUS_LINK_EARLY: */
u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW: u64 LinkBufOflow; /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE: u64 LinkCode; /* SXG_RCV_STATUS_LINK_CODE: */
u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE: u64 LinkDribble; /* SXG_RCV_STATUS_LINK_DRIBBLE: */
u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC: u64 LinkCrc; /* SXG_RCV_STATUS_LINK_CRC: */
u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW: u64 LinkOflow; /* SXG_RCV_STATUS_LINK_OFLOW: */
u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW: u64 LinkUflow; /* SXG_RCV_STATUS_LINK_UFLOW: */
}; };
/**************************************************************************** /* DUMB-NIC Send path definitions */
* DUMB-NIC Send path definitions
****************************************************************************/
#define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \ #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
ASSERT(_skb); \ ASSERT(_skb); \
@ -126,17 +126,17 @@ struct sxg_stats {
dev_kfree_skb(_skb); \ dev_kfree_skb(_skb); \
} }
// Locate current receive header buffer location. Use this /*
// instead of RcvDataHdr->VirtualAddress since the data * Locate current receive header buffer location. Use this
// may have been offset by SXG_ADVANCE_MDL_OFFSET * instead of RcvDataHdr->VirtualAddress since the data
* may have been offset by SXG_ADVANCE_MDL_OFFSET
*/
#define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
/************************************************************************ /* Dumb-NIC receive processing */
* Dumb-NIC receive processing /* Define an SXG_PACKET as an NDIS_PACKET */
************************************************************************/
// Define an SXG_PACKET as an NDIS_PACKET
#define PSXG_PACKET struct sk_buff * #define PSXG_PACKET struct sk_buff *
// Indications array size /* Indications array size */
#define SXG_RCV_ARRAYSIZE 64 #define SXG_RCV_ARRAYSIZE 64
#define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \ #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \
@ -156,9 +156,11 @@ struct sxg_stats {
} \ } \
} }
// Macro to add a NDIS_PACKET to an indication array /*
// If we fill up our array of packet pointers, then indicate this * Macro to add a NDIS_PACKET to an indication array
// block up now and start on a new one. * If we fill up our array of packet pointers, then indicate this
* block up now and start on a new one.
*/
#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \ #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
(_IndicationList)[_NumPackets] = (_Packet); \ (_IndicationList)[_NumPackets] = (_Packet); \
(_NumPackets)++; \ (_NumPackets)++; \
@ -182,7 +184,7 @@ struct sxg_stats {
#define SXG_REINIATIALIZE_PACKET(_Packet) \ #define SXG_REINIATIALIZE_PACKET(_Packet) \
{} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */ {} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
// Definitions to initialize Dumb-nic Receive NBLs /* Definitions to initialize Dumb-nic Receive NBLs */
#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr) #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \ #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
@ -210,10 +212,10 @@ struct sxg_stats {
skb_put(Packet, (_Event)->Length); \ skb_put(Packet, (_Event)->Length); \
} }
/////////////////////////////////////////////////////////////////////////////// /*
// Macros to free a receive data buffer and receive data descriptor block * Macros to free a receive data buffer and receive data descriptor block
/////////////////////////////////////////////////////////////////////////////// * NOTE - Lock must be held with RCV macros
// NOTE - Lock must be held with RCV macros */
#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \ #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
struct list_entry *_ple; \ struct list_entry *_ple; \
_Hdr = NULL; \ _Hdr = NULL; \
@ -246,7 +248,7 @@ struct sxg_stats {
InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \ InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
} }
// SGL macros /* SGL macros */
#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \ #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
spin_lock(&(_pAdapt)->SglQLock); \ spin_lock(&(_pAdapt)->SglQLock); \
(_pAdapt)->FreeSglBufferCount++; \ (_pAdapt)->FreeSglBufferCount++; \
@ -257,11 +259,13 @@ struct sxg_stats {
spin_unlock(&(_pAdapt)->SglQLock); \ spin_unlock(&(_pAdapt)->SglQLock); \
} }
// Get an SGL buffer from the free queue. The first part of this macro /*
// attempts to keep ahead of buffer depletion by allocating more when * Get an SGL buffer from the free queue. The first part of this macro
// we hit a minimum threshold. Note that we don't grab the lock * attempts to keep ahead of buffer depletion by allocating more when
// until after that. We're dealing with round numbers here, so we don't need to, * we hit a minimum threshold. Note that we don't grab the lock
// and not grabbing it avoids a possible double-trip. * until after that. We're dealing with round numbers here, so we don't need to,
* and not grabbing it avoids a possible double-trip.
*/
#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \ #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
struct list_entry *_ple; \ struct list_entry *_ple; \
if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \ if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
@ -285,28 +289,30 @@ struct sxg_stats {
spin_unlock(&(_pAdapt)->SglQLock); \ spin_unlock(&(_pAdapt)->SglQLock); \
} }
// /*
// struct sxg_multicast_address * struct sxg_multicast_address
// * Linked list of multicast addresses.
// Linked list of multicast addresses. */
struct sxg_multicast_address { struct sxg_multicast_address {
unsigned char Address[6]; unsigned char Address[6];
struct sxg_multicast_address *Next; struct sxg_multicast_address *Next;
}; };
// Structure to maintain chimney send and receive buffer queues. /*
// This structure maintains NET_BUFFER_LIST queues that are * Structure to maintain chimney send and receive buffer queues.
// given to us via the Chimney MiniportTcpOffloadSend and * This structure maintains NET_BUFFER_LIST queues that are
// MiniportTcpOffloadReceive routines. This structure DOES NOT * given to us via the Chimney MiniportTcpOffloadSend and
// manage our data buffer queue * MiniportTcpOffloadReceive routines. This structure DOES NOT
* manage our data buffer queue
*/
struct sxg_buffer_queue { struct sxg_buffer_queue {
u32 Type; // Slow or fast - See below u32 Type; /* Slow or fast - See below */
u32 Direction; // Xmt or Rcv u32 Direction; /* Xmt or Rcv */
u32 Bytes; // Byte count u32 Bytes; /* Byte count */
u32 * Head; // Send queue head u32 * Head; /* Send queue head */
u32 * Tail; // Send queue tail u32 * Tail; /* Send queue tail */
// PNET_BUFFER_LIST NextNBL; // Short cut - next NBL /* PNET_BUFFER_LIST NextNBL;*/ /* Short cut - next NBL */
// PNET_BUFFER NextNB; // Short cut - next NB /* PNET_BUFFER NextNB; */ /* Short cut - next NB */
}; };
#define SXG_SLOW_SEND_BUFFER 0 #define SXG_SLOW_SEND_BUFFER 0
@ -329,64 +335,66 @@ struct sxg_buffer_queue {
#define SXG_RSS_CPU_COUNT(_pAdapt) \ #define SXG_RSS_CPU_COUNT(_pAdapt) \
((_pAdapt)->RssEnabled ? NR_CPUS : 1) ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
/**************************************************************************** /* DRIVER and ADAPTER structures */
* DRIVER and ADAPTER structures
****************************************************************************/
// Adapter states - These states closely match the adapter states /*
// documented in the DDK (with a few exceptions). * Adapter states - These states closely match the adapter states
* documented in the DDK (with a few exceptions).
*/
enum SXG_STATE { enum SXG_STATE {
SXG_STATE_INITIALIZING, // Initializing SXG_STATE_INITIALIZING, /* Initializing */
SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode SXG_STATE_BOOTDIAG, /* Boot-Diagnostic mode */
SXG_STATE_PAUSING, // Pausing SXG_STATE_PAUSING, /* Pausing */
SXG_STATE_PAUSED, // Paused SXG_STATE_PAUSED, /* Paused */
SXG_STATE_RUNNING, // Running SXG_STATE_RUNNING, /* Running */
SXG_STATE_RESETTING, // Reset in progress SXG_STATE_RESETTING, /* Reset in progress */
SXG_STATE_SLEEP, // Sleeping SXG_STATE_SLEEP, /* Sleeping */
SXG_STATE_DIAG, // Diagnostic mode SXG_STATE_DIAG, /* Diagnostic mode */
SXG_STATE_HALTING, // Halting SXG_STATE_HALTING, /* Halting */
SXG_STATE_HALTED, // Down or not-initialized SXG_STATE_HALTED, /* Down or not-initialized */
SXG_STATE_SHUTDOWN // shutdown SXG_STATE_SHUTDOWN /* shutdown */
}; };
// Link state /* Link state */
enum SXG_LINK_STATE { enum SXG_LINK_STATE {
SXG_LINK_DOWN, SXG_LINK_DOWN,
SXG_LINK_UP SXG_LINK_UP
}; };
// Link initialization timeout in 100us units /* Link initialization timeout in 100us units */
#define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE! #define SXG_LINK_TIMEOUT 100000 /* 10 Seconds - REDUCE! */
// Microcode file selection codes /* Microcode file selection codes */
enum SXG_UCODE_SEL { enum SXG_UCODE_SEL {
SXG_UCODE_SAHARA, // Sahara ucode SXG_UCODE_SAHARA, /* Sahara ucode */
SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */
SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */
}; };
#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt) #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
#define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt) #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
// This probably lives in a proto.h file. Move later /* This probably lives in a proto.h file. Move later */
#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01) #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
#define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \ #define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
(*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF)) (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
// For DbgPrints /* For DbgPrints */
#define SXG_ID DPFLTR_IHVNETWORK_ID #define SXG_ID DPFLTR_IHVNETWORK_ID
#define SXG_ERROR DPFLTR_ERROR_LEVEL #define SXG_ERROR DPFLTR_ERROR_LEVEL
// /*
// struct sxg_driver structure - * struct sxg_driver structure -
// *
// contains information about the sxg driver. There is only * contains information about the sxg driver. There is only
// one of these, and it is defined as a global. * one of these, and it is defined as a global.
*/
struct sxg_driver { struct sxg_driver {
struct adapter_t *Adapters; // Linked list of adapters struct adapter_t *Adapters; /* Linked list of adapters */
ushort AdapterID; // Maintain unique adapter ID ushort AdapterID; /* Maintain unique adapter ID */
}; };
#ifdef STATUS_SUCCESS #ifdef STATUS_SUCCESS
@ -404,12 +412,14 @@ struct sxg_driver {
#define SLIC_MAX_CARDS 32 #define SLIC_MAX_CARDS 32
#define SLIC_MAX_PORTS 4 /* Max # of ports per card */ #define SLIC_MAX_PORTS 4 /* Max # of ports per card */
#if SLIC_DUMP_ENABLED #if SLIC_DUMP_ENABLED
// Dump buffer size
// /*
// This cannot be bigger than the max DMA size the card supports, * Dump buffer size
// given the current code structure in the host and ucode. * This cannot be bigger than the max DMA size the card supports,
// Mojave supports 16K, Oasis supports 16K-1, so * given the current code structure in the host and ucode.
// just set this at 15K, shouldnt make that much of a diff. * Mojave supports 16K, Oasis supports 16K-1, so
* just set this at 15K, shouldnt make that much of a diff.
*/
#define DUMP_BUF_SIZE 0x3C00 #define DUMP_BUF_SIZE 0x3C00
#endif #endif
@ -560,123 +570,123 @@ struct adapter_t {
u32 rcv_interrupt_yields; u32 rcv_interrupt_yields;
u32 intagg_period; u32 intagg_period;
struct net_device_stats stats; struct net_device_stats stats;
u32 * MiniportHandle; // Our miniport handle u32 * MiniportHandle; /* Our miniport handle */
enum SXG_STATE State; // Adapter state enum SXG_STATE State; /* Adapter state */
enum SXG_LINK_STATE LinkState; // Link state enum SXG_LINK_STATE LinkState; /* Link state */
u64 LinkSpeed; // Link Speed u64 LinkSpeed; /* Link Speed */
u32 PowerState; // NDIS power state u32 PowerState; /* NDIS power state */
struct adapter_t *Next; // Linked list struct adapter_t *Next; /* Linked list */
ushort AdapterID; // 1..n ushort AdapterID; /* 1..n */
struct net_device * netdev; struct net_device * netdev;
struct net_device * next_netdevice; struct net_device * next_netdevice;
struct pci_dev * pcidev; struct pci_dev *pcidev;
struct sxg_multicast_address *MulticastAddrs; /* Multicast list */
u64 MulticastMask; /* Multicast mask */
u32 *InterruptHandle; /* Register Interrupt handle */
u32 InterruptLevel; /* From Resource list */
u32 InterruptVector; /* From Resource list */
spinlock_t AdapterLock; /* Serialize access adapter routines */
spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
struct sxg_hw_regs *HwRegs; /* Sahara HW Register Memory (BAR0/1) */
struct sxg_ucode_regs *UcodeRegs; /* Microcode Register Memory (BAR2/3) */
struct sxg_tcb_regs *TcbRegs; /* Same as Ucode regs - See sxghw.h */
ushort FrameSize; /* Maximum frame size */
u32 * DmaHandle; /* NDIS DMA handle */
u32 * PacketPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
u32 * BufferPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
u32 MacFilter; /* NDIS MAC Filter */
struct sxg_event_ring *EventRings; /* Host event rings. 1/CPU to 16 max */
dma_addr_t PEventRings; /* Physical address */
u32 NextEvent[SXG_MAX_RSS]; /* Current location in ring */
dma_addr_t PTcbBuffers; /* TCB Buffers - physical address */
dma_addr_t PTcbCompBuffers; /* TCB Composite Buffers - phys addr */
struct sxg_xmt_ring *XmtRings; /* Transmit rings */
dma_addr_t PXmtRings; /* Transmit rings - physical address */
struct sxg_ring_info XmtRingZeroInfo; /* Transmit ring 0 info */
struct sxg_multicast_address *MulticastAddrs; // Multicast list
u64 MulticastMask; // Multicast mask
u32 * InterruptHandle; // Register Interrupt handle
u32 InterruptLevel; // From Resource list
u32 InterruptVector; // From Resource list
spinlock_t AdapterLock; /* Serialize access adapter routines */
spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
struct sxg_hw_regs *HwRegs; // Sahara HW Register Memory (BAR0/1)
struct sxg_ucode_regs *UcodeRegs; // Microcode Register Memory (BAR2/3)
struct sxg_tcb_regs *TcbRegs; // Same as Ucode regs - See sxghw.h
ushort FrameSize; // Maximum frame size
u32 * DmaHandle; // NDIS DMA handle
u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
u32 MacFilter; // NDIS MAC Filter
struct sxg_event_ring *EventRings; // Host event rings. 1/CPU to 16 max
dma_addr_t PEventRings; // Physical address
u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
dma_addr_t PTcbBuffers; // TCB Buffers - physical address
dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
struct sxg_xmt_ring *XmtRings; // Transmit rings
dma_addr_t PXmtRings; // Transmit rings - physical address
struct sxg_ring_info XmtRingZeroInfo; // Transmit ring 0 info
spinlock_t XmtZeroLock; /* Transmit ring 0 lock */ spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
u32 * XmtRingZeroIndex; // Shared XMT ring 0 index u32 * XmtRingZeroIndex; /* Shared XMT ring 0 index */
dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical dma_addr_t PXmtRingZeroIndex; /* Shared XMT ring 0 index - physical */
struct list_entry FreeProtocolHeaders;// Free protocol headers struct list_entry FreeProtocolHeaders;/* Free protocol headers */
u32 FreeProtoHdrCount; // Count u32 FreeProtoHdrCount; /* Count */
void * ProtocolHeaders; // Block of protocol header void * ProtocolHeaders; /* Block of protocol header */
dma_addr_t PProtocolHeaders; // Block of protocol headers - phys dma_addr_t PProtocolHeaders; /* Block of protocol headers - phys */
struct sxg_rcv_ring *RcvRings; // Receive rings struct sxg_rcv_ring *RcvRings; /* Receive rings */
dma_addr_t PRcvRings; // Receive rings - physical address dma_addr_t PRcvRings; /* Receive rings - physical address */
struct sxg_ring_info RcvRingZeroInfo; // Receive ring 0 info struct sxg_ring_info RcvRingZeroInfo; /* Receive ring 0 info */
u32 * Isr; // Interrupt status register u32 * Isr; /* Interrupt status register */
dma_addr_t PIsr; // ISR - physical address dma_addr_t PIsr; /* ISR - physical address */
u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR u32 IsrCopy[SXG_MAX_RSS]; /* Copy of ISR */
ushort InterruptsEnabled; // Bitmask of enabled vectors ushort InterruptsEnabled; /* Bitmask of enabled vectors */
unsigned char * IndirectionTable; // RSS indirection table unsigned char *IndirectionTable; /* RSS indirection table */
dma_addr_t PIndirectionTable; // Physical address dma_addr_t PIndirectionTable; /* Physical address */
ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS ushort RssTableSize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS ushort HashKeySize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
unsigned char HashSecretKey[40]; // rss key unsigned char HashSecretKey[40]; /* rss key */
u32 HashInformation; u32 HashInformation;
// Receive buffer queues /* Receive buffer queues */
spinlock_t RcvQLock; /* Receive Queue Lock */ spinlock_t RcvQLock; /* Receive Queue Lock */
struct list_entry FreeRcvBuffers; // Free SXG_DATA_BUFFER queue struct list_entry FreeRcvBuffers; /* Free SXG_DATA_BUFFER queue */
struct list_entry FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q struct list_entry FreeRcvBlocks; /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
struct list_entry AllRcvBlocks; // All SXG_RCV_BLOCKs struct list_entry AllRcvBlocks; /* All SXG_RCV_BLOCKs */
ushort FreeRcvBufferCount; // Number of free rcv data buffers ushort FreeRcvBufferCount; /* Number of free rcv data buffers */
ushort FreeRcvBlockCount; // # of free rcv descriptor blocks ushort FreeRcvBlockCount; /* # of free rcv descriptor blocks */
ushort AllRcvBlockCount; // Number of total receive blocks ushort AllRcvBlockCount; /* Number of total receive blocks */
ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only ushort ReceiveBufferSize; /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
u32 AllocationsPending; // Receive allocation pending u32 AllocationsPending; /* Receive allocation pending */
u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card u32 RcvBuffersOnCard; /* SXG_DATA_BUFFERS owned by card */
// SGL buffers /* SGL buffers */
spinlock_t SglQLock; /* SGL Queue Lock */ spinlock_t SglQLock; /* SGL Queue Lock */
struct list_entry FreeSglBuffers; // Free SXG_SCATTER_GATHER struct list_entry FreeSglBuffers; /* Free struct sxg_scatter_gather */
struct list_entry AllSglBuffers; // All SXG_SCATTER_GATHER struct list_entry AllSglBuffers; /* All struct sxg_scatter_gather */
ushort FreeSglBufferCount; // Number of free SGL buffers ushort FreeSglBufferCount; /* Number of free SGL buffers */
ushort AllSglBufferCount; // Number of total SGL buffers ushort AllSglBufferCount; /* Number of total SGL buffers */
u32 CurrentTime; // Tick count u32 CurrentTime; /* Tick count */
u32 FastpathConnections;// # of fastpath connections u32 FastpathConnections;/* # of fastpath connections */
// Various single-bit flags: /* Various single-bit flags: */
u32 BasicAllocations:1; // Locks and listheads u32 BasicAllocations:1; /* Locks and listheads */
u32 IntRegistered:1; // Interrupt registered u32 IntRegistered:1; /* Interrupt registered */
u32 PingOutstanding:1; // Ping outstanding to card u32 PingOutstanding:1; /* Ping outstanding to card */
u32 Dead:1; // Card dead u32 Dead:1; /* Card dead */
u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request u32 DumpDriver:1; /* OID_SLIC_DRIVER_DUMP request */
u32 DumpCard:1; // OID_SLIC_CARD_DUMP request u32 DumpCard:1; /* OID_SLIC_CARD_DUMP request */
u32 DumpCmdRunning:1; // Dump command in progress u32 DumpCmdRunning:1; /* Dump command in progress */
u32 DebugRunning:1; // AGDB debug in progress u32 DebugRunning:1; /* AGDB debug in progress */
u32 JumboEnabled:1; // Jumbo frames enabled u32 JumboEnabled:1; /* Jumbo frames enabled */
u32 MsiEnabled:1; // MSI interrupt enabled u32 MsiEnabled:1; /* MSI interrupt enabled */
u32 RssEnabled:1; // RSS Enabled u32 RssEnabled:1; /* RSS Enabled */
u32 FailOnBadEeprom:1; // Fail on Bad Eeprom u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
u32 DiagStart:1; // Init adapter for diagnostic start u32 DiagStart:1; /* Init adapter for diagnostic start */
// Stats /* Stats */
u32 PendingRcvCount; // Outstanding rcv indications u32 PendingRcvCount; /* Outstanding rcv indications */
u32 PendingXmtCount; // Outstanding send requests u32 PendingXmtCount; /* Outstanding send requests */
struct sxg_stats Stats; // Statistics struct sxg_stats Stats; /* Statistics */
u32 ReassBufs; // Number of reassembly buffers u32 ReassBufs; /* Number of reassembly buffers */
// Card Crash Info /* Card Crash Info */
ushort CrashLocation; // Microcode crash location ushort CrashLocation; /* Microcode crash location */
unsigned char CrashCpu; // Sahara CPU ID unsigned char CrashCpu; /* Sahara CPU ID */
// Diagnostics /* Diagnostics */
// PDIAG_CMD DiagCmds; // List of free diagnostic commands /* PDIAG_CMD DiagCmds; */ /* List of free diagnostic commands */
// PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers /* PDIAG_BUFFER DiagBuffers; */ /* List of free diagnostic buffers */
// PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests /* PDIAG_REQ DiagReqQ; */ /* List of outstanding (asynchronous) diag requests */
// u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? /* u32 DiagCmdTimeout; */ /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
// unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) /* unsigned char DiagDmaDesc[DMA_CPU_CTXS]; */ /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
/*
///////////////////////////////////////////////////////////////////// * Put preprocessor-conditional fields at the end so we don't
// Put preprocessor-conditional fields at the end so we don't * have to recompile sxgdbg everytime we reconfigure the driver
// have to recompile sxgdbg everytime we reconfigure the driver */
/////////////////////////////////////////////////////////////////////
#if defined(CONFIG_X86) #if defined(CONFIG_X86)
u32 AddrUpper; // Upper 32 bits of 64-bit register u32 AddrUpper; /* Upper 32 bits of 64-bit register */
#endif #endif
//#if SXG_FAILURE_DUMP /*#if SXG_FAILURE_DUMP */
// NDIS_EVENT DumpThreadEvent; // syncronize dump thread /* NDIS_EVENT DumpThreadEvent; */ /* syncronize dump thread */
// BOOLEAN DumpThreadRunning; // termination flag /* BOOLEAN DumpThreadRunning; */ /* termination flag */
// PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer /* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
// dma_addr_t PDumpBuffer; // Physical address /* dma_addr_t PDumpBuffer; */ /* Physical address */
//#endif // SXG_FAILURE_DUMP /*#endif */ /* SXG_FAILURE_DUMP */
}; };
@ -685,12 +695,10 @@ struct adapter_t {
#define SLIC_DUMP_IN_PROGRESS 2 #define SLIC_DUMP_IN_PROGRESS 2
#define SLIC_DUMP_DONE 3 #define SLIC_DUMP_DONE 3
/**************************************************************************** /*
*
* Microcode crash information structure. This * Microcode crash information structure. This
* structure is written out to the card's SRAM when the microcode panic's. * structure is written out to the card's SRAM when the microcode panic's.
* */
****************************************************************************/
struct slic_crash_info { struct slic_crash_info {
ushort cpu_id; ushort cpu_id;
ushort crash_pc; ushort crash_pc;

2
drivers/staging/sxg/sxg_os.h
View File

@ -128,7 +128,7 @@ static __inline struct list_entry *RemoveTailList(struct list_entry *l)
#define SLIC_TIMESTAMP(value) #define SLIC_TIMESTAMP(value)
#endif #endif
/****************** SXG DEFINES *****************************************/ /* SXG DEFINES */
#ifdef ATKDBG #ifdef ATKDBG
#define SXG_TIMESTAMP(value) { \ #define SXG_TIMESTAMP(value) { \

14
drivers/staging/sxg/sxgdbg.h
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@ -100,9 +100,7 @@ struct trace_entry {
u32 arg4; /* Caller arg4 */ u32 arg4; /* Caller arg4 */
}; };
/* /* Driver types for driver field in struct trace_entry */
* Driver types for driver field in struct trace_entry
*/
#define TRACE_SXG 1 #define TRACE_SXG 1
#define TRACE_VPCI 2 #define TRACE_VPCI 2
#define TRACE_SLIC 3 #define TRACE_SLIC 3
@ -129,11 +127,7 @@ struct sxg_trace_buffer {
#define TRACE_NOISY 10 /* Everything in the world */ #define TRACE_NOISY 10 /* Everything in the world */
/********************************************************************** /* The macros themselves */
*
* The macros themselves -
*
*********************************************************************/
#if ATK_TRACE_ENABLED #if ATK_TRACE_ENABLED
#define SXG_TRACE_INIT(buffer, tlevel) \ #define SXG_TRACE_INIT(buffer, tlevel) \
{ \ { \
@ -146,9 +140,7 @@ struct sxg_trace_buffer {
#define SXG_TRACE_INIT(buffer, tlevel) #define SXG_TRACE_INIT(buffer, tlevel)
#endif #endif
/* /*The trace macro. This is active only if ATK_TRACE_ENABLED is set. */
* The trace macro. This is active only if ATK_TRACE_ENABLED is set.
*/
#if ATK_TRACE_ENABLED #if ATK_TRACE_ENABLED
#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4) { \ #define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4) { \
if ((buffer) && ((buffer)->level >= (tlevel))) { \ if ((buffer) && ((buffer)->level >= (tlevel))) { \

796
drivers/staging/sxg/sxghif.h
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File diff suppressed because it is too large Load Diff

1246
drivers/staging/sxg/sxghw.h
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File diff suppressed because it is too large Load Diff

13
drivers/staging/sxg/sxgphycode.h
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@ -1,23 +1,20 @@
/* /********************************************************************
* Copyright (C) 1997-2008 Alacritech, Inc. All rights reserved * Copyright (C) 1997-2008 Alacritech, Inc. All rights reserved
* *
* sxgphycode.h: * sxgphycode.h:
* *
* This file PHY microcode and register initialization data. * This file PHY microcode and register initialization data.
*/ ********************************************************************/
/********************************************************************** /*
* PHY Microcode * PHY Microcode
* *
* The following contains both PHY microcode and PHY register * The following contains both PHY microcode and PHY register
* initialization data. It is specific to both the PHY and the * initialization data. It is specific to both the PHY and the
* type of transceiver. * type of transceiver.
*
**********************************************************************/
/*
* Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR)
*/ */
/* Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR) */
static struct phy_ucode PhyUcode[] = { static struct phy_ucode PhyUcode[] = {
/* /*
* NOTE: An address of 0 is a special case. When the download routine * NOTE: An address of 0 is a special case. When the download routine