ASoC: SOF: Intel: Add APL/CNL HW DSP support
Add SOF hardware DSP support for Intel Apollolake and Cannonlake based devices. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Liam Girdwood
Mark Brown
parent
351d1174fe
commit
dd96daca6c
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@ -0,0 +1,671 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include <linux/module.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include "../ops.h"
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#include "hda.h"
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
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#include "../../codecs/hdac_hda.h"
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#endif
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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#include <sound/soc-acpi-intel-match.h>
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#endif
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/* platform specific devices */
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#include "shim.h"
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/*
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* Debug
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*/
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struct hda_dsp_msg_code {
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u32 code;
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const char *msg;
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};
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static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
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{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
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{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
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{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
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{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
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{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
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{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
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{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
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{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
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{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
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{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
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{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
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{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
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{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatble"},
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{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
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{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
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{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
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{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
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{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
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{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
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};
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static void hda_dsp_get_status_skl(struct snd_sof_dev *sdev)
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{
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u32 status;
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int i;
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status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_ADSP_FW_STATUS_SKL);
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for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
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if (status == hda_dsp_rom_msg[i].code) {
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dev_err(sdev->dev, "%s - code %8.8x\n",
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hda_dsp_rom_msg[i].msg, status);
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return;
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}
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}
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/* not for us, must be generic sof message */
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dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
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}
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static void hda_dsp_get_status(struct snd_sof_dev *sdev)
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{
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u32 status;
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int i;
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status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_ROM_STATUS);
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for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
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if (status == hda_dsp_rom_msg[i].code) {
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dev_err(sdev->dev, "%s - code %8.8x\n",
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hda_dsp_rom_msg[i].msg, status);
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return;
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}
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}
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/* not for us, must be generic sof message */
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dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
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}
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static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
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struct sof_ipc_dsp_oops_xtensa *xoops,
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struct sof_ipc_panic_info *panic_info,
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u32 *stack, size_t stack_words)
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{
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/* first read registers */
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sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset, xoops,
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sizeof(*xoops));
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/* then get panic info */
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sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset +
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sizeof(*xoops), panic_info, sizeof(*panic_info));
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/* then get the stack */
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sof_block_read(sdev, sdev->mmio_bar, sdev->dsp_oops_offset +
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sizeof(*xoops) + sizeof(*panic_info), stack,
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stack_words * sizeof(u32));
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}
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void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags)
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{
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[HDA_DSP_STACK_DUMP_SIZE];
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u32 status, panic;
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/* try APL specific status message types first */
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hda_dsp_get_status_skl(sdev);
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/* now try generic SOF status messages */
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status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_ADSP_ERROR_CODE_SKL);
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/*TODO: Check: there is no define in spec, but it is used in the code*/
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panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_ADSP_ERROR_CODE_SKL + 0x4);
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if (sdev->boot_complete) {
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hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
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HDA_DSP_STACK_DUMP_SIZE);
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snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
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stack, HDA_DSP_STACK_DUMP_SIZE);
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} else {
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dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
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status, panic);
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hda_dsp_get_status_skl(sdev);
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}
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}
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void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[HDA_DSP_STACK_DUMP_SIZE];
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u32 status, panic;
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/* try APL specific status message types first */
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hda_dsp_get_status(sdev);
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/* now try generic SOF status messages */
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status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_FW_STATUS);
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panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
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if (sdev->boot_complete) {
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hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
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HDA_DSP_STACK_DUMP_SIZE);
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snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
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stack, HDA_DSP_STACK_DUMP_SIZE);
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} else {
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dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
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status, panic);
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hda_dsp_get_status(sdev);
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}
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}
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static int hda_init(struct snd_sof_dev *sdev)
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{
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struct hda_bus *hbus;
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struct hdac_bus *bus;
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struct hdac_ext_bus_ops *ext_ops = NULL;
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struct pci_dev *pci = to_pci_dev(sdev->dev);
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int ret;
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hbus = sof_to_hbus(sdev);
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bus = sof_to_bus(sdev);
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/* HDA bus init */
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC)
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ext_ops = snd_soc_hdac_hda_get_ops();
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#endif
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sof_hda_bus_init(bus, &pci->dev, ext_ops);
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bus->use_posbuf = 1;
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bus->bdl_pos_adj = 0;
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mutex_init(&hbus->prepare_mutex);
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hbus->pci = pci;
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hbus->mixer_assigned = -1;
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hbus->modelname = "sofbus";
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/* initialise hdac bus */
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bus->addr = pci_resource_start(pci, 0);
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bus->remap_addr = pci_ioremap_bar(pci, 0);
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if (!bus->remap_addr) {
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dev_err(bus->dev, "error: ioremap error\n");
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return -ENXIO;
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}
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/* HDA base */
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sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
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/* get controller capabilities */
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ret = hda_dsp_ctrl_get_caps(sdev);
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if (ret < 0)
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dev_err(sdev->dev, "error: get caps error\n");
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return ret;
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
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const char *sof_tplg_filename)
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{
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const char *tplg_filename = NULL;
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char *filename;
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char *split_ext;
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filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
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if (!filename)
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return NULL;
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/* this assumes a .tplg extension */
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split_ext = strsep(&filename, ".");
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if (split_ext) {
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tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
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"%s-idisp.tplg", split_ext);
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if (!tplg_filename)
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return NULL;
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}
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return tplg_filename;
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}
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static int hda_init_caps(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_ext_link *hlink;
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struct snd_soc_acpi_mach_params *mach_params;
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struct snd_soc_acpi_mach *hda_mach;
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struct snd_sof_pdata *pdata = sdev->pdata;
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struct snd_soc_acpi_mach *mach;
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const char *tplg_filename;
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int codec_num = 0;
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int ret = 0;
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int i;
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device_disable_async_suspend(bus->dev);
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/* check if dsp is there */
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if (bus->ppcap)
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dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
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if (bus->mlcap)
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snd_hdac_ext_bus_get_ml_capabilities(bus);
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/* init i915 and HDMI codecs */
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ret = hda_codec_i915_init(sdev);
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if (ret < 0) {
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dev_err(sdev->dev, "error: no HDMI audio devices found\n");
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return ret;
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}
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ret = hda_dsp_ctrl_init_chip(sdev, true);
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if (ret < 0) {
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dev_err(bus->dev, "error: init chip failed with ret: %d\n", ret);
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goto out;
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}
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/* codec detection */
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if (!bus->codec_mask) {
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dev_info(bus->dev, "no hda codecs found!\n");
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} else {
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dev_info(bus->dev, "hda codecs found, mask %lx\n",
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bus->codec_mask);
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for (i = 0; i < HDA_MAX_CODECS; i++) {
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if (bus->codec_mask & (1 << i))
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codec_num++;
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}
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/*
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* If no machine driver is found, then:
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*
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* hda machine driver is used if :
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* 1. there is one HDMI codec and one external HDAudio codec
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* 2. only HDMI codec
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*/
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if (!pdata->machine && codec_num <= 2 &&
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HDA_IDISP_CODEC(bus->codec_mask)) {
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hda_mach = snd_soc_acpi_intel_hda_machines;
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pdata->machine = hda_mach;
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/* topology: use the info from hda_machines */
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pdata->tplg_filename =
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hda_mach->sof_tplg_filename;
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/* firmware: pick the first in machine list */
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mach = pdata->desc->machines;
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pdata->fw_filename = mach->sof_fw_filename;
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dev_info(bus->dev, "using HDA machine driver %s now\n",
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hda_mach->drv_name);
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/* fixup topology file for HDMI only platforms */
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if (codec_num == 1) {
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/* use local variable for readability */
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tplg_filename = pdata->tplg_filename;
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tplg_filename = fixup_tplg_name(sdev, tplg_filename);
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if (!tplg_filename)
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goto out;
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pdata->tplg_filename = tplg_filename;
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}
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}
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}
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/* used by hda machine driver to create dai links */
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if (pdata->machine) {
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mach_params = (struct snd_soc_acpi_mach_params *)
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&pdata->machine->mach_params;
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mach_params->codec_mask = bus->codec_mask;
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mach_params->platform = dev_name(sdev->dev);
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}
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/* create codec instances */
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hda_codec_probe_bus(sdev);
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hda_codec_i915_put(sdev);
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/*
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* we are done probing so decrement link counts
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*/
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list_for_each_entry(hlink, &bus->hlink_list, list)
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snd_hdac_ext_bus_link_put(bus, hlink);
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return 0;
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out:
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hda_codec_i915_exit(sdev);
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return ret;
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}
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#else
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static int hda_init_caps(struct snd_sof_dev *sdev)
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{
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/*
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* set CGCTL.MISCBDCGE to 0 during reset and set back to 1
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* when reset finished.
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* TODO: maybe no need for init_caps?
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*/
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hda_dsp_ctrl_misc_clock_gating(sdev, 0);
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/* clear WAKESTS */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK,
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SOF_HDA_WAKESTS_INT_MASK);
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return 0;
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}
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#endif
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static const struct sof_intel_dsp_desc
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*get_chip_info(struct snd_sof_pdata *pdata)
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{
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const struct sof_dev_desc *desc = pdata->desc;
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const struct sof_intel_dsp_desc *chip_info;
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chip_info = desc->chip_info;
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return chip_info;
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}
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int hda_dsp_probe(struct snd_sof_dev *sdev)
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{
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struct pci_dev *pci = to_pci_dev(sdev->dev);
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struct sof_intel_hda_dev *hdev;
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struct hdac_bus *bus;
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struct hdac_stream *stream;
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const struct sof_intel_dsp_desc *chip;
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int sd_offset, ret = 0;
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/*
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* detect DSP by checking class/subclass/prog-id information
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* class=04 subclass 03 prog-if 00: no DSP, legacy driver is required
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* class=04 subclass 01 prog-if 00: DSP is present
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* (and may be required e.g. for DMIC or SSP support)
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* class=04 subclass 03 prog-if 80: either of DSP or legacy mode works
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*/
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if (pci->class == 0x040300) {
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dev_err(sdev->dev, "error: the DSP is not enabled on this platform, aborting probe\n");
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return -ENODEV;
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} else if (pci->class != 0x040100 && pci->class != 0x040380) {
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dev_err(sdev->dev, "error: unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", pci->class);
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return -ENODEV;
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}
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dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", pci->class);
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chip = get_chip_info(sdev->pdata);
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if (!chip) {
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dev_err(sdev->dev, "error: no such device supported, chip id:%x\n",
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pci->device);
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ret = -EIO;
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goto err;
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}
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hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL);
|
||||
if (!hdev)
|
||||
return -ENOMEM;
|
||||
sdev->pdata->hw_pdata = hdev;
|
||||
hdev->desc = chip;
|
||||
|
||||
hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
|
||||
PLATFORM_DEVID_NONE,
|
||||
NULL, 0);
|
||||
if (IS_ERR(hdev->dmic_dev)) {
|
||||
dev_err(sdev->dev, "error: failed to create DMIC device\n");
|
||||
return PTR_ERR(hdev->dmic_dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* use position update IPC if either it is forced
|
||||
* or we don't have other choice
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
|
||||
hdev->no_ipc_position = 0;
|
||||
#else
|
||||
hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0;
|
||||
#endif
|
||||
|
||||
/* set up HDA base */
|
||||
bus = sof_to_bus(sdev);
|
||||
ret = hda_init(sdev);
|
||||
if (ret < 0)
|
||||
goto hdac_bus_unmap;
|
||||
|
||||
/* DSP base */
|
||||
sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
|
||||
if (!sdev->bar[HDA_DSP_BAR]) {
|
||||
dev_err(sdev->dev, "error: ioremap error\n");
|
||||
ret = -ENXIO;
|
||||
goto hdac_bus_unmap;
|
||||
}
|
||||
|
||||
sdev->mmio_bar = HDA_DSP_BAR;
|
||||
sdev->mailbox_bar = HDA_DSP_BAR;
|
||||
|
||||
/* allow 64bit DMA address if supported by H/W */
|
||||
if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
|
||||
dev_dbg(sdev->dev, "DMA mask is 64 bit\n");
|
||||
dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
|
||||
} else {
|
||||
dev_dbg(sdev->dev, "DMA mask is 32 bit\n");
|
||||
dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
|
||||
dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
|
||||
}
|
||||
|
||||
/* init streams */
|
||||
ret = hda_dsp_stream_init(sdev);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: failed to init streams\n");
|
||||
/*
|
||||
* not all errors are due to memory issues, but trying
|
||||
* to free everything does not harm
|
||||
*/
|
||||
goto free_streams;
|
||||
}
|
||||
|
||||
/*
|
||||
* register our IRQ
|
||||
* let's try to enable msi firstly
|
||||
* if it fails, use legacy interrupt mode
|
||||
* TODO: support interrupt mode selection with kernel parameter
|
||||
* support msi multiple vectors
|
||||
*/
|
||||
ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
|
||||
if (ret < 0) {
|
||||
dev_info(sdev->dev, "use legacy interrupt mode\n");
|
||||
/*
|
||||
* in IO-APIC mode, hda->irq and ipc_irq are using the same
|
||||
* irq number of pci->irq
|
||||
*/
|
||||
hdev->irq = pci->irq;
|
||||
sdev->ipc_irq = pci->irq;
|
||||
sdev->msi_enabled = 0;
|
||||
} else {
|
||||
dev_info(sdev->dev, "use msi interrupt mode\n");
|
||||
hdev->irq = pci_irq_vector(pci, 0);
|
||||
/* ipc irq number is the same of hda irq */
|
||||
sdev->ipc_irq = hdev->irq;
|
||||
sdev->msi_enabled = 1;
|
||||
}
|
||||
|
||||
dev_dbg(sdev->dev, "using HDA IRQ %d\n", hdev->irq);
|
||||
ret = request_threaded_irq(hdev->irq, hda_dsp_stream_interrupt,
|
||||
hda_dsp_stream_threaded_handler,
|
||||
IRQF_SHARED, "AudioHDA", bus);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
|
||||
hdev->irq);
|
||||
goto free_irq_vector;
|
||||
}
|
||||
|
||||
dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
|
||||
ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
|
||||
sof_ops(sdev)->irq_thread, IRQF_SHARED,
|
||||
"AudioDSP", sdev);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
|
||||
sdev->ipc_irq);
|
||||
goto free_hda_irq;
|
||||
}
|
||||
|
||||
pci_set_master(pci);
|
||||
synchronize_irq(pci->irq);
|
||||
|
||||
/*
|
||||
* clear TCSEL to clear playback on some HD Audio
|
||||
* codecs. PCI TCSEL is defined in the Intel manuals.
|
||||
*/
|
||||
snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
|
||||
|
||||
/* init HDA capabilities */
|
||||
ret = hda_init_caps(sdev);
|
||||
if (ret < 0)
|
||||
goto free_ipc_irq;
|
||||
|
||||
/* reset HDA controller */
|
||||
ret = hda_dsp_ctrl_link_reset(sdev, true);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: failed to reset HDA controller\n");
|
||||
goto free_ipc_irq;
|
||||
}
|
||||
|
||||
/* exit HDA controller reset */
|
||||
ret = hda_dsp_ctrl_link_reset(sdev, false);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
|
||||
goto free_ipc_irq;
|
||||
}
|
||||
|
||||
/* clear stream status */
|
||||
list_for_each_entry(stream, &bus->stream_list, list) {
|
||||
sd_offset = SOF_STREAM_SD_OFFSET(stream);
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
|
||||
sd_offset +
|
||||
SOF_HDA_ADSP_REG_CL_SD_STS,
|
||||
SOF_HDA_CL_DMA_SD_INT_MASK,
|
||||
SOF_HDA_CL_DMA_SD_INT_MASK);
|
||||
}
|
||||
|
||||
/* clear WAKESTS */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
|
||||
SOF_HDA_WAKESTS_INT_MASK,
|
||||
SOF_HDA_WAKESTS_INT_MASK);
|
||||
|
||||
/* clear interrupt status register */
|
||||
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
|
||||
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
|
||||
|
||||
/* enable CIE and GIE interrupts */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
|
||||
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
|
||||
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
|
||||
|
||||
/* re-enable CGCTL.MISCBDCGE after reset */
|
||||
hda_dsp_ctrl_misc_clock_gating(sdev, true);
|
||||
|
||||
device_disable_async_suspend(&pci->dev);
|
||||
|
||||
/* enable DSP features */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
|
||||
SOF_HDA_PPCTL_GPROCEN, SOF_HDA_PPCTL_GPROCEN);
|
||||
|
||||
/* enable DSP IRQ */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
|
||||
SOF_HDA_PPCTL_PIE, SOF_HDA_PPCTL_PIE);
|
||||
|
||||
/* initialize waitq for code loading */
|
||||
init_waitqueue_head(&sdev->waitq);
|
||||
|
||||
/* set default mailbox offset for FW ready message */
|
||||
sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
|
||||
|
||||
return 0;
|
||||
|
||||
free_ipc_irq:
|
||||
free_irq(sdev->ipc_irq, sdev);
|
||||
free_hda_irq:
|
||||
free_irq(hdev->irq, bus);
|
||||
free_irq_vector:
|
||||
if (sdev->msi_enabled)
|
||||
pci_free_irq_vectors(pci);
|
||||
free_streams:
|
||||
hda_dsp_stream_free(sdev);
|
||||
/* dsp_unmap: not currently used */
|
||||
iounmap(sdev->bar[HDA_DSP_BAR]);
|
||||
hdac_bus_unmap:
|
||||
iounmap(bus->remap_addr);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int hda_dsp_remove(struct snd_sof_dev *sdev)
|
||||
{
|
||||
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
|
||||
struct hdac_bus *bus = sof_to_bus(sdev);
|
||||
struct pci_dev *pci = to_pci_dev(sdev->dev);
|
||||
const struct sof_intel_dsp_desc *chip = hda->desc;
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
/* codec removal, invoke bus_device_remove */
|
||||
snd_hdac_ext_bus_device_remove(bus);
|
||||
#endif
|
||||
|
||||
if (!IS_ERR_OR_NULL(hda->dmic_dev))
|
||||
platform_device_unregister(hda->dmic_dev);
|
||||
|
||||
/* disable DSP IRQ */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
|
||||
SOF_HDA_PPCTL_PIE, 0);
|
||||
|
||||
/* disable CIE and GIE interrupts */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
|
||||
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
|
||||
|
||||
/* disable cores */
|
||||
if (chip)
|
||||
hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
|
||||
|
||||
/* disable DSP */
|
||||
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
|
||||
SOF_HDA_PPCTL_GPROCEN, 0);
|
||||
|
||||
free_irq(sdev->ipc_irq, sdev);
|
||||
free_irq(hda->irq, bus);
|
||||
if (sdev->msi_enabled)
|
||||
pci_free_irq_vectors(pci);
|
||||
|
||||
hda_dsp_stream_free(sdev);
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
snd_hdac_link_free_all(bus);
|
||||
#endif
|
||||
|
||||
iounmap(sdev->bar[HDA_DSP_BAR]);
|
||||
iounmap(bus->remap_addr);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
snd_hdac_ext_bus_exit(bus);
|
||||
#endif
|
||||
hda_codec_i915_exit(sdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
|
@ -0,0 +1,560 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* Copyright(c) 2017 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __SOF_INTEL_HDA_H
|
||||
#define __SOF_INTEL_HDA_H
|
||||
|
||||
#include <sound/hda_codec.h>
|
||||
#include <sound/hdaudio_ext.h>
|
||||
#include "shim.h"
|
||||
|
||||
/* PCI registers */
|
||||
#define PCI_TCSEL 0x44
|
||||
#define PCI_PGCTL PCI_TCSEL
|
||||
#define PCI_CGCTL 0x48
|
||||
|
||||
/* PCI_PGCTL bits */
|
||||
#define PCI_PGCTL_ADSPPGD BIT(2)
|
||||
#define PCI_PGCTL_LSRMD_MASK BIT(4)
|
||||
|
||||
/* PCI_CGCTL bits */
|
||||
#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
|
||||
#define PCI_CGCTL_ADSPDCGE BIT(1)
|
||||
|
||||
/* Legacy HDA registers and bits used - widths are variable */
|
||||
#define SOF_HDA_GCAP 0x0
|
||||
#define SOF_HDA_GCTL 0x8
|
||||
/* accept unsol. response enable */
|
||||
#define SOF_HDA_GCTL_UNSOL BIT(8)
|
||||
#define SOF_HDA_LLCH 0x14
|
||||
#define SOF_HDA_INTCTL 0x20
|
||||
#define SOF_HDA_INTSTS 0x24
|
||||
#define SOF_HDA_WAKESTS 0x0E
|
||||
#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
|
||||
#define SOF_HDA_RIRBSTS 0x5d
|
||||
#define SOF_HDA_VS_EM2_L1SEN BIT(13)
|
||||
|
||||
/* SOF_HDA_GCTL register bist */
|
||||
#define SOF_HDA_GCTL_RESET BIT(0)
|
||||
|
||||
/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
|
||||
#define SOF_HDA_INT_GLOBAL_EN BIT(31)
|
||||
#define SOF_HDA_INT_CTRL_EN BIT(30)
|
||||
#define SOF_HDA_INT_ALL_STREAM 0xff
|
||||
|
||||
#define SOF_HDA_MAX_CAPS 10
|
||||
#define SOF_HDA_CAP_ID_OFF 16
|
||||
#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
|
||||
SOF_HDA_CAP_ID_OFF)
|
||||
#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
|
||||
|
||||
#define SOF_HDA_GTS_CAP_ID 0x1
|
||||
#define SOF_HDA_ML_CAP_ID 0x2
|
||||
|
||||
#define SOF_HDA_PP_CAP_ID 0x3
|
||||
#define SOF_HDA_REG_PP_PPCH 0x10
|
||||
#define SOF_HDA_REG_PP_PPCTL 0x04
|
||||
#define SOF_HDA_PPCTL_PIE BIT(31)
|
||||
#define SOF_HDA_PPCTL_GPROCEN BIT(30)
|
||||
|
||||
/* DPIB entry size: 8 Bytes = 2 DWords */
|
||||
#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
|
||||
|
||||
#define SOF_HDA_SPIB_CAP_ID 0x4
|
||||
#define SOF_HDA_DRSM_CAP_ID 0x5
|
||||
|
||||
#define SOF_HDA_SPIB_BASE 0x08
|
||||
#define SOF_HDA_SPIB_INTERVAL 0x08
|
||||
#define SOF_HDA_SPIB_SPIB 0x00
|
||||
#define SOF_HDA_SPIB_MAXFIFO 0x04
|
||||
|
||||
#define SOF_HDA_PPHC_BASE 0x10
|
||||
#define SOF_HDA_PPHC_INTERVAL 0x10
|
||||
|
||||
#define SOF_HDA_PPLC_BASE 0x10
|
||||
#define SOF_HDA_PPLC_MULTI 0x10
|
||||
#define SOF_HDA_PPLC_INTERVAL 0x10
|
||||
|
||||
#define SOF_HDA_DRSM_BASE 0x08
|
||||
#define SOF_HDA_DRSM_INTERVAL 0x08
|
||||
|
||||
/* Descriptor error interrupt */
|
||||
#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
|
||||
|
||||
/* FIFO error interrupt */
|
||||
#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
|
||||
|
||||
/* Buffer completion interrupt */
|
||||
#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
|
||||
|
||||
#define SOF_HDA_CL_DMA_SD_INT_MASK \
|
||||
(SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
|
||||
SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
|
||||
SOF_HDA_CL_DMA_SD_INT_COMPLETE)
|
||||
#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
|
||||
|
||||
/* Intel HD Audio Code Loader DMA Registers */
|
||||
#define SOF_HDA_ADSP_LOADER_BASE 0x80
|
||||
#define SOF_HDA_ADSP_DPLBASE 0x70
|
||||
#define SOF_HDA_ADSP_DPUBASE 0x74
|
||||
#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
|
||||
|
||||
/* Stream Registers */
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
|
||||
#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
|
||||
#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
|
||||
|
||||
/* CL: Software Position Based FIFO Capability Registers */
|
||||
#define SOF_DSP_REG_CL_SPBFIFO \
|
||||
(SOF_HDA_ADSP_LOADER_BASE + 0x20)
|
||||
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
|
||||
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
|
||||
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
|
||||
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
|
||||
|
||||
/* Stream Number */
|
||||
#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
|
||||
#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
|
||||
GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
|
||||
SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
|
||||
|
||||
#define HDA_DSP_HDA_BAR 0
|
||||
#define HDA_DSP_PP_BAR 1
|
||||
#define HDA_DSP_SPIB_BAR 2
|
||||
#define HDA_DSP_DRSM_BAR 3
|
||||
#define HDA_DSP_BAR 4
|
||||
|
||||
#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
|
||||
|
||||
#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
|
||||
|
||||
#define HDA_DSP_PANIC_OFFSET(x) \
|
||||
(((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
|
||||
|
||||
/* SRAM window 0 FW "registers" */
|
||||
#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
|
||||
#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
|
||||
/* FW and ROM share offset 4 */
|
||||
#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
|
||||
#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
|
||||
#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
|
||||
|
||||
#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
|
||||
|
||||
#define HDA_DSP_STREAM_RESET_TIMEOUT 300
|
||||
#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
|
||||
|
||||
#define HDA_DSP_SPIB_ENABLE 1
|
||||
#define HDA_DSP_SPIB_DISABLE 0
|
||||
|
||||
#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
|
||||
|
||||
#define HDA_DSP_STACK_DUMP_SIZE 32
|
||||
|
||||
/* ROM status/error values */
|
||||
#define HDA_DSP_ROM_STS_MASK 0xf
|
||||
#define HDA_DSP_ROM_INIT 0x1
|
||||
#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
|
||||
#define HDA_DSP_ROM_FW_FW_LOADED 0x4
|
||||
#define HDA_DSP_ROM_FW_ENTERED 0x5
|
||||
#define HDA_DSP_ROM_RFW_START 0xf
|
||||
#define HDA_DSP_ROM_CSE_ERROR 40
|
||||
#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
|
||||
#define HDA_DSP_ROM_IMR_TO_SMALL 42
|
||||
#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
|
||||
#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
|
||||
#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
|
||||
#define HDA_DSP_ROM_L2_CACHE_ERROR 46
|
||||
#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
|
||||
#define HDA_DSP_ROM_API_PTR_INVALID 50
|
||||
#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
|
||||
#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
|
||||
#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
|
||||
#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
|
||||
#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
|
||||
#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
|
||||
#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
|
||||
#define HDA_DSP_IPC_PURGE_FW 0x01004000
|
||||
|
||||
/* various timeout values */
|
||||
#define HDA_DSP_PU_TIMEOUT 50
|
||||
#define HDA_DSP_PD_TIMEOUT 50
|
||||
#define HDA_DSP_RESET_TIMEOUT_US 50000
|
||||
#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
|
||||
#define HDA_DSP_INIT_TIMEOUT_US 500000
|
||||
#define HDA_DSP_CTRL_RESET_TIMEOUT 100
|
||||
#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
|
||||
#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
|
||||
|
||||
#define HDA_DSP_ADSPIC_IPC 1
|
||||
#define HDA_DSP_ADSPIS_IPC 1
|
||||
|
||||
/* Intel HD Audio General DSP Registers */
|
||||
#define HDA_DSP_GEN_BASE 0x0
|
||||
#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
|
||||
#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
|
||||
#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
|
||||
#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
|
||||
#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
|
||||
|
||||
/* Intel HD Audio Inter-Processor Communication Registers */
|
||||
#define HDA_DSP_IPC_BASE 0x40
|
||||
#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
|
||||
#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
|
||||
#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
|
||||
#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
|
||||
#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
|
||||
|
||||
/* HIPCI */
|
||||
#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
|
||||
#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCIE */
|
||||
#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
|
||||
#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
|
||||
|
||||
/* HIPCCTL */
|
||||
#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
|
||||
#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
|
||||
|
||||
/* HIPCT */
|
||||
#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
|
||||
#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCTE */
|
||||
#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
|
||||
|
||||
#define HDA_DSP_ADSPIC_CL_DMA 0x2
|
||||
#define HDA_DSP_ADSPIS_CL_DMA 0x2
|
||||
|
||||
/* Delay before scheduling D0i3 entry */
|
||||
#define BXT_D0I3_DELAY 5000
|
||||
|
||||
#define FW_CL_STREAM_NUMBER 0x1
|
||||
|
||||
/* ADSPCS - Audio DSP Control & Status */
|
||||
|
||||
/*
|
||||
* Core Reset - asserted high
|
||||
* CRST Mask for a given core mask pattern, cm
|
||||
*/
|
||||
#define HDA_DSP_ADSPCS_CRST_SHIFT 0
|
||||
#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
|
||||
|
||||
/*
|
||||
* Core run/stall - when set to '1' core is stalled
|
||||
* CSTALL Mask for a given core mask pattern, cm
|
||||
*/
|
||||
#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
|
||||
#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
|
||||
|
||||
/*
|
||||
* Set Power Active - when set to '1' turn cores on
|
||||
* SPA Mask for a given core mask pattern, cm
|
||||
*/
|
||||
#define HDA_DSP_ADSPCS_SPA_SHIFT 16
|
||||
#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
|
||||
|
||||
/*
|
||||
* Current Power Active - power status of cores, set by hardware
|
||||
* CPA Mask for a given core mask pattern, cm
|
||||
*/
|
||||
#define HDA_DSP_ADSPCS_CPA_SHIFT 24
|
||||
#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
|
||||
|
||||
/* Mask for a given core index, c = 0.. number of supported cores - 1 */
|
||||
#define HDA_DSP_CORE_MASK(c) BIT(c)
|
||||
|
||||
/*
|
||||
* Mask for a given number of cores
|
||||
* nc = number of supported cores
|
||||
*/
|
||||
#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
|
||||
|
||||
/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
|
||||
#define CNL_DSP_IPC_BASE 0xc0
|
||||
#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
|
||||
#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
|
||||
#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
|
||||
#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
|
||||
#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
|
||||
#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
|
||||
|
||||
/* HIPCI */
|
||||
#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
|
||||
#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCIE */
|
||||
#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
|
||||
#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCCTL */
|
||||
#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
|
||||
#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
|
||||
|
||||
/* HIPCT */
|
||||
#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
|
||||
#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCTDA */
|
||||
#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
|
||||
#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* HIPCTDD */
|
||||
#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
|
||||
|
||||
/* BDL */
|
||||
#define HDA_DSP_BDL_SIZE 4096
|
||||
#define HDA_DSP_MAX_BDL_ENTRIES \
|
||||
(HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
|
||||
|
||||
/* Number of DAIs */
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
#define SOF_SKL_NUM_DAIS 14
|
||||
#else
|
||||
#define SOF_SKL_NUM_DAIS 8
|
||||
#endif
|
||||
|
||||
/* Intel HD Audio SRAM Window 0*/
|
||||
#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
|
||||
|
||||
/* Firmware status window */
|
||||
#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
|
||||
#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
|
||||
|
||||
#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
|
||||
|
||||
struct sof_intel_dsp_bdl {
|
||||
__le32 addr_l;
|
||||
__le32 addr_h;
|
||||
__le32 size;
|
||||
__le32 ioc;
|
||||
} __attribute((packed));
|
||||
|
||||
#define SOF_HDA_PLAYBACK_STREAMS 16
|
||||
#define SOF_HDA_CAPTURE_STREAMS 16
|
||||
#define SOF_HDA_PLAYBACK 0
|
||||
#define SOF_HDA_CAPTURE 1
|
||||
|
||||
/* represents DSP HDA controller frontend - i.e. host facing control */
|
||||
struct sof_intel_hda_dev {
|
||||
|
||||
struct hda_bus hbus;
|
||||
|
||||
/* hw config */
|
||||
const struct sof_intel_dsp_desc *desc;
|
||||
|
||||
/* trace */
|
||||
struct hdac_ext_stream *dtrace_stream;
|
||||
|
||||
/* if position update IPC needed */
|
||||
u32 no_ipc_position;
|
||||
|
||||
int irq;
|
||||
|
||||
/* DMIC device */
|
||||
struct platform_device *dmic_dev;
|
||||
};
|
||||
|
||||
static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
|
||||
{
|
||||
struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
|
||||
|
||||
return &hda->hbus.core;
|
||||
}
|
||||
|
||||
static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
|
||||
{
|
||||
struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
|
||||
|
||||
return &hda->hbus;
|
||||
}
|
||||
|
||||
struct sof_intel_hda_stream {
|
||||
struct hdac_ext_stream hda_stream;
|
||||
struct sof_intel_stream stream;
|
||||
};
|
||||
|
||||
#define bus_to_sof_hda(bus) \
|
||||
container_of(bus, struct sof_intel_hda_dev, hbus.core)
|
||||
|
||||
#define SOF_STREAM_SD_OFFSET(s) \
|
||||
(SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
|
||||
+ SOF_HDA_ADSP_LOADER_BASE)
|
||||
|
||||
/*
|
||||
* DSP Core services.
|
||||
*/
|
||||
int hda_dsp_probe(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_remove(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
|
||||
unsigned int core_mask);
|
||||
int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
|
||||
unsigned int core_mask);
|
||||
int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
|
||||
int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
|
||||
int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
|
||||
int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
|
||||
int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
|
||||
bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
|
||||
unsigned int core_mask);
|
||||
int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
|
||||
unsigned int core_mask);
|
||||
void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
|
||||
void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
|
||||
|
||||
int hda_dsp_suspend(struct snd_sof_dev *sdev, int state);
|
||||
int hda_dsp_resume(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state);
|
||||
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
|
||||
void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
|
||||
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
|
||||
|
||||
/*
|
||||
* DSP PCM Operations.
|
||||
*/
|
||||
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream);
|
||||
int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream);
|
||||
int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct sof_ipc_stream_params *ipc_params);
|
||||
int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream, int cmd);
|
||||
snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream);
|
||||
|
||||
/*
|
||||
* DSP Stream Operations.
|
||||
*/
|
||||
|
||||
int hda_dsp_stream_init(struct snd_sof_dev *sdev);
|
||||
void hda_dsp_stream_free(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
|
||||
struct hdac_ext_stream *stream,
|
||||
struct snd_dma_buffer *dmab,
|
||||
struct snd_pcm_hw_params *params);
|
||||
int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
|
||||
struct hdac_ext_stream *stream, int cmd);
|
||||
irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
|
||||
irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
|
||||
int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
|
||||
struct snd_dma_buffer *dmab,
|
||||
struct hdac_stream *stream);
|
||||
|
||||
struct hdac_ext_stream *
|
||||
hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
|
||||
int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
|
||||
int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
|
||||
struct hdac_ext_stream *stream,
|
||||
int enable, u32 size);
|
||||
|
||||
void hda_ipc_msg_data(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream,
|
||||
void *p, size_t sz);
|
||||
int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream,
|
||||
const struct sof_ipc_pcm_params_reply *reply);
|
||||
|
||||
/*
|
||||
* DSP IPC Operations.
|
||||
*/
|
||||
int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
|
||||
struct snd_sof_ipc_msg *msg);
|
||||
void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
|
||||
irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
|
||||
irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
|
||||
int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
|
||||
|
||||
/*
|
||||
* DSP Code loader.
|
||||
*/
|
||||
int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
|
||||
|
||||
/* pre and post fw run ops */
|
||||
int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
|
||||
|
||||
/*
|
||||
* HDA Controller Operations.
|
||||
*/
|
||||
int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
|
||||
void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
|
||||
void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
|
||||
int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
|
||||
void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
|
||||
int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
|
||||
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
|
||||
|
||||
/*
|
||||
* HDA bus operations.
|
||||
*/
|
||||
void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev,
|
||||
const struct hdac_ext_bus_ops *ext_ops);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
|
||||
/*
|
||||
* HDA Codec operations.
|
||||
*/
|
||||
int hda_codec_probe_bus(struct snd_sof_dev *sdev);
|
||||
|
||||
#endif /* CONFIG_SND_SOC_SOF_HDA */
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
|
||||
|
||||
void hda_codec_i915_get(struct snd_sof_dev *sdev);
|
||||
void hda_codec_i915_put(struct snd_sof_dev *sdev);
|
||||
int hda_codec_i915_init(struct snd_sof_dev *sdev);
|
||||
int hda_codec_i915_exit(struct snd_sof_dev *sdev);
|
||||
|
||||
#else
|
||||
|
||||
static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { }
|
||||
static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { }
|
||||
static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
|
||||
static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
|
||||
|
||||
#endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
|
||||
|
||||
/*
|
||||
* Trace Control.
|
||||
*/
|
||||
int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
|
||||
int hda_dsp_trace_release(struct snd_sof_dev *sdev);
|
||||
int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
|
||||
|
||||
/* common dai driver */
|
||||
extern struct snd_soc_dai_driver skl_dai[];
|
||||
|
||||
/*
|
||||
* Platform Specific HW abstraction Ops.
|
||||
*/
|
||||
extern const struct snd_sof_dsp_ops sof_apl_ops;
|
||||
extern const struct snd_sof_dsp_ops sof_cnl_ops;
|
||||
extern const struct snd_sof_dsp_ops sof_skl_ops;
|
||||
|
||||
extern const struct sof_intel_dsp_desc apl_chip_info;
|
||||
extern const struct sof_intel_dsp_desc cnl_chip_info;
|
||||
extern const struct sof_intel_dsp_desc skl_chip_info;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue