iio: adc: ti-ads7950: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: 902c4b2446
("iio: adc: New driver for TI ADS7950 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: David Lechner <david@lechnology.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-37-jic23@kernel.org
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@ -102,11 +102,11 @@ struct ti_ads7950_state {
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unsigned int gpio_cmd_settings_bitmask;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* DMA (thus cache coherency maintenance) may require the
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* transfer buffers to live in their own cache lines.
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*/
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u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
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____cacheline_aligned;
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__aligned(IIO_DMA_MINALIGN);
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u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
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u16 single_tx;
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u16 single_rx;
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