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perf vendor events intel: Update CLX uncore to v1.14 

JSON uncore events are generated for CascadeLake Server for v1.14 with
events from:

https://download.01.org/perfmon/CLX/

New event names are added, that match the original JSON names,
due to an update to:

https://github.com/intel/event-converter-for-linux-perf/

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-4-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-04-13 14:04:53 -07:00 committed by Arnaldo Carvalho de Melo
parent 12c6385eeb
commit dd498d0804
2 changed files with 153 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
View File

@ -9,6 +9,16 @@
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "read requests to memory controller",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
@ -19,6 +29,16 @@
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "write requests to memory controller",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0xC",
"Unit": "iMC"
},
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
@ -89,6 +109,15 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec)",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
"Counter": "0,1,2,3",
@ -98,6 +127,15 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec)",
"Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "UNC_M_PMM_WPQ_INSERTS",
"PerPkg": "1",
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
"Counter": "0,1,2,3",
@ -109,6 +147,17 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec)",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M_PMM_RPQ_INSERTS",
"MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
"MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL",
"PerPkg": "1",
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
"Counter": "0,1,2,3",
@ -130,6 +179,18 @@
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory read latency (ns)",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
"MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
"MetricName": "UNC_M_PMM_READ_LATENCY",
"PerPkg": "1",
"ScaleUnit": "6000000000ns",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Page Activate commands sent due to a write request",
"Counter": "0,1,2,3",

92
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
View File

@ -16,6 +16,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"Filter": "config1=0x40e33",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@ -26,6 +36,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO reads",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"Filter": "config1=0x40040e33",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@ -36,6 +56,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "MMIO writes",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"Filter": "config1=0x40041e33",
"PerPkg": "1",
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@ -47,6 +77,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (full cache line)",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"Filter": "config1=0x41833",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@ -58,6 +99,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "Streaming stores (partial cache line)",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"Filter": "config1=0x41a33",
"PerPkg": "1",
"ScaleUnit": "64Bytes",
"UMask": "0x21",
"Unit": "CHA"
},
{
"BriefDescription": "read requests from home agent",
"Counter": "0,1,2,3",
@ -113,6 +165,16 @@
"UMask": "0xf",
"Unit": "UPI LL"
},
{
"BriefDescription": "UPI interconnect send bandwidth for payload",
"Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
"ScaleUnit": "7.11E-06Bytes",
"UMask": "0xf",
"Unit": "UPI LL"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
"Counter": "0,1",
@ -176,6 +238,21 @@
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth writing at IIO",
"Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"Filter": "ch_mask=0x1f",
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"MetricName": "LLC_MISSES.PCIE_WRITE",
"PerPkg": "1",
"PortMask": "0x01",
"ScaleUnit": "4Bytes",
"UMask": "0x01",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
"Counter": "0,1",
@ -239,6 +316,21 @@
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "PCI Express bandwidth reading at IIO",
"Counter": "0,1",
"EventCode": "0x83",
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"Filter": "ch_mask=0x1f",
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"MetricName": "LLC_MISSES.PCIE_READ",
"PerPkg": "1",
"PortMask": "0x01",
"ScaleUnit": "4Bytes",
"UMask": "0x04",
"Unit": "IIO"
},
{
"BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
"Counter": "0,1,2,3",