From dd2ab5c8b81e23847db5477033fc14f9b8783db2 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:52 +0200 Subject: [PATCH] arm64: dts: ls2088ardb: add PHY nodes for the AQR405 PHYs Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index a4b0dcab6e8e..854f604049ca 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -43,6 +43,26 @@ phy-connection-type = "10gbase-r"; }; +&dpmac5 { + phy-handle = <&mdio2_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac6 { + phy-handle = <&mdio2_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac7 { + phy-handle = <&mdio2_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac8 { + phy-handle = <&mdio2_phy4>; + phy-connection-type = "10gbase-r"; +}; + &emdio1 { status = "okay"; @@ -66,3 +86,27 @@ reg = <0x13>; }; }; + +&emdio2 { + status = "okay"; + + mdio2_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + mdio2_phy2: ethernet-phy@1 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + mdio2_phy3: ethernet-phy@2 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + mdio2_phy4: ethernet-phy@3 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +};