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Merge branch 'for-linus/i2c' of git://git.fluff.org/bjdooks/linux 

* 'for-linus/i2c' of git://git.fluff.org/bjdooks/linux:
  i2c: Add support for Xilinx XPS IIC Bus Interface
  i2c: omap: Add support for 16-bit registers
  i2c-pnx: fix setting start/stop condition
  powerpc: doc/dts-bindings: update doc of FSL I2C bindings
  i2c-mpc: add support for the MPC512x processors from Freescale
  i2c-mpc: rename "setclock" initialization functions to "setup"
  i2c-mpc: use __devinit[data] for initialization functions and data
  i2c/imx: don't add probe function to the driver struct
  i2c: Add support for Ux500/Nomadik I2C controller
This commit is contained in:
Linus Torvalds 2010-03-07 15:56:25 -08:00
parent 6dc3eb5c1f 3f4ae86052
commit dd04265b02
9 changed files with 1973 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/powerpc/dts-bindings/fsl/i2c.txt
View File

@ -2,15 +2,14 @@
Required properties : Required properties :
- device_type : Should be "i2c"
- reg : Offset and length of the register set for the device - reg : Offset and length of the register set for the device
- compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
mpc5200 or mpc5200b. For the mpc5121, an additional node
"fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
Recommended properties : Recommended properties :
- compatible : compatibility list with 2 entries, the first should
be "fsl,CHIP-i2c" where CHIP is the name of a compatible processor,
e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
should be "fsl-i2c".
- interrupts : <a b> where a is the interrupt number and b is a - interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on information for the interrupt. This should be encoded based on
@ -24,25 +23,40 @@ Recommended properties :
Examples : Examples :
/* MPC5121 based board */
i2c@1740 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
i2ccontrol@1760 {
compatible = "fsl,mpc5121-i2c-ctrl";
reg = <0x1760 0x8>;
};
/* MPC5200B based board */
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <2 15 0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>; interrupt-parent = <&mpc5200_pic>;
fsl,preserve-clocking; fsl,preserve-clocking;
}; };
/* MPC8544 base board */
i2c@3100 { i2c@3100 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cell-index = <1>;
compatible = "fsl,mpc8544-i2c", "fsl-i2c"; compatible = "fsl,mpc8544-i2c", "fsl-i2c";
reg = <0x3100 0x100>; reg = <0x3100 0x100>;
interrupts = <43 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };

24
drivers/i2c/busses/Kconfig
View File

@ -421,13 +421,12 @@ config I2C_IXP2000
instead. instead.
config I2C_MPC config I2C_MPC
tristate "MPC107/824x/85xx/52xx/86xx" tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
depends on PPC32 depends on PPC32
help help
If you say yes to this option, support will be included for the If you say yes to this option, support will be included for the
built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
MPC85xx/MPC8641 family processors. The driver may also work on 52xx MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors.
family processors, though interrupts are known not to work.
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called i2c-mpc. will be called i2c-mpc.
@ -442,6 +441,13 @@ config I2C_MV64XXX
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called i2c-mv64xxx. will be called i2c-mv64xxx.
config I2C_NOMADIK
tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
depends on PLAT_NOMADIK
help
If you say yes to this option, support will be included for the
I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.
config I2C_OCORES config I2C_OCORES
tristate "OpenCores I2C Controller" tristate "OpenCores I2C Controller"
depends on EXPERIMENTAL depends on EXPERIMENTAL
@ -577,6 +583,16 @@ config I2C_OCTEON
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called i2c-octeon. will be called i2c-octeon.
config I2C_XILINX
tristate "Xilinx I2C Controller"
depends on EXPERIMENTAL && HAS_IOMEM
help
If you say yes to this option, support will be included for the
Xilinx I2C controller.
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
comment "External I2C/SMBus adapter drivers" comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT config I2C_PARPORT

2
drivers/i2c/busses/Makefile
View File

@ -42,6 +42,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
obj-$(CONFIG_I2C_MPC) += i2c-mpc.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
@ -55,6 +56,7 @@ obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
obj-$(CONFIG_I2C_STU300) += i2c-stu300.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
# External I2C/SMBus adapter drivers # External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o

1
drivers/i2c/busses/i2c-imx.c
View File

@ -627,7 +627,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
} }
static struct platform_driver i2c_imx_driver = { static struct platform_driver i2c_imx_driver = {
.probe = i2c_imx_probe,
.remove = __exit_p(i2c_imx_remove), .remove = __exit_p(i2c_imx_remove),
.driver = { .driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,

194
drivers/i2c/busses/i2c-mpc.c
View File

@ -31,6 +31,9 @@
#define DRV_NAME "mpc-i2c" #define DRV_NAME "mpc-i2c"
#define MPC_I2C_CLOCK_LEGACY 0
#define MPC_I2C_CLOCK_PRESERVE (~0U)
#define MPC_I2C_FDR 0x04 #define MPC_I2C_FDR 0x04
#define MPC_I2C_CR 0x08 #define MPC_I2C_CR 0x08
#define MPC_I2C_SR 0x0c #define MPC_I2C_SR 0x0c
@ -66,10 +69,9 @@ struct mpc_i2c_divider {
u16 fdr; /* including dfsrr */ u16 fdr; /* including dfsrr */
}; };
struct mpc_i2c_match_data { struct mpc_i2c_data {
void (*setclock)(struct device_node *node, void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
struct mpc_i2c *i2c, u32 clock, u32 prescaler);
u32 clock, u32 prescaler);
u32 prescaler; u32 prescaler;
}; };
@ -164,8 +166,8 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
return 0; return 0;
} }
#ifdef CONFIG_PPC_MPC52xx #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@ -186,14 +188,15 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
}; };
int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
int prescaler)
{ {
const struct mpc_i2c_divider *div = NULL; const struct mpc_i2c_divider *div = NULL;
unsigned int pvr = mfspr(SPRN_PVR); unsigned int pvr = mfspr(SPRN_PVR);
u32 divider; u32 divider;
int i; int i;
if (!clock) if (clock == MPC_I2C_CLOCK_LEGACY)
return -EINVAL; return -EINVAL;
/* Determine divider value */ /* Determine divider value */
@ -215,12 +218,18 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
return div ? (int)div->fdr : -EINVAL; return div ? (int)div->fdr : -EINVAL;
} }
static void mpc_i2c_setclock_52xx(struct device_node *node, static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
int ret, fdr; int ret, fdr;
if (clock == MPC_I2C_CLOCK_PRESERVE) {
dev_dbg(i2c->dev, "using fdr %d\n",
readb(i2c->base + MPC_I2C_FDR));
return;
}
ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
@ -229,16 +238,52 @@ static void mpc_i2c_setclock_52xx(struct device_node *node,
if (ret >= 0) if (ret >= 0)
dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
} }
#else /* !CONFIG_PPC_MPC52xx */ #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
static void mpc_i2c_setclock_52xx(struct device_node *node, static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
} }
#endif /* CONFIG_PPC_MPC52xx*/ #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
#ifdef CONFIG_PPC_MPC512x
static void __devinit mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
struct device_node *node_ctrl;
void __iomem *ctrl;
const u32 *pval;
u32 idx;
/* Enable I2C interrupts for mpc5121 */
node_ctrl = of_find_compatible_node(NULL, NULL,
"fsl,mpc5121-i2c-ctrl");
if (node_ctrl) {
ctrl = of_iomap(node_ctrl, 0);
if (ctrl) {
/* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
pval = of_get_property(node, "reg", NULL);
idx = (*pval & 0xff) / 0x20;
setbits32(ctrl, 1 << (24 + idx * 2));
iounmap(ctrl);
}
of_node_put(node_ctrl);
}
/* The clock setup for the 52xx works also fine for the 512x */
mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
}
#else /* CONFIG_PPC_MPC512x */
static void __devinit mpc_i2c_setup_512x(struct device_node *node,
struct mpc_i2c *i2c,
u32 clock, u32 prescaler)
{
}
#endif /* CONFIG_PPC_MPC512x */
#ifdef CONFIG_FSL_SOC #ifdef CONFIG_FSL_SOC
static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
@ -258,7 +303,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
{49152, 0x011e}, {61440, 0x011f} {49152, 0x011e}, {61440, 0x011f}
}; };
u32 mpc_i2c_get_sec_cfg_8xxx(void) static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
{ {
struct device_node *node = NULL; struct device_node *node = NULL;
u32 __iomem *reg; u32 __iomem *reg;
@ -287,13 +332,14 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void)
return val; return val;
} }
int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
u32 prescaler)
{ {
const struct mpc_i2c_divider *div = NULL; const struct mpc_i2c_divider *div = NULL;
u32 divider; u32 divider;
int i; int i;
if (!clock) if (clock == MPC_I2C_CLOCK_LEGACY)
return -EINVAL; return -EINVAL;
/* Determine proper divider value */ /* Determine proper divider value */
@ -320,12 +366,19 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
return div ? (int)div->fdr : -EINVAL; return div ? (int)div->fdr : -EINVAL;
} }
static void mpc_i2c_setclock_8xxx(struct device_node *node, static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
int ret, fdr; int ret, fdr;
if (clock == MPC_I2C_CLOCK_PRESERVE) {
dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
readb(i2c->base + MPC_I2C_DFSRR),
readb(i2c->base + MPC_I2C_FDR));
return;
}
ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
@ -338,9 +391,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
} }
#else /* !CONFIG_FSL_SOC */ #else /* !CONFIG_FSL_SOC */
static void mpc_i2c_setclock_8xxx(struct device_node *node, static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
} }
#endif /* CONFIG_FSL_SOC */ #endif /* CONFIG_FSL_SOC */
@ -494,7 +547,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
{ {
struct mpc_i2c *i2c; struct mpc_i2c *i2c;
const u32 *prop; const u32 *prop;
u32 clock = 0; u32 clock = MPC_I2C_CLOCK_LEGACY;
int result = 0; int result = 0;
int plen; int plen;
@ -523,21 +576,21 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
} }
} }
if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) { if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
clock = MPC_I2C_CLOCK_PRESERVE;
} else {
prop = of_get_property(op->node, "clock-frequency", &plen); prop = of_get_property(op->node, "clock-frequency", &plen);
if (prop && plen == sizeof(u32)) if (prop && plen == sizeof(u32))
clock = *prop; clock = *prop;
}
if (match->data) { if (match->data) {
struct mpc_i2c_match_data *data = struct mpc_i2c_data *data = match->data;
(struct mpc_i2c_match_data *)match->data; data->setup(op->node, i2c, clock, data->prescaler);
data->setclock(op->node, i2c, clock, data->prescaler); } else {
} else { /* Backwards compatibility */
/* Backwards compatibility */ if (of_get_property(op->node, "dfsrr", NULL))
if (of_get_property(op->node, "dfsrr", NULL)) mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
mpc_i2c_setclock_8xxx(op->node, i2c,
clock, 0);
}
} }
dev_set_drvdata(&op->dev, i2c); dev_set_drvdata(&op->dev, i2c);
@ -582,47 +635,42 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
return 0; return 0;
}; };
static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
.setup = mpc_i2c_setup_512x,
};
static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
.setup = mpc_i2c_setup_52xx,
};
static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
.setup = mpc_i2c_setup_8xxx,
};
static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
.setup = mpc_i2c_setup_8xxx,
.prescaler = 2,
};
static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
.setup = mpc_i2c_setup_8xxx,
.prescaler = 3,
};
static const struct of_device_id mpc_i2c_of_match[] = { static const struct of_device_id mpc_i2c_of_match[] = {
{.compatible = "mpc5200-i2c", {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
.data = &(struct mpc_i2c_match_data) { {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
.setclock = mpc_i2c_setclock_52xx, {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
}, {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
}, {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
{.compatible = "fsl,mpc5200b-i2c", {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
.data = &(struct mpc_i2c_match_data) { {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
.setclock = mpc_i2c_setclock_52xx,
},
},
{.compatible = "fsl,mpc5200-i2c",
.data = &(struct mpc_i2c_match_data) {
.setclock = mpc_i2c_setclock_52xx,
},
},
{.compatible = "fsl,mpc8313-i2c",
.data = &(struct mpc_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
},
},
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct mpc_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
{.compatible = "fsl,mpc8544-i2c",
.data = &(struct mpc_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 3,
},
/* Backward compatibility */ /* Backward compatibility */
},
{.compatible = "fsl-i2c", }, {.compatible = "fsl-i2c", },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
/* Structure for a device driver */ /* Structure for a device driver */
static struct of_platform_driver mpc_i2c_driver = { static struct of_platform_driver mpc_i2c_driver = {
.match_table = mpc_i2c_of_match, .match_table = mpc_i2c_of_match,
@ -655,5 +703,5 @@ module_exit(fsl_i2c_exit);
MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
"MPC824x/85xx/52xx processors"); "MPC824x/83xx/85xx/86xx/512x/52xx processors");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");

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/*
* Copyright (C) 2009 ST-Ericsson
* Copyright (C) 2009 STMicroelectronics
*
* I2C master mode controller driver, used in Nomadik 8815
* and Ux500 platforms.
*
* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
* Author: Sachin Verma <sachin.verma@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <plat/i2c.h>
#define DRIVER_NAME "nmk-i2c"
/* I2C Controller register offsets */
#define I2C_CR (0x000)
#define I2C_SCR (0x004)
#define I2C_HSMCR (0x008)
#define I2C_MCR (0x00C)
#define I2C_TFR (0x010)
#define I2C_SR (0x014)
#define I2C_RFR (0x018)
#define I2C_TFTR (0x01C)
#define I2C_RFTR (0x020)
#define I2C_DMAR (0x024)
#define I2C_BRCR (0x028)
#define I2C_IMSCR (0x02C)
#define I2C_RISR (0x030)
#define I2C_MISR (0x034)
#define I2C_ICR (0x038)
/* Control registers */
#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
#define I2C_CR_OM (0x3 << 1) /* Operating mode */
#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
#define I2C_CR_SM (0x3 << 4) /* Speed mode */
#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
#define I2C_CR_FON (0x3 << 13) /* Filtering on */
#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
/* Master controller (MCR) register */
#define I2C_MCR_OP (0x1 << 0) /* Operation */
#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
#define I2C_MCR_SB (0x1 << 11) /* Extended address */
#define I2C_MCR_AM (0x3 << 12) /* Address type */
#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
/* Status register (SR) */
#define I2C_SR_OP (0x3 << 0) /* Operation */
#define I2C_SR_STATUS (0x3 << 2) /* controller status */
#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
/* Interrupt mask set/clear (IMSCR) bits */
#define I2C_IT_TXFE (0x1 << 0)
#define I2C_IT_TXFNE (0x1 << 1)
#define I2C_IT_TXFF (0x1 << 2)
#define I2C_IT_TXFOVR (0x1 << 3)
#define I2C_IT_RXFE (0x1 << 4)
#define I2C_IT_RXFNF (0x1 << 5)
#define I2C_IT_RXFF (0x1 << 6)
#define I2C_IT_RFSR (0x1 << 16)
#define I2C_IT_RFSE (0x1 << 17)
#define I2C_IT_WTSR (0x1 << 18)
#define I2C_IT_MTD (0x1 << 19)
#define I2C_IT_STD (0x1 << 20)
#define I2C_IT_MAL (0x1 << 24)
#define I2C_IT_BERR (0x1 << 25)
#define I2C_IT_MTDWS (0x1 << 28)
#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
/* some bits in ICR are reserved */
#define I2C_CLEAR_ALL_INTS 0x131f007f
/* first three msb bits are reserved */
#define IRQ_MASK(mask) (mask & 0x1fffffff)
/* maximum threshold value */
#define MAX_I2C_FIFO_THRESHOLD 15
enum i2c_status {
I2C_NOP,
I2C_ON_GOING,
I2C_OK,
I2C_ABORT
};
/* operation */
enum i2c_operation {
I2C_NO_OPERATION = 0xff,
I2C_WRITE = 0x00,
I2C_READ = 0x01
};
/* controller response timeout in ms */
#define I2C_TIMEOUT_MS 500
/**
* struct i2c_nmk_client - client specific data
* @slave_adr: 7-bit slave address
* @count: no. bytes to be transfered
* @buffer: client data buffer
* @xfer_bytes: bytes transfered till now
* @operation: current I2C operation
*/
struct i2c_nmk_client {
unsigned short slave_adr;
unsigned long count;
unsigned char *buffer;
unsigned long xfer_bytes;
enum i2c_operation operation;
};
/**
* struct nmk_i2c_dev - private data structure of the controller
* @pdev: parent platform device
* @adap: corresponding I2C adapter
* @irq: interrupt line for the controller
* @virtbase: virtual io memory area
* @clk: hardware i2c block clock
* @cfg: machine provided controller configuration
* @cli: holder of client specific data
* @stop: stop condition
* @xfer_complete: acknowledge completion for a I2C message
* @result: controller propogated result
*/
struct nmk_i2c_dev {
struct platform_device *pdev;
struct i2c_adapter adap;
int irq;
void __iomem *virtbase;
struct clk *clk;
struct nmk_i2c_controller cfg;
struct i2c_nmk_client cli;
int stop;
struct completion xfer_complete;
int result;
};
/* controller's abort causes */
static const char *abort_causes[] = {
"no ack received after address transmission",
"no ack received during data phase",
"ack received after xmission of master code",
"master lost arbitration",
"slave restarts",
"slave reset",
"overflow, maxsize is 2047 bytes",
};
static inline void i2c_set_bit(void __iomem *reg, u32 mask)
{
writel(readl(reg) | mask, reg);
}
static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
{
writel(readl(reg) & ~mask, reg);
}
/**
* flush_i2c_fifo() - This function flushes the I2C FIFO
* @dev: private data of I2C Driver
*
* This function flushes the I2C Tx and Rx FIFOs. It returns
* 0 on successful flushing of FIFO
*/
static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
{
#define LOOP_ATTEMPTS 10
int i;
unsigned long timeout;
/*
* flush the transmit and receive FIFO. The flushing
* operation takes several cycles before to be completed.
* On the completion, the I2C internal logic clears these
* bits, until then no one must access Tx, Rx FIFO and
* should poll on these bits waiting for the completion.
*/
writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
for (i = 0; i < LOOP_ATTEMPTS; i++) {
timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
while (!time_after(jiffies, timeout)) {
if ((readl(dev->virtbase + I2C_CR) &
(I2C_CR_FTX | I2C_CR_FRX)) == 0)
return 0;
}
}
dev_err(&dev->pdev->dev, "flushing operation timed out "
"giving up after %d attempts", LOOP_ATTEMPTS);
return -ETIMEDOUT;
}
/**
* disable_all_interrupts() - Disable all interrupts of this I2c Bus
* @dev: private data of I2C Driver
*/
static void disable_all_interrupts(struct nmk_i2c_dev *dev)
{
u32 mask = IRQ_MASK(0);
writel(mask, dev->virtbase + I2C_IMSCR);
}
/**
* clear_all_interrupts() - Clear all interrupts of I2C Controller
* @dev: private data of I2C Driver
*/
static void clear_all_interrupts(struct nmk_i2c_dev *dev)
{
u32 mask;
mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
writel(mask, dev->virtbase + I2C_ICR);
}
/**
* init_hw() - initialize the I2C hardware
* @dev: private data of I2C Driver
*/
static int init_hw(struct nmk_i2c_dev *dev)
{
int stat;
stat = flush_i2c_fifo(dev);
if (stat)
return stat;
/* disable the controller */
i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
disable_all_interrupts(dev);
clear_all_interrupts(dev);
dev->cli.operation = I2C_NO_OPERATION;
return 0;
}
/* enable peripheral, master mode operation */
#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
/**
* load_i2c_mcr_reg() - load the MCR register
* @dev: private data of controller
*/
static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
{
u32 mcr = 0;
/* 7-bit address transaction */
mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
/* start byte procedure not applied */
mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
/* check the operation, master read/write? */
if (dev->cli.operation == I2C_WRITE)
mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
else
mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
/* stop or repeated start? */
if (dev->stop)
mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
else
mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
return mcr;
}
/**
* setup_i2c_controller() - setup the controller
* @dev: private data of controller
*/
static void setup_i2c_controller(struct nmk_i2c_dev *dev)
{
u32 brcr1, brcr2;
u32 i2c_clk, div;
writel(0x0, dev->virtbase + I2C_CR);
writel(0x0, dev->virtbase + I2C_HSMCR);
writel(0x0, dev->virtbase + I2C_TFTR);
writel(0x0, dev->virtbase + I2C_RFTR);
writel(0x0, dev->virtbase + I2C_DMAR);
/*
* set the slsu:
*
* slsu defines the data setup time after SCL clock
* stretching in terms of i2c clk cycles. The
* needed setup time for the three modes are 250ns,
* 100ns, 10ns repectively thus leading to the values
* of 14, 6, 2 for a 48 MHz i2c clk.
*/
writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
i2c_clk = clk_get_rate(dev->clk);
/* fallback to std. mode if machine has not provided it */
if (dev->cfg.clk_freq == 0)
dev->cfg.clk_freq = 100000;
/*
* The spec says, in case of std. mode the divider is
* 2 whereas it is 3 for fast and fastplus mode of
* operation. TODO - high speed support.
*/
div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
/*
* generate the mask for baud rate counters. The controller
* has two baud rate counters. One is used for High speed
* operation, and the other is for std, fast mode, fast mode
* plus operation. Currently we do not supprt high speed mode
* so set brcr1 to 0.
*/
brcr1 = 0 << 16;
brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
/* set the baud rate counter register */
writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
/*
* set the speed mode. Currently we support
* only standard and fast mode of operation
* TODO - support for fast mode plus (upto 1Mb/s)
* and high speed (up to 3.4 Mb/s)
*/
if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
dev_err(&dev->pdev->dev, "do not support this mode "
"defaulting to std. mode\n");
brcr2 = i2c_clk/(100000 * 2) & 0xffff;
writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
writel(I2C_FREQ_MODE_STANDARD << 4,
dev->virtbase + I2C_CR);
}
writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
/* set the Tx and Rx FIFO threshold */
writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
}
/**
* read_i2c() - Read from I2C client device
* @dev: private data of I2C Driver
*
* This function reads from i2c client device when controller is in
* master mode. There is a completion timeout. If there is no transfer
* before timeout error is returned.
*/
static int read_i2c(struct nmk_i2c_dev *dev)
{
u32 status = 0;
u32 mcr;
u32 irq_mask = 0;
int timeout;
mcr = load_i2c_mcr_reg(dev);
writel(mcr, dev->virtbase + I2C_MCR);
/* load the current CR value */
writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
dev->virtbase + I2C_CR);
/* enable the controller */
i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
init_completion(&dev->xfer_complete);
/* enable interrupts by setting the mask */
irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
I2C_IT_MAL | I2C_IT_BERR);
if (dev->stop)
irq_mask |= I2C_IT_MTD;
else
irq_mask |= I2C_IT_MTDWS;
irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
&dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
if (timeout < 0) {
dev_err(&dev->pdev->dev,
"wait_for_completion_interruptible_timeout"
"returned %d waiting for event\n", timeout);
status = timeout;
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;
}
return status;
}
/**
* write_i2c() - Write data to I2C client.
* @dev: private data of I2C Driver
*
* This function writes data to I2C client
*/
static int write_i2c(struct nmk_i2c_dev *dev)
{
u32 status = 0;
u32 mcr;
u32 irq_mask = 0;
int timeout;
mcr = load_i2c_mcr_reg(dev);
writel(mcr, dev->virtbase + I2C_MCR);
/* load the current CR value */
writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
dev->virtbase + I2C_CR);
/* enable the controller */
i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
init_completion(&dev->xfer_complete);
/* enable interrupts by settings the masks */
irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
I2C_IT_MAL | I2C_IT_BERR);
/*
* check if we want to transfer a single or multiple bytes, if so
* set the MTDWS bit (Master Transaction Done Without Stop)
* to start repeated start operation
*/
if (dev->stop)
irq_mask |= I2C_IT_MTD;
else
irq_mask |= I2C_IT_MTDWS;
irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
&dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
if (timeout < 0) {
dev_err(&dev->pdev->dev,
"wait_for_completion_interruptible_timeout"
"returned %d waiting for event\n", timeout);
status = timeout;
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;
}
return status;
}
/**
* nmk_i2c_xfer() - I2C transfer function used by kernel framework
* @i2c_adap - Adapter pointer to the controller
* @msgs[] - Pointer to data to be written.
* @num_msgs - Number of messages to be executed
*
* This is the function called by the generic kernel i2c_transfer()
* or i2c_smbus...() API calls. Note that this code is protected by the
* semaphore set in the kernel i2c_transfer() function.
*
* NOTE:
* READ TRANSFER : We impose a restriction of the first message to be the
* index message for any read transaction.
* - a no index is coded as '0',
* - 2byte big endian index is coded as '3'
* !!! msg[0].buf holds the actual index.
* This is compatible with generic messages of smbus emulator
* that send a one byte index.
* eg. a I2C transation to read 2 bytes from index 0
* idx = 0;
* msg[0].addr = client->addr;
* msg[0].flags = 0x0;
* msg[0].len = 1;
* msg[0].buf = &idx;
*
* msg[1].addr = client->addr;
* msg[1].flags = I2C_M_RD;
* msg[1].len = 2;
* msg[1].buf = rd_buff
* i2c_transfer(adap, msg, 2);
*
* WRITE TRANSFER : The I2C standard interface interprets all data as payload.
* If you want to emulate an SMBUS write transaction put the
* index as first byte(or first and second) in the payload.
* eg. a I2C transation to write 2 bytes from index 1
* wr_buff[0] = 0x1;
* wr_buff[1] = 0x23;
* wr_buff[2] = 0x46;
* msg[0].flags = 0x0;
* msg[0].len = 3;
* msg[0].buf = wr_buff;
* i2c_transfer(adap, msg, 1);
*
* To read or write a block of data (multiple bytes) using SMBUS emulation
* please use the i2c_smbus_read_i2c_block_data()
* or i2c_smbus_write_i2c_block_data() API
*/
static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msgs[], int num_msgs)
{
int status;
int i;
u32 cause;
struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
status = init_hw(dev);
if (status)
return status;
/* setup the i2c controller */
setup_i2c_controller(dev);
for (i = 0; i < num_msgs; i++) {
if (unlikely(msgs[i].flags & I2C_M_TEN)) {
dev_err(&dev->pdev->dev, "10 bit addressing"
"not supported\n");
return -EINVAL;
}
dev->cli.slave_adr = msgs[i].addr;
dev->cli.buffer = msgs[i].buf;
dev->cli.count = msgs[i].len;
dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
dev->result = 0;
if (msgs[i].flags & I2C_M_RD) {
/* it is a read operation */
dev->cli.operation = I2C_READ;
status = read_i2c(dev);
} else {
/* write operation */
dev->cli.operation = I2C_WRITE;
status = write_i2c(dev);
}
if (status || (dev->result)) {
/* get the abort cause */
cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
dev_err(&dev->pdev->dev, "error during I2C"
"message xfer: %d\n", cause);
dev_err(&dev->pdev->dev, "%s\n",
cause >= ARRAY_SIZE(abort_causes)
? "unknown reason" : abort_causes[cause]);
return status;
}
mdelay(1);
}
/* return the no. messages processed */
if (status)
return status;
else
return num_msgs;
}
/**
* disable_interrupts() - disable the interrupts
* @dev: private data of controller
*/
static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
{
irq = IRQ_MASK(irq);
writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
dev->virtbase + I2C_IMSCR);
return 0;
}
/**
* i2c_irq_handler() - interrupt routine
* @irq: interrupt number
* @arg: data passed to the handler
*
* This is the interrupt handler for the i2c driver. Currently
* it handles the major interrupts like Rx & Tx FIFO management
* interrupts, master transaction interrupts, arbitration and
* bus error interrupts. The rest of the interrupts are treated as
* unhandled.
*/
static irqreturn_t i2c_irq_handler(int irq, void *arg)
{
struct nmk_i2c_dev *dev = arg;
u32 tft, rft;
u32 count;
u32 misr;
u32 src = 0;
/* load Tx FIFO and Rx FIFO threshold values */
tft = readl(dev->virtbase + I2C_TFTR);
rft = readl(dev->virtbase + I2C_RFTR);
/* read interrupt status register */
misr = readl(dev->virtbase + I2C_MISR);
src = __ffs(misr);
switch ((1 << src)) {
/* Transmit FIFO nearly empty interrupt */
case I2C_IT_TXFNE:
{
if (dev->cli.operation == I2C_READ) {
/*
* in read operation why do we care for writing?
* so disable the Transmit FIFO interrupt
*/
disable_interrupts(dev, I2C_IT_TXFNE);
} else {
for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
(count > 0) &&
(dev->cli.count != 0);
count--) {
/* write to the Tx FIFO */
writeb(*dev->cli.buffer,
dev->virtbase + I2C_TFR);
dev->cli.buffer++;
dev->cli.count--;
dev->cli.xfer_bytes++;
}
/*
* if done, close the transfer by disabling the
* corresponding TXFNE interrupt
*/
if (dev->cli.count == 0)
disable_interrupts(dev, I2C_IT_TXFNE);
}
}
break;
/*
* Rx FIFO nearly full interrupt.
* This is set when the numer of entries in Rx FIFO is
* greater or equal than the threshold value programmed
* in RFT
*/
case I2C_IT_RXFNF:
for (count = rft; count > 0; count--) {
/* Read the Rx FIFO */
*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
dev->cli.buffer++;
}
dev->cli.count -= rft;
dev->cli.xfer_bytes += rft;
break;
/* Rx FIFO full */
case I2C_IT_RXFF:
for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
dev->cli.buffer++;
}
dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
break;
/* Master Transaction Done with/without stop */
case I2C_IT_MTD:
case I2C_IT_MTDWS:
if (dev->cli.operation == I2C_READ) {
while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) {
if (dev->cli.count == 0)
break;
*dev->cli.buffer =
readb(dev->virtbase + I2C_RFR);
dev->cli.buffer++;
dev->cli.count--;
dev->cli.xfer_bytes++;
}
}
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
disable_interrupts(dev,
(I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
| I2C_IT_TXFOVR | I2C_IT_RXFNF
| I2C_IT_RXFF | I2C_IT_RXFE));
if (dev->cli.count) {
dev->result = -1;
dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
"xfered\n", dev->cli.count);
(void) init_hw(dev);
}
complete(&dev->xfer_complete);
break;
/* Master Arbitration lost interrupt */
case I2C_IT_MAL:
dev->result = -1;
(void) init_hw(dev);
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
complete(&dev->xfer_complete);
break;
/*
* Bus Error interrupt.
* This happens when an unexpected start/stop condition occurs
* during the transaction.
*/
case I2C_IT_BERR:
dev->result = -1;
/* get the status */
if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
(void) init_hw(dev);
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
complete(&dev->xfer_complete);
break;
/*
* Tx FIFO overrun interrupt.
* This is set when a write operation in Tx FIFO is performed and
* the Tx FIFO is full.
*/
case I2C_IT_TXFOVR:
dev->result = -1;
(void) init_hw(dev);
dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
complete(&dev->xfer_complete);
break;
/* unhandled interrupts by this driver - TODO*/
case I2C_IT_TXFE:
case I2C_IT_TXFF:
case I2C_IT_RXFE:
case I2C_IT_RFSR:
case I2C_IT_RFSE:
case I2C_IT_WTSR:
case I2C_IT_STD:
dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
break;
default:
dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
break;
}
return IRQ_HANDLED;
}
static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
| I2C_FUNC_SMBUS_I2C_BLOCK;
}
static const struct i2c_algorithm nmk_i2c_algo = {
.master_xfer = nmk_i2c_xfer,
.functionality = nmk_i2c_functionality
};
static int __devinit nmk_i2c_probe(struct platform_device *pdev)
{
int ret = 0;
struct resource *res;
struct nmk_i2c_controller *pdata =
pdev->dev.platform_data;
struct nmk_i2c_dev *dev;
struct i2c_adapter *adap;
dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
if (!dev) {
dev_err(&pdev->dev, "cannot allocate memory\n");
ret = -ENOMEM;
goto err_no_mem;
}
dev->pdev = pdev;
platform_set_drvdata(pdev, dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENOENT;
goto err_no_resource;
}
if (request_mem_region(res->start, resource_size(res),
DRIVER_NAME "I/O region") == NULL) {
ret = -EBUSY;
goto err_no_region;
}
dev->virtbase = ioremap(res->start, resource_size(res));
if (!dev->virtbase) {
ret = -ENOMEM;
goto err_no_ioremap;
}
dev->irq = platform_get_irq(pdev, 0);
ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
DRIVER_NAME, dev);
if (ret) {
dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
goto err_irq;
}
dev->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "could not get i2c clock\n");
ret = PTR_ERR(dev->clk);
goto err_no_clk;
}
clk_enable(dev->clk);
adap = &dev->adap;
adap->dev.parent = &pdev->dev;
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
adap->algo = &nmk_i2c_algo;
/* fetch the controller id */
adap->nr = pdev->id;
/* fetch the controller configuration from machine */
dev->cfg.clk_freq = pdata->clk_freq;
dev->cfg.slsu = pdata->slsu;
dev->cfg.tft = pdata->tft;
dev->cfg.rft = pdata->rft;
dev->cfg.sm = pdata->sm;
i2c_set_adapdata(adap, dev);
ret = init_hw(dev);
if (ret != 0) {
dev_err(&pdev->dev, "error in initializing i2c hardware\n");
goto err_init_hw;
}
dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
"base %p\n", pdev->id, dev->virtbase);
ret = i2c_add_numbered_adapter(adap);
if (ret) {
dev_err(&pdev->dev, "failed to add adapter\n");
goto err_add_adap;
}
return 0;
err_init_hw:
clk_disable(dev->clk);
err_add_adap:
clk_put(dev->clk);
err_no_clk:
free_irq(dev->irq, dev);
err_irq:
iounmap(dev->virtbase);
err_no_ioremap:
release_mem_region(res->start, resource_size(res));
err_no_region:
platform_set_drvdata(pdev, NULL);
err_no_resource:
kfree(dev);
err_no_mem:
return ret;
}
static int __devexit nmk_i2c_remove(struct platform_device *pdev)
{
struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
i2c_del_adapter(&dev->adap);
flush_i2c_fifo(dev);
disable_all_interrupts(dev);
clear_all_interrupts(dev);
/* disable the controller */
i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
free_irq(dev->irq, dev);
iounmap(dev->virtbase);
clk_disable(dev->clk);
clk_put(dev->clk);
platform_set_drvdata(pdev, NULL);
kfree(dev);
return 0;
}
static struct platform_driver nmk_i2c_driver = {
.driver = {
.owner = THIS_MODULE,
.name = DRIVER_NAME,
},
.probe = nmk_i2c_probe,
.remove = __devexit_p(nmk_i2c_remove),
};
static int __init nmk_i2c_init(void)
{
return platform_driver_register(&nmk_i2c_driver);
}
static void __exit nmk_i2c_exit(void)
{
platform_driver_unregister(&nmk_i2c_driver);
}
subsys_initcall(nmk_i2c_init);
module_exit(nmk_i2c_exit);
MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);

44
drivers/i2c/busses/i2c-omap.c
View File

@ -49,24 +49,24 @@
#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
#define OMAP_I2C_REV_REG 0x00 #define OMAP_I2C_REV_REG 0x00
#define OMAP_I2C_IE_REG 0x04 #define OMAP_I2C_IE_REG 0x01
#define OMAP_I2C_STAT_REG 0x08 #define OMAP_I2C_STAT_REG 0x02
#define OMAP_I2C_IV_REG 0x0c #define OMAP_I2C_IV_REG 0x03
/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
#define OMAP_I2C_WE_REG 0x0c #define OMAP_I2C_WE_REG 0x03
#define OMAP_I2C_SYSS_REG 0x10 #define OMAP_I2C_SYSS_REG 0x04
#define OMAP_I2C_BUF_REG 0x14 #define OMAP_I2C_BUF_REG 0x05
#define OMAP_I2C_CNT_REG 0x18 #define OMAP_I2C_CNT_REG 0x06
#define OMAP_I2C_DATA_REG 0x1c #define OMAP_I2C_DATA_REG 0x07
#define OMAP_I2C_SYSC_REG 0x20 #define OMAP_I2C_SYSC_REG 0x08
#define OMAP_I2C_CON_REG 0x24 #define OMAP_I2C_CON_REG 0x09
#define OMAP_I2C_OA_REG 0x28 #define OMAP_I2C_OA_REG 0x0a
#define OMAP_I2C_SA_REG 0x2c #define OMAP_I2C_SA_REG 0x0b
#define OMAP_I2C_PSC_REG 0x30 #define OMAP_I2C_PSC_REG 0x0c
#define OMAP_I2C_SCLL_REG 0x34 #define OMAP_I2C_SCLL_REG 0x0d
#define OMAP_I2C_SCLH_REG 0x38 #define OMAP_I2C_SCLH_REG 0x0e
#define OMAP_I2C_SYSTEST_REG 0x3c #define OMAP_I2C_SYSTEST_REG 0x0f
#define OMAP_I2C_BUFSTAT_REG 0x40 #define OMAP_I2C_BUFSTAT_REG 0x10
/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
@ -161,6 +161,7 @@ struct omap_i2c_dev {
struct device *dev; struct device *dev;
void __iomem *base; /* virtual */ void __iomem *base; /* virtual */
int irq; int irq;
int reg_shift; /* bit shift for I2C register addresses */
struct clk *iclk; /* Interface clock */ struct clk *iclk; /* Interface clock */
struct clk *fclk; /* Functional clock */ struct clk *fclk; /* Functional clock */
struct completion cmd_complete; struct completion cmd_complete;
@ -189,12 +190,12 @@ struct omap_i2c_dev {
static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
int reg, u16 val) int reg, u16 val)
{ {
__raw_writew(val, i2c_dev->base + reg); __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift));
} }
static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
{ {
return __raw_readw(i2c_dev->base + reg); return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift));
} }
static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
@ -924,6 +925,11 @@ omap_i2c_probe(struct platform_device *pdev)
dev->b_hw = 1; /* Enable hardware fixes */ dev->b_hw = 1; /* Enable hardware fixes */
} }
if (cpu_is_omap7xx())
dev->reg_shift = 1;
else
dev->reg_shift = 2;
/* reset ASAP, clearing any IRQs */ /* reset ASAP, clearing any IRQs */
omap_i2c_init(dev); omap_i2c_init(dev);

11
drivers/i2c/busses/i2c-pnx.c
View File

@ -172,12 +172,6 @@ static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
/* We still have something to talk about... */ /* We still have something to talk about... */
val = *alg_data->mif.buf++; val = *alg_data->mif.buf++;
if (alg_data->mif.len == 1) {
val |= stop_bit;
if (!alg_data->last)
val |= start_bit;
}
alg_data->mif.len--; alg_data->mif.len--;
iowrite32(val, I2C_REG_TX(alg_data)); iowrite32(val, I2C_REG_TX(alg_data));
@ -251,11 +245,6 @@ static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
__func__); __func__);
if (alg_data->mif.len == 1) { if (alg_data->mif.len == 1) {
/* Last byte, do not acknowledge next rcv. */
val |= stop_bit;
if (!alg_data->last)
val |= start_bit;
/* /*
* Enable interrupt RFDAIE (data in Rx fifo), * Enable interrupt RFDAIE (data in Rx fifo),
* and disable DRMIE (need data for Tx) * and disable DRMIE (need data for Tx)

824
drivers/i2c/busses/i2c-xiic.c Normal file
View File

@ -0,0 +1,824 @@
/*
* i2c-xiic.c
* Copyright (c) 2002-2007 Xilinx Inc.
* Copyright (c) 2009-2010 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* This code was implemented by Mocean Laboratories AB when porting linux
* to the automotive development board Russellville. The copyright holder
* as seen in the header is Intel corporation.
* Mocean Laboratories forked off the GNU/Linux platform work into a
* separate company called Pelagicore AB, which commited the code to the
* kernel.
*/
/* Supports:
* Xilinx IIC
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/i2c-xiic.h>
#include <linux/io.h>
#define DRIVER_NAME "xiic-i2c"
enum xilinx_i2c_state {
STATE_DONE,
STATE_ERROR,
STATE_START
};
/**
* struct xiic_i2c - Internal representation of the XIIC I2C bus
* @base: Memory base of the HW registers
* @wait: Wait queue for callers
* @adap: Kernel adapter representation
* @tx_msg: Messages from above to be sent
* @lock: Mutual exclusion
* @tx_pos: Current pos in TX message
* @nmsgs: Number of messages in tx_msg
* @state: See STATE_
* @rx_msg: Current RX message
* @rx_pos: Position within current RX message
*/
struct xiic_i2c {
void __iomem *base;
wait_queue_head_t wait;
struct i2c_adapter adap;
struct i2c_msg *tx_msg;
spinlock_t lock;
unsigned int tx_pos;
unsigned int nmsgs;
enum xilinx_i2c_state state;
struct i2c_msg *rx_msg;
int rx_pos;
};
#define XIIC_MSB_OFFSET 0
#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
/*
* Register offsets in bytes from RegisterBase. Three is added to the
* base offset to access LSB (IBM style) of the word
*/
#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
/* Control Register masks */
#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
/* Status Register masks */
#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
/* Interrupt Status Register masks Interrupt occurs when... */
#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
/* The following constants specify the depth of the FIFOs */
#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
/* The following constants specify groups of interrupts that are typically
* enabled or disables at the same time
*/
#define XIIC_TX_INTERRUPTS \
(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
/* The following constants are used with the following macros to specify the
* operation, a read or write operation.
*/
#define XIIC_READ_OPERATION 1
#define XIIC_WRITE_OPERATION 0
/*
* Tx Fifo upper bit masks.
*/
#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
/*
* The following constants define the register offsets for the Interrupt
* registers. There are some holes in the memory map for reserved addresses
* to allow other registers to be added and still match the memory map of the
* interrupt controller registers
*/
#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
#define XIIC_RESET_MASK 0xAUL
/*
* The following constant is used for the device global interrupt enable
* register, to enable all interrupts for the device, this is the only bit
* in the register
*/
#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
static void xiic_start_xfer(struct xiic_i2c *i2c);
static void __xiic_start_xfer(struct xiic_i2c *i2c);
static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
{
iowrite8(value, i2c->base + reg);
}
static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
{
return ioread8(i2c->base + reg);
}
static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
{
iowrite16(value, i2c->base + reg);
}
static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
{
iowrite32(value, i2c->base + reg);
}
static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
{
return ioread32(i2c->base + reg);
}
static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
{
u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
}
static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
{
u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
}
static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
{
u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
}
static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
{
xiic_irq_clr(i2c, mask);
xiic_irq_en(i2c, mask);
}
static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
{
u8 sr;
for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
}
static void xiic_reinit(struct xiic_i2c *i2c)
{
xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
/* Set receive Fifo depth to maximum (zero based). */
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
/* Reset Tx Fifo. */
xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
/* Enable IIC Device, remove Tx Fifo reset & disable general call. */
xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
/* make sure RX fifo is empty */
xiic_clear_rx_fifo(i2c);
/* Enable interrupts */
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
}
static void xiic_deinit(struct xiic_i2c *i2c)
{
u8 cr;
xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
/* Disable IIC Device. */
cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
}
static void xiic_read_rx(struct xiic_i2c *i2c)
{
u8 bytes_in_fifo;
int i;
bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
", SR: 0x%x, CR: 0x%x\n",
__func__, bytes_in_fifo, xiic_rx_space(i2c),
xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
if (bytes_in_fifo > xiic_rx_space(i2c))
bytes_in_fifo = xiic_rx_space(i2c);
for (i = 0; i < bytes_in_fifo; i++)
i2c->rx_msg->buf[i2c->rx_pos++] =
xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
(xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
}
static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
{
/* return the actual space left in the FIFO */
return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
}
static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
{
u8 fifo_space = xiic_tx_fifo_space(i2c);
int len = xiic_tx_space(i2c);
len = (len > fifo_space) ? fifo_space : len;
dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
__func__, len, fifo_space);
while (len--) {
u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
/* last message in transfer -> STOP */
data |= XIIC_TX_DYN_STOP_MASK;
dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
} else
xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
}
}
static void xiic_wakeup(struct xiic_i2c *i2c, int code)
{
i2c->tx_msg = NULL;
i2c->rx_msg = NULL;
i2c->nmsgs = 0;
i2c->state = code;
wake_up(&i2c->wait);
}
static void xiic_process(struct xiic_i2c *i2c)
{
u32 pend, isr, ier;
u32 clr = 0;
/* Get the interrupt Status from the IPIF. There is no clearing of
* interrupts in the IPIF. Interrupts must be cleared at the source.
* To find which interrupts are pending; AND interrupts pending with
* interrupts masked.
*/
isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
pend = isr & ier;
dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
"pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
__func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
i2c->tx_msg, i2c->nmsgs);
/* Do not processes a devices interrupts if the device has no
* interrupts pending
*/
if (!pend)
return;
/* Service requesting interrupt */
if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
((pend & XIIC_INTR_TX_ERROR_MASK) &&
!(pend & XIIC_INTR_RX_FULL_MASK))) {
/* bus arbritration lost, or...
* Transmit error _OR_ RX completed
* if this happens when RX_FULL is not set
* this is probably a TX error
*/
dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
/* dynamic mode seem to suffer from problems if we just flushes
* fifos and the next message is a TX with len 0 (only addr)
* reset the IP instead of just flush fifos
*/
xiic_reinit(i2c);
if (i2c->tx_msg)
xiic_wakeup(i2c, STATE_ERROR);
} else if (pend & XIIC_INTR_RX_FULL_MASK) {
/* Receive register/FIFO is full */
clr = XIIC_INTR_RX_FULL_MASK;
if (!i2c->rx_msg) {
dev_dbg(i2c->adap.dev.parent,
"%s unexpexted RX IRQ\n", __func__);
xiic_clear_rx_fifo(i2c);
goto out;
}
xiic_read_rx(i2c);
if (xiic_rx_space(i2c) == 0) {
/* this is the last part of the message */
i2c->rx_msg = NULL;
/* also clear TX error if there (RX complete) */
clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
dev_dbg(i2c->adap.dev.parent,
"%s end of message, nmsgs: %d\n",
__func__, i2c->nmsgs);
/* send next message if this wasn't the last,
* otherwise the transfer will be finialise when
* receiving the bus not busy interrupt
*/
if (i2c->nmsgs > 1) {
i2c->nmsgs--;
i2c->tx_msg++;
dev_dbg(i2c->adap.dev.parent,
"%s will start next...\n", __func__);
__xiic_start_xfer(i2c);
}
}
} else if (pend & XIIC_INTR_BNB_MASK) {
/* IIC bus has transitioned to not busy */
clr = XIIC_INTR_BNB_MASK;
/* The bus is not busy, disable BusNotBusy interrupt */
xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
if (!i2c->tx_msg)
goto out;
if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
xiic_tx_space(i2c) == 0)
xiic_wakeup(i2c, STATE_DONE);
else
xiic_wakeup(i2c, STATE_ERROR);
} else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
/* Transmit register/FIFO is empty or ½ empty */
clr = pend &
(XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
if (!i2c->tx_msg) {
dev_dbg(i2c->adap.dev.parent,
"%s unexpexted TX IRQ\n", __func__);
goto out;
}
xiic_fill_tx_fifo(i2c);
/* current message sent and there is space in the fifo */
if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
dev_dbg(i2c->adap.dev.parent,
"%s end of message sent, nmsgs: %d\n",
__func__, i2c->nmsgs);
if (i2c->nmsgs > 1) {
i2c->nmsgs--;
i2c->tx_msg++;
__xiic_start_xfer(i2c);
} else {
xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
dev_dbg(i2c->adap.dev.parent,
"%s Got TX IRQ but no more to do...\n",
__func__);
}
} else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
/* current frame is sent and is last,
* make sure to disable tx half
*/
xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
} else {
/* got IRQ which is not acked */
dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
__func__);
clr = pend;
}
out:
dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
}
static int xiic_bus_busy(struct xiic_i2c *i2c)
{
u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
}
static int xiic_busy(struct xiic_i2c *i2c)
{
int tries = 3;
int err;
if (i2c->tx_msg)
return -EBUSY;
/* for instance if previous transfer was terminated due to TX error
* it might be that the bus is on it's way to become available
* give it at most 3 ms to wake
*/
err = xiic_bus_busy(i2c);
while (err && tries--) {
mdelay(1);
err = xiic_bus_busy(i2c);
}
return err;
}
static void xiic_start_recv(struct xiic_i2c *i2c)
{
u8 rx_watermark;
struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
/* Clear and enable Rx full interrupt. */
xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
/* we want to get all but last byte, because the TX_ERROR IRQ is used
* to inidicate error ACK on the address, and negative ack on the last
* received byte, so to not mix them receive all but last.
* In the case where there is only one byte to receive
* we can check if ERROR and RX full is set at the same time
*/
rx_watermark = msg->len;
if (rx_watermark > IIC_RX_FIFO_DEPTH)
rx_watermark = IIC_RX_FIFO_DEPTH;
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
if (!(msg->flags & I2C_M_NOSTART))
/* write the address */
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
(msg->addr << 1) | XIIC_READ_OPERATION |
XIIC_TX_DYN_START_MASK);
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
if (i2c->nmsgs == 1)
/* very last, enable bus not busy as well */
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
/* the message is tx:ed */
i2c->tx_pos = msg->len;
}
static void xiic_start_send(struct xiic_i2c *i2c)
{
struct i2c_msg *msg = i2c->tx_msg;
xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, "
"ISR: 0x%x, CR: 0x%x\n",
__func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
if (!(msg->flags & I2C_M_NOSTART)) {
/* write the address */
u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
XIIC_TX_DYN_START_MASK;
if ((i2c->nmsgs == 1) && msg->len == 0)
/* no data and last message -> add STOP */
data |= XIIC_TX_DYN_STOP_MASK;
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
}
xiic_fill_tx_fifo(i2c);
/* Clear any pending Tx empty, Tx Error and then enable them. */
xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_BNB_MASK);
}
static irqreturn_t xiic_isr(int irq, void *dev_id)
{
struct xiic_i2c *i2c = dev_id;
spin_lock(&i2c->lock);
/* disable interrupts globally */
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
xiic_process(i2c);
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
spin_unlock(&i2c->lock);
return IRQ_HANDLED;
}
static void __xiic_start_xfer(struct xiic_i2c *i2c)
{
int first = 1;
int fifo_space = xiic_tx_fifo_space(i2c);
dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
__func__, i2c->tx_msg, fifo_space);
if (!i2c->tx_msg)
return;
i2c->rx_pos = 0;
i2c->tx_pos = 0;
i2c->state = STATE_START;
while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
if (!first) {
i2c->nmsgs--;
i2c->tx_msg++;
i2c->tx_pos = 0;
} else
first = 0;
if (i2c->tx_msg->flags & I2C_M_RD) {
/* we dont date putting several reads in the FIFO */
xiic_start_recv(i2c);
return;
} else {
xiic_start_send(i2c);
if (xiic_tx_space(i2c) != 0) {
/* the message could not be completely sent */
break;
}
}
fifo_space = xiic_tx_fifo_space(i2c);
}
/* there are more messages or the current one could not be completely
* put into the FIFO, also enable the half empty interrupt
*/
if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
}
static void xiic_start_xfer(struct xiic_i2c *i2c)
{
unsigned long flags;
spin_lock_irqsave(&i2c->lock, flags);
xiic_reinit(i2c);
/* disable interrupts globally */
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
spin_unlock_irqrestore(&i2c->lock, flags);
__xiic_start_xfer(i2c);
xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
}
static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct xiic_i2c *i2c = i2c_get_adapdata(adap);
int err;
dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
err = xiic_busy(i2c);
if (err)
return err;
i2c->tx_msg = msgs;
i2c->nmsgs = num;
xiic_start_xfer(i2c);
if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
(i2c->state == STATE_DONE), HZ))
return (i2c->state == STATE_DONE) ? num : -EIO;
else {
i2c->tx_msg = NULL;
i2c->rx_msg = NULL;
i2c->nmsgs = 0;
return -ETIMEDOUT;
}
}
static u32 xiic_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm xiic_algorithm = {
.master_xfer = xiic_xfer,
.functionality = xiic_func,
};
static struct i2c_adapter xiic_adapter = {
.owner = THIS_MODULE,
.name = DRIVER_NAME,
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
.algo = &xiic_algorithm,
};
static int __devinit xiic_i2c_probe(struct platform_device *pdev)
{
struct xiic_i2c *i2c;
struct xiic_i2c_platform_data *pdata;
struct resource *res;
int ret, irq;
u8 i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
goto resource_missing;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
goto resource_missing;
pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data;
if (!pdata)
return -EINVAL;
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
dev_err(&pdev->dev, "Memory region busy\n");
ret = -EBUSY;
goto request_mem_failed;
}
i2c->base = ioremap(res->start, resource_size(res));
if (!i2c->base) {
dev_err(&pdev->dev, "Unable to map registers\n");
ret = -EIO;
goto map_failed;
}
/* hook up driver to tree */
platform_set_drvdata(pdev, i2c);
i2c->adap = xiic_adapter;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent = &pdev->dev;
xiic_reinit(i2c);
spin_lock_init(&i2c->lock);
init_waitqueue_head(&i2c->wait);
ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c);
if (ret) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
goto request_irq_failed;
}
/* add i2c adapter to i2c tree */
ret = i2c_add_adapter(&i2c->adap);
if (ret) {
dev_err(&pdev->dev, "Failed to add adapter\n");
goto add_adapter_failed;
}
/* add in known devices to the bus */
for (i = 0; i < pdata->num_devices; i++)
i2c_new_device(&i2c->adap, pdata->devices + i);
return 0;
add_adapter_failed:
free_irq(irq, i2c);
request_irq_failed:
xiic_deinit(i2c);
iounmap(i2c->base);
map_failed:
release_mem_region(res->start, resource_size(res));
request_mem_failed:
kfree(i2c);
return ret;
resource_missing:
dev_err(&pdev->dev, "IRQ or Memory resource is missing\n");
return -ENOENT;
}
static int __devexit xiic_i2c_remove(struct platform_device* pdev)
{
struct xiic_i2c *i2c = platform_get_drvdata(pdev);
struct resource *res;
/* remove adapter & data */
i2c_del_adapter(&i2c->adap);
xiic_deinit(i2c);
platform_set_drvdata(pdev, NULL);
free_irq(platform_get_irq(pdev, 0), i2c);
iounmap(i2c->base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res)
release_mem_region(res->start, resource_size(res));
kfree(i2c);
return 0;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:"DRIVER_NAME);
static struct platform_driver xiic_i2c_driver = {
.probe = xiic_i2c_probe,
.remove = __devexit_p(xiic_i2c_remove),
.driver = {
.owner = THIS_MODULE,
.name = DRIVER_NAME,
},
};
static int __init xiic_i2c_init(void)
{
return platform_driver_register(&xiic_i2c_driver);
}
static void __exit xiic_i2c_exit(void)
{
platform_driver_unregister(&xiic_i2c_driver);
}
module_init(xiic_i2c_init);
module_exit(xiic_i2c_exit);
MODULE_AUTHOR("info@mocean-labs.com");
MODULE_DESCRIPTION("Xilinx I2C bus driver");
MODULE_LICENSE("GPL v2");