OMAPDSS: DISPC: Cleanup cpu_is_xxxx checks
All the cpu_is checks have been moved to dispc_init_features function providing a much more generic and cleaner interface. The OMAP version and revision specific functions and data are initialized by dispc_features structure which is local to dispc.c. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Chandrabhanu Mahapatra
Tomi Valkeinen
parent
0b3d9cfe7d
commit
dcbe765b4f
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@ -81,6 +81,23 @@ struct dispc_irq_stats {
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unsigned irqs[32];
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};
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struct dispc_features {
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u8 sw_start;
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u8 fp_start;
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u8 bp_start;
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u16 sw_max;
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u16 vp_max;
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u16 hp_max;
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int (*calc_scaling) (enum omap_channel channel,
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const struct omap_video_timings *mgr_timings,
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u16 width, u16 height, u16 out_width, u16 out_height,
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enum omap_color_mode color_mode, bool *five_taps,
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int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
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u16 pos_x, unsigned long *core_clk);
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unsigned long (*calc_core_clk) (enum omap_channel channel,
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u16 width, u16 height, u16 out_width, u16 out_height);
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};
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static struct {
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struct platform_device *pdev;
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void __iomem *base;
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@ -101,6 +118,8 @@ static struct {
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bool ctx_valid;
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u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
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const struct dispc_features *feat;
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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spinlock_t irq_stats_lock;
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struct dispc_irq_stats irq_stats;
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@ -1939,7 +1958,18 @@ static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
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return core_clk;
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}
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static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
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static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width,
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u16 height, u16 out_width, u16 out_height)
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{
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unsigned long pclk = dispc_mgr_pclk_rate(channel);
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if (height > out_height && width > out_width)
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return pclk * 4;
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else
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return pclk * 2;
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}
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static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width,
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u16 height, u16 out_width, u16 out_height)
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{
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unsigned int hf, vf;
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@ -1958,25 +1988,163 @@ static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
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hf = 2;
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else
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hf = 1;
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if (height > out_height)
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vf = 2;
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else
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vf = 1;
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if (cpu_is_omap24xx()) {
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if (vf > 1 && hf > 1)
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return pclk * 4;
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else
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return pclk * 2;
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} else if (cpu_is_omap34xx()) {
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return pclk * vf * hf;
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} else {
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if (hf > 1)
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return DIV_ROUND_UP(pclk, out_width) * width;
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else
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return pclk;
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return pclk * vf * hf;
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}
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static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width,
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u16 height, u16 out_width, u16 out_height)
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{
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unsigned long pclk = dispc_mgr_pclk_rate(channel);
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if (width > out_width)
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return DIV_ROUND_UP(pclk, out_width) * width;
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else
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return pclk;
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}
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static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel,
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const struct omap_video_timings *mgr_timings,
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u16 width, u16 height, u16 out_width, u16 out_height,
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enum omap_color_mode color_mode, bool *five_taps,
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int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
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u16 pos_x, unsigned long *core_clk)
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{
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int error;
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u16 in_width, in_height;
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int min_factor = min(*decim_x, *decim_y);
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const int maxsinglelinewidth =
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dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
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*five_taps = false;
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do {
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in_height = DIV_ROUND_UP(height, *decim_y);
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in_width = DIV_ROUND_UP(width, *decim_x);
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*core_clk = dispc.feat->calc_core_clk(channel, in_width,
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in_height, out_width, out_height);
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error = (in_width > maxsinglelinewidth || !*core_clk ||
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*core_clk > dispc_core_clk_rate());
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if (error) {
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if (*decim_x == *decim_y) {
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*decim_x = min_factor;
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++*decim_y;
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} else {
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swap(*decim_x, *decim_y);
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if (*decim_x < *decim_y)
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++*decim_x;
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}
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}
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} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
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if (in_width > maxsinglelinewidth) {
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DSSERR("Cannot scale max input width exceeded");
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return -EINVAL;
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}
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return 0;
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}
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static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel,
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const struct omap_video_timings *mgr_timings,
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u16 width, u16 height, u16 out_width, u16 out_height,
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enum omap_color_mode color_mode, bool *five_taps,
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int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
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u16 pos_x, unsigned long *core_clk)
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{
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int error;
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u16 in_width, in_height;
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int min_factor = min(*decim_x, *decim_y);
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const int maxsinglelinewidth =
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dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
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do {
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in_height = DIV_ROUND_UP(height, *decim_y);
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in_width = DIV_ROUND_UP(width, *decim_x);
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*core_clk = calc_core_clk_five_taps(channel, mgr_timings,
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in_width, in_height, out_width, out_height, color_mode);
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error = check_horiz_timing_omap3(channel, mgr_timings, pos_x,
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in_width, in_height, out_width, out_height);
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if (in_width > maxsinglelinewidth)
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if (in_height > out_height &&
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in_height < out_height * 2)
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*five_taps = false;
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if (!*five_taps)
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*core_clk = dispc.feat->calc_core_clk(channel, in_width,
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in_height, out_width, out_height);
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error = (error || in_width > maxsinglelinewidth * 2 ||
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(in_width > maxsinglelinewidth && *five_taps) ||
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!*core_clk || *core_clk > dispc_core_clk_rate());
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if (error) {
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if (*decim_x == *decim_y) {
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*decim_x = min_factor;
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++*decim_y;
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} else {
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swap(*decim_x, *decim_y);
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if (*decim_x < *decim_y)
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++*decim_x;
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}
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}
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} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
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if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height,
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out_width, out_height)){
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DSSERR("horizontal timing too tight\n");
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return -EINVAL;
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}
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if (in_width > (maxsinglelinewidth * 2)) {
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DSSERR("Cannot setup scaling");
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DSSERR("width exceeds maximum width possible");
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return -EINVAL;
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}
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if (in_width > maxsinglelinewidth && *five_taps) {
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DSSERR("cannot setup scaling with five taps");
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return -EINVAL;
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}
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return 0;
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}
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static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel,
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const struct omap_video_timings *mgr_timings,
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u16 width, u16 height, u16 out_width, u16 out_height,
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enum omap_color_mode color_mode, bool *five_taps,
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int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
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u16 pos_x, unsigned long *core_clk)
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{
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u16 in_width, in_width_max;
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int decim_x_min = *decim_x;
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u16 in_height = DIV_ROUND_UP(height, *decim_y);
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const int maxsinglelinewidth =
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dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
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in_width_max = dispc_core_clk_rate() /
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DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width);
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*decim_x = DIV_ROUND_UP(width, in_width_max);
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*decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
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if (*decim_x > *x_predecim)
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return -EINVAL;
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do {
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in_width = DIV_ROUND_UP(width, *decim_x);
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} while (*decim_x <= *x_predecim &&
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in_width > maxsinglelinewidth && ++*decim_x);
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if (in_width > maxsinglelinewidth) {
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DSSERR("Cannot scale width exceeds max line width");
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return -EINVAL;
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}
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*core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height,
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out_width, out_height);
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return 0;
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}
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static int dispc_ovl_calc_scaling(enum omap_plane plane,
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@ -1988,12 +2156,9 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
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{
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struct omap_overlay *ovl = omap_dss_get_overlay(plane);
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const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
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const int maxsinglelinewidth =
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dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
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const int max_decim_limit = 16;
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unsigned long core_clk = 0;
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int decim_x, decim_y, error, min_factor;
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u16 in_width, in_height, in_width_max = 0;
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int decim_x, decim_y, ret;
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if (width == out_width && height == out_height)
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return 0;
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@ -2017,118 +2182,17 @@ static int dispc_ovl_calc_scaling(enum omap_plane plane,
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decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
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decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
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min_factor = min(decim_x, decim_y);
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if (decim_x > *x_predecim || out_width > width * 8)
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return -EINVAL;
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if (decim_y > *y_predecim || out_height > height * 8)
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return -EINVAL;
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if (cpu_is_omap24xx()) {
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*five_taps = false;
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do {
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in_height = DIV_ROUND_UP(height, decim_y);
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in_width = DIV_ROUND_UP(width, decim_x);
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core_clk = calc_core_clk(channel, in_width, in_height,
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out_width, out_height);
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error = (in_width > maxsinglelinewidth || !core_clk ||
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core_clk > dispc_core_clk_rate());
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if (error) {
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if (decim_x == decim_y) {
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decim_x = min_factor;
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decim_y++;
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} else {
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swap(decim_x, decim_y);
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if (decim_x < decim_y)
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decim_x++;
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}
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}
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} while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
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error);
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if (in_width > maxsinglelinewidth) {
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DSSERR("Cannot scale max input width exceeded");
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return -EINVAL;
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}
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} else if (cpu_is_omap34xx()) {
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do {
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in_height = DIV_ROUND_UP(height, decim_y);
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in_width = DIV_ROUND_UP(width, decim_x);
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core_clk = calc_core_clk_five_taps(channel, mgr_timings,
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in_width, in_height, out_width, out_height,
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color_mode);
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error = check_horiz_timing_omap3(channel, mgr_timings,
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pos_x, in_width, in_height, out_width,
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out_height);
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if (in_width > maxsinglelinewidth)
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if (in_height > out_height &&
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in_height < out_height * 2)
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*five_taps = false;
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if (!*five_taps)
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core_clk = calc_core_clk(channel, in_width,
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in_height, out_width, out_height);
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error = (error || in_width > maxsinglelinewidth * 2 ||
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(in_width > maxsinglelinewidth && *five_taps) ||
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!core_clk || core_clk > dispc_core_clk_rate());
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if (error) {
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if (decim_x == decim_y) {
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decim_x = min_factor;
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decim_y++;
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} else {
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swap(decim_x, decim_y);
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if (decim_x < decim_y)
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decim_x++;
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}
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}
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} while (decim_x <= *x_predecim && decim_y <= *y_predecim
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&& error);
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if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
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height, out_width, out_height)){
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DSSERR("horizontal timing too tight\n");
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return -EINVAL;
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}
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if (in_width > (maxsinglelinewidth * 2)) {
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DSSERR("Cannot setup scaling");
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DSSERR("width exceeds maximum width possible");
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return -EINVAL;
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}
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if (in_width > maxsinglelinewidth && *five_taps) {
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DSSERR("cannot setup scaling with five taps");
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return -EINVAL;
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}
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} else {
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int decim_x_min = decim_x;
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in_height = DIV_ROUND_UP(height, decim_y);
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in_width_max = dispc_core_clk_rate() /
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DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
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out_width);
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decim_x = DIV_ROUND_UP(width, in_width_max);
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decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
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if (decim_x > *x_predecim)
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return -EINVAL;
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do {
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in_width = DIV_ROUND_UP(width, decim_x);
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} while (decim_x <= *x_predecim &&
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in_width > maxsinglelinewidth && decim_x++);
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if (in_width > maxsinglelinewidth) {
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DSSERR("Cannot scale width exceeds max line width");
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return -EINVAL;
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}
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core_clk = calc_core_clk(channel, in_width, in_height,
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out_width, out_height);
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}
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ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height,
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out_width, out_height, color_mode, five_taps, x_predecim,
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y_predecim, &decim_x, &decim_y, pos_x, &core_clk);
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if (ret)
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return ret;
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DSSDBG("required core clk rate = %lu Hz\n", core_clk);
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DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
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@ -2604,24 +2668,13 @@ static bool _dispc_mgr_size_ok(u16 width, u16 height)
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static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
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int vsw, int vfp, int vbp)
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{
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if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
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if (hsw < 1 || hsw > 64 ||
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hfp < 1 || hfp > 256 ||
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hbp < 1 || hbp > 256 ||
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vsw < 1 || vsw > 64 ||
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vfp < 0 || vfp > 255 ||
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vbp < 0 || vbp > 255)
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return false;
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} else {
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if (hsw < 1 || hsw > 256 ||
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hfp < 1 || hfp > 4096 ||
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hbp < 1 || hbp > 4096 ||
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vsw < 1 || vsw > 256 ||
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vfp < 0 || vfp > 4095 ||
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vbp < 0 || vbp > 4095)
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return false;
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}
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if (hsw < 1 || hsw > dispc.feat->sw_max ||
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hfp < 1 || hfp > dispc.feat->hp_max ||
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hbp < 1 || hbp > dispc.feat->hp_max ||
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vsw < 1 || vsw > dispc.feat->sw_max ||
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vfp < 0 || vfp > dispc.feat->vp_max ||
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vbp < 0 || vbp > dispc.feat->vp_max)
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return false;
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return true;
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}
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@ -2653,19 +2706,12 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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u32 timing_h, timing_v, l;
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bool onoff, rf, ipc;
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if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
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timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
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FLD_VAL(hbp-1, 27, 20);
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timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
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FLD_VAL(vbp, 27, 20);
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} else {
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timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
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FLD_VAL(hbp-1, 31, 20);
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timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
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||||
FLD_VAL(vbp, 31, 20);
|
||||
}
|
||||
timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
|
||||
FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
|
||||
FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
|
||||
timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
|
||||
FLD_VAL(vfp, dispc.feat->fp_start, 8) |
|
||||
FLD_VAL(vbp, dispc.feat->bp_start, 20);
|
||||
|
||||
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
|
||||
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
|
||||
|
|
@ -3671,6 +3717,80 @@ static void _omap_dispc_initial_config(void)
|
|||
dispc_ovl_enable_zorder_planes();
|
||||
}
|
||||
|
||||
static const struct dispc_features omap24xx_dispc_feats __initconst = {
|
||||
.sw_start = 5,
|
||||
.fp_start = 15,
|
||||
.bp_start = 27,
|
||||
.sw_max = 64,
|
||||
.vp_max = 255,
|
||||
.hp_max = 256,
|
||||
.calc_scaling = dispc_ovl_calc_scaling_24xx,
|
||||
.calc_core_clk = calc_core_clk_24xx,
|
||||
};
|
||||
|
||||
static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
|
||||
.sw_start = 5,
|
||||
.fp_start = 15,
|
||||
.bp_start = 27,
|
||||
.sw_max = 64,
|
||||
.vp_max = 255,
|
||||
.hp_max = 256,
|
||||
.calc_scaling = dispc_ovl_calc_scaling_34xx,
|
||||
.calc_core_clk = calc_core_clk_34xx,
|
||||
};
|
||||
|
||||
static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
|
||||
.sw_start = 7,
|
||||
.fp_start = 19,
|
||||
.bp_start = 31,
|
||||
.sw_max = 256,
|
||||
.vp_max = 4095,
|
||||
.hp_max = 4096,
|
||||
.calc_scaling = dispc_ovl_calc_scaling_34xx,
|
||||
.calc_core_clk = calc_core_clk_34xx,
|
||||
};
|
||||
|
||||
static const struct dispc_features omap44xx_dispc_feats __initconst = {
|
||||
.sw_start = 7,
|
||||
.fp_start = 19,
|
||||
.bp_start = 31,
|
||||
.sw_max = 256,
|
||||
.vp_max = 4095,
|
||||
.hp_max = 4096,
|
||||
.calc_scaling = dispc_ovl_calc_scaling_44xx,
|
||||
.calc_core_clk = calc_core_clk_44xx,
|
||||
};
|
||||
|
||||
static int __init dispc_init_features(struct device *dev)
|
||||
{
|
||||
const struct dispc_features *src;
|
||||
struct dispc_features *dst;
|
||||
|
||||
dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
|
||||
if (!dst) {
|
||||
dev_err(dev, "Failed to allocate DISPC Features\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
src = &omap24xx_dispc_feats;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
if (omap_rev() < OMAP3430_REV_ES3_0)
|
||||
src = &omap34xx_rev1_0_dispc_feats;
|
||||
else
|
||||
src = &omap34xx_rev3_0_dispc_feats;
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
src = &omap44xx_dispc_feats;
|
||||
} else {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
memcpy(dst, src, sizeof(*dst));
|
||||
dispc.feat = dst;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* DISPC HW IP initialisation */
|
||||
static int __init omap_dispchw_probe(struct platform_device *pdev)
|
||||
{
|
||||
|
|
@ -3681,6 +3801,10 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
|
|||
|
||||
dispc.pdev = pdev;
|
||||
|
||||
r = dispc_init_features(&dispc.pdev->dev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
spin_lock_init(&dispc.irq_lock);
|
||||
|
||||
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
|
||||
|
|
|
|||
Loading…
Reference in New Issue