net/mlx5e: Add a counter for congested UMRs
Add per-ring and global ethtool counters for congested UMR requests. These events indicate congestion in UMR handlers in HW. Such event is concluded when there's an outstanding UMR post, yet the SW consumed at least two additional MPWQEs in the meanwhile. Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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@ -601,6 +601,8 @@ bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
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if (!rq->mpwqe.umr_in_progress)
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mlx5e_alloc_rx_mpwqe(rq, wq->head);
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else
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rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
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return false;
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}
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@ -83,6 +83,7 @@ static const struct counter_desc sw_stats_desc[] = {
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
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{ MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
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@ -152,6 +153,7 @@ void mlx5e_grp_sw_update_stats(struct mlx5e_priv *priv)
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s->rx_cache_empty += rq_stats->cache_empty;
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s->rx_cache_busy += rq_stats->cache_busy;
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s->rx_cache_waive += rq_stats->cache_waive;
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s->rx_congst_umr += rq_stats->congst_umr;
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s->ch_poll += ch_stats->poll;
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s->ch_arm += ch_stats->arm;
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s->ch_aff_change += ch_stats->aff_change;
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@ -1135,6 +1137,7 @@ static const struct counter_desc rq_stats_desc[] = {
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{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
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{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
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{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
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{ MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
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};
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static const struct counter_desc sq_stats_desc[] = {
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@ -94,6 +94,7 @@ struct mlx5e_sw_stats {
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u64 rx_cache_empty;
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u64 rx_cache_busy;
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u64 rx_cache_waive;
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u64 rx_congst_umr;
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u64 ch_poll;
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u64 ch_arm;
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u64 ch_aff_change;
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@ -188,6 +189,7 @@ struct mlx5e_rq_stats {
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u64 cache_empty;
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u64 cache_busy;
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u64 cache_waive;
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u64 congst_umr;
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};
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struct mlx5e_sq_stats {
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@ -229,6 +229,11 @@ static inline int mlx5_wq_ll_is_empty(struct mlx5_wq_ll *wq)
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return !wq->cur_sz;
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}
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static inline int mlx5_wq_ll_missing(struct mlx5_wq_ll *wq)
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{
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return wq->fbc.sz_m1 - wq->cur_sz;
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}
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static inline void *mlx5_wq_ll_get_wqe(struct mlx5_wq_ll *wq, u16 ix)
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{
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return mlx5_frag_buf_get_wqe(&wq->fbc, ix);
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