!256 intel: backport GNR and SRF intel_idle for 6.6
Merge pull request !256 from jiayingbao/gnr-srf-intel-idle-support-and-fix
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dc68d8b70d
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@ -120,6 +120,12 @@ static unsigned int mwait_substates __initdata;
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*/
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#define CPUIDLE_FLAG_INIT_XSTATE BIT(17)
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/*
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* Ignore the sub-state when matching mwait hints between the ACPI _CST and
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* custom tables.
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*/
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#define CPUIDLE_FLAG_PARTIAL_HINT_MATCH BIT(18)
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/*
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* MWAIT takes an 8-bit "hint" in EAX "suggesting"
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* the C-state (top nibble) and sub-state (bottom nibble)
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@ -993,6 +999,47 @@ static struct cpuidle_state spr_cstates[] __initdata = {
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.enter = NULL }
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};
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static struct cpuidle_state gnr_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 4,
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.target_residency = 4,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |
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CPUIDLE_FLAG_INIT_XSTATE |
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CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
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.exit_latency = 170,
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.target_residency = 650,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6P",
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.desc = "MWAIT 0x21",
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.flags = MWAIT2flg(0x21) | CPUIDLE_FLAG_TLB_FLUSHED |
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CPUIDLE_FLAG_INIT_XSTATE |
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CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
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.exit_latency = 210,
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.target_residency = 1000,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state atom_cstates[] __initdata = {
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{
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.name = "C1E",
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@ -1237,6 +1284,45 @@ static struct cpuidle_state snr_cstates[] __initdata = {
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.enter = NULL }
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};
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static struct cpuidle_state srf_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 2,
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.target_residency = 10,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6S",
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.desc = "MWAIT 0x22",
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.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED |
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CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
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.exit_latency = 270,
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.target_residency = 700,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6SP",
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.desc = "MWAIT 0x23",
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.flags = MWAIT2flg(0x23) | CPUIDLE_FLAG_TLB_FLUSHED |
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CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
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.exit_latency = 310,
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.target_residency = 900,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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static const struct idle_cpu idle_cpu_nehalem __initconst = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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@ -1354,6 +1440,12 @@ static const struct idle_cpu idle_cpu_spr __initconst = {
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_gnr __initconst = {
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.state_table = gnr_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_avn __initconst = {
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.state_table = avn_cstates,
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.disable_promotion_to_c1e = true,
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@ -1382,6 +1474,12 @@ static const struct idle_cpu idle_cpu_snr __initconst = {
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_srf __initconst = {
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.state_table = srf_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
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X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
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@ -1421,12 +1519,14 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &idle_cpu_gmt),
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
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X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &idle_cpu_spr),
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X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &idle_cpu_gnr),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, &idle_cpu_srf),
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{}
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};
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@ -1578,7 +1678,7 @@ static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
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}
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}
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static bool __init intel_idle_off_by_default(u32 mwait_hint)
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static bool __init intel_idle_off_by_default(unsigned int flags, u32 mwait_hint)
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{
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int cstate, limit;
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@ -1595,7 +1695,15 @@ static bool __init intel_idle_off_by_default(u32 mwait_hint)
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* the interesting states are ACPI_CSTATE_FFH.
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*/
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for (cstate = 1; cstate < limit; cstate++) {
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if (acpi_state_table.states[cstate].address == mwait_hint)
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u32 acpi_hint = acpi_state_table.states[cstate].address;
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u32 table_hint = mwait_hint;
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if (flags & CPUIDLE_FLAG_PARTIAL_HINT_MATCH) {
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acpi_hint &= ~MWAIT_SUBSTATE_MASK;
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table_hint &= ~MWAIT_SUBSTATE_MASK;
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}
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if (acpi_hint == table_hint)
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return false;
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}
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return true;
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@ -1605,7 +1713,10 @@ static bool __init intel_idle_off_by_default(u32 mwait_hint)
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static inline bool intel_idle_acpi_cst_extract(void) { return false; }
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static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
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static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
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static inline bool intel_idle_off_by_default(unsigned int flags, u32 mwait_hint)
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{
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return false;
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}
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#endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
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/**
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@ -1929,7 +2040,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
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if ((disabled_states_mask & BIT(drv->state_count)) ||
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((icpu->use_acpi || force_use_acpi) &&
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intel_idle_off_by_default(mwait_hint) &&
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intel_idle_off_by_default(state->flags, mwait_hint) &&
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!(state->flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
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state->flags |= CPUIDLE_FLAG_OFF;
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