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Merge Linus's tree into staging-next 

This was done to resolve the conflicts that were in a number of files
due to changes done upstream with others done in the staging-next
branch.

Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman 2011-06-09 13:49:02 -07:00
parent 461df4ded3 c773298788
commit dc5a18941b
182 changed files with 8982 additions and 16711 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -1533,9 +1533,10 @@ F: drivers/net/tg3.*
BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
M: Brett Rudley <brudley@broadcom.com>
M: Henry Ptasinski <henryp@broadcom.com>
M: Dowan Kim <dowan@broadcom.com>
M: Roland Vossen <rvossen@broadcom.com>
M: Arend van Spriel <arend@broadcom.com>
M: Franky (Zhenhui) Lin <frankyl@broadcom.com>
M: Kan Yan <kanyan@broadcom.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/staging/brcm80211/

2
drivers/staging/brcm80211/Kconfig
View File

@ -7,6 +7,7 @@ config BRCMSMAC
default n
depends on PCI
depends on WLAN && MAC80211
depends on !PPC64 && !PPC32
select BRCMUTIL
select FW_LOADER
select CRC_CCITT
@ -20,6 +21,7 @@ config BRCMFMAC
default n
depends on MMC
depends on WLAN && CFG80211
depends on !PPC64 && !PPC32
select BRCMUTIL
select FW_LOADER
select WIRELESS_EXT

2
drivers/staging/brcm80211/Makefile
View File

@ -19,6 +19,6 @@
subdir-ccflags-y := -DBCMDMA32
subdir-ccflags-$(CONFIG_BRCMDBG) += -DBCMDBG -DBCMDBG_ASSERT
obj-$(CONFIG_BRCMUTIL) += util/
obj-$(CONFIG_BRCMUTIL) += brcmutil/
obj-$(CONFIG_BRCMFMAC) += brcmfmac/
obj-$(CONFIG_BRCMSMAC) += brcmsmac/

65
drivers/staging/brcm80211/README
View File

@ -1,64 +1 @@
Broadcom brcmsmac (mac80211-based softmac PCIe) and brcmfmac (SDIO) drivers.
Completely open source host drivers, no binary object files.
Support for the following chips:
===============================
brcmsmac (PCIe)
Name Device ID
BCM4313 0x4727
BCM43224 0x4353
BCM43225 0x4357
brcmfmac (SDIO)
Name
BCM4329
Both brcmsmac and brcmfmac drivers require firmware files that need to be
separately downloaded.
Firmware
======================
Firmware is available from the Linux firmware repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
http://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
https://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
===============================================================
Broadcom brcmsmac driver
===============================================================
- Support for both 32 and 64 bit Linux kernels
Firmware installation
======================
Copy brcm/bcm43xx-0.fw and brcm/bcm43xx_hdr-0.fw to
/lib/firmware/brcm (or wherever firmware is normally installed
on your system).
===============================================================
Broadcom brcmfmac driver
===============================================================
- Support for 32 bit Linux kernel, 64 bit untested
Firmware installation
======================
Copy brcm/bcm4329-fullmac-4.bin and brcm/bcm4329-fullmac-4.txt
to /lib/firmware/brcm (or wherever firmware is normally installed on your
system).
Contact Info:
=============
Brett Rudley brudley@broadcom.com
Henry Ptasinski henryp@broadcom.com
Dowan Kim dowan@broadcom.com
Roland Vossen rvossen@broadcom.com
Arend van Spriel arend@broadcom.com
For more info, refer to: http://linuxwireless.org/en/users/Drivers/brcm80211
refer to: http://linuxwireless.org/en/users/Drivers/brcm80211

14
drivers/staging/brcm80211/TODO
View File

@ -2,14 +2,22 @@ To Do List for Broadcom Mac80211 driver before getting in mainline
Bugs
====
- Oops on AMPDU traffic, to be solved by new ucode (currently under test)
- none known at this moment
brcmfmac and brcmsmac
=====================
- ASSERTS not allowed in mainline, replace by warning + error handling
- Replace printk and WL_ERROR() with proper routines
- replace company specific acronym wlc_
- Resolve all XXX, TODO, FIXME in code
brcmfmac
=====================
- Remove unnecessary includes, move #includes from .h files into .c files.
- Absorb and delete header files that are included in only one .c file
- ASSERTS not allowed in mainline, replace by warning + error handling
- Replace printk and WL_ERROR() with proper routines
- Replace driver's proprietary ssb interface with generic kernel ssb module
- Build and test on 64 bit linux kernel
brcm80211 info page
=====================
http://linuxwireless.org/en/users/Drivers/brcm80211

98
drivers/staging/brcm80211/brcmfmac/bcmcdc.h
View File

@ -1,98 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/if_ether.h>
typedef struct cdc_ioctl {
u32 cmd; /* ioctl command value */
u32 len; /* lower 16: output buflen; upper 16:
input buflen (excludes header) */
u32 flags; /* flag defns given below */
u32 status; /* status code returned from the device */
} cdc_ioctl_t;
/* Max valid buffer size that can be sent to the dongle */
#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
/* len field is divided into input and output buffer lengths */
#define CDCL_IOC_OUTLEN_MASK 0x0000FFFF /* maximum or expected
response length, */
/* excluding IOCTL header */
#define CDCL_IOC_OUTLEN_SHIFT 0
#define CDCL_IOC_INLEN_MASK 0xFFFF0000 /* input buffer length,
excluding IOCTL header */
#define CDCL_IOC_INLEN_SHIFT 16
/* CDC flag definitions */
#define CDCF_IOC_ERROR 0x01 /* 0=success, 1=ioctl cmd failed */
#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */
#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */
#define CDCF_IOC_IF_SHIFT 12
#define CDCF_IOC_ID_MASK 0xFFFF0000 /* used to uniquely id an ioctl
req/resp pairing */
#define CDCF_IOC_ID_SHIFT 16 /* # of bits of shift for ID Mask */
#define CDC_IOC_IF_IDX(flags) \
(((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)
#define CDC_IOC_ID(flags) \
(((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT)
#define CDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT))
#define CDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | \
((idx) << CDCF_IOC_IF_SHIFT)))
/*
* BDC header
*
* The BDC header is used on data packets to convey priority across USB.
*/
#define BDC_HEADER_LEN 4
#define BDC_PROTO_VER 1 /* Protocol version */
#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
#define BDC_FLAG__UNUSED 0x03 /* Unassigned */
#define BDC_FLAG_SUM_GOOD 0x04 /* Dongle has verified good
RX checksums */
#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
#define BDC_PRIORITY_MASK 0x7
#define BDC_FLAG2_FC_FLAG 0x10 /* flag to indicate if pkt contains */
/* FLOW CONTROL info only */
#define BDC_PRIORITY_FC_SHIFT 4 /* flow control info shift */
#define BDC_FLAG2_IF_MASK 0x0f /* APSTA: interface on which the
packet was received */
#define BDC_FLAG2_IF_SHIFT 0
#define BDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
#define BDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \
((idx) << BDC_FLAG2_IF_SHIFT)))
struct bdc_header {
u8 flags; /* Flags */
u8 priority; /* 802.1d Priority 0:2 bits, 4:7 flow
control info for usb */
u8 flags2;
u8 rssi;
};

6
drivers/staging/brcm80211/brcmfmac/bcmchip.h
View File

@ -17,12 +17,6 @@
#ifndef _bcmchip_h_
#define _bcmchip_h_
/* Core reg address translation */
#define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
#define CORE_BUS_REG(base, field) (base + offsetof(sdpcmd_regs_t, field))
#define CORE_SB(base, field) \
(base + SBCONFIGOFF + offsetof(sbconfig_t, field))
/* bcm4329 */
/* SDIO device core, ID 0x829 */
#define BCM4329_CORE_BUS_BASE 0x18011000

2
drivers/staging/brcm80211/brcmfmac/bcmsdbus.h
View File

@ -17,6 +17,8 @@
#ifndef _sdio_api_h_
#define _sdio_api_h_
#include "sdio_host.h"
#define SDIOH_API_RC_SUCCESS (0x00)
#define SDIOH_API_RC_FAIL (0x01)
#define SDIOH_API_SUCCESS(status) (status == 0)

13
drivers/staging/brcm80211/brcmfmac/bcmsdh.c
View File

@ -18,17 +18,16 @@
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/pci_ids.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <hndsoc.h>
#include <linux/sched.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <soc.h>
#include <bcmsdh.h> /* BRCM API for SDIO
clients (such as wl, dhd) */
#include <bcmsdbus.h> /* common SDIO/controller interface */
#include <sbsdio.h> /* BRCM sdio device core */
#include <sdio.h> /* sdio spec */
#include "dngl_stats.h"
#include "dhd.h"

29
drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
View File

@ -23,17 +23,17 @@
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/completion.h>
#include <linux/sched.h>
#include <pcicfg.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include "sdio_host.h"
#if defined(OOB_INTR_ONLY)
#include <linux/irq.h>
extern void dhdsdio_isr(void *args);
#include <dngl_stats.h>
#include <dhd.h>
#endif /* defined(OOB_INTR_ONLY) */
#if defined(CONFIG_MACH_SANDGATE2G) || defined(CONFIG_MACH_LOGICPD_PXA270)
#if !defined(BCMPLATFORM_BUS)
@ -365,22 +365,5 @@ void bcmsdh_unregister_oob_intr(void)
extern uint sd_msglevel; /* Debug message level */
module_param(sd_msglevel, uint, 0);
extern uint sd_power; /* 0 = SD Power OFF,
1 = SD Power ON. */
module_param(sd_power, uint, 0);
extern uint sd_clock; /* SD Clock Control, 0 = SD Clock OFF,
1 = SD Clock ON */
module_param(sd_clock, uint, 0);
extern uint sd_divisor; /* Divisor (-1 means external clock) */
module_param(sd_divisor, uint, 0);
extern uint sd_sdmode; /* Default is SD4, 0=SPI, 1=SD1, 2=SD4 */
module_param(sd_sdmode, uint, 0);
extern uint sd_hiok; /* Ok to use hi-speed mode */
module_param(sd_hiok, uint, 0);
extern uint sd_f2_blocksize;
module_param(sd_f2_blocksize, int, 0);

196
drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
View File

@ -15,11 +15,12 @@
*/
#include <linux/types.h>
#include <linux/netdevice.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Device and Protocol Specs */
#include <sdioh.h> /* SDIO Host Controller Specification */
#include <linux/mmc/sdio.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include "sdio_host.h"
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* ioctl/iovars */
@ -45,16 +46,9 @@ extern int sdio_reset_comm(struct mmc_card *card);
extern PBCMSDH_SDMMC_INSTANCE gInstance;
uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
uint sd_f2_blocksize = 512; /* Default blocksize */
uint sd_divisor = 2; /* Default 48MHz/2 = 24MHz */
uint sd_power = 1; /* Default to SD Slot powered ON */
uint sd_clock = 1; /* Default to SD Clock turned ON */
uint sd_hiok = false; /* Don't use hi-speed mode by default */
uint sd_msglevel = 0x01;
uint sd_use_dma = true;
DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
@ -81,16 +75,16 @@ static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
sd_trace(("%s\n", __func__));
/* Get the Card's common CIS address */
sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIO_CCCR_CIS);
sd->func_cis_ptr[0] = sd->com_cis_ptr;
sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
sd->com_cis_ptr));
/* Get the Card's function CIS (for each function) */
for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
for (fbraddr = SDIO_FBR_BASE(1), func = 1;
func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
sd->func_cis_ptr[func] =
sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
sdioh_sdmmc_get_cisaddr(sd, SDIO_FBR_CIS + fbraddr);
sd_info(("%s: Function %d CIS Ptr = 0x%x\n", __func__, func,
sd->func_cis_ptr[func]));
}
@ -138,7 +132,6 @@ sdioh_info_t *sdioh_attach(void *bar0, uint irq)
}
sd->num_funcs = 2;
sd->sd_blockmode = true;
sd->use_client_ints = true;
sd->client_block_size[0] = 64;
@ -352,46 +345,22 @@ uint sdioh_query_iofnum(sdioh_info_t *sd)
/* IOVar table */
enum {
IOV_MSGLEVEL = 1,
IOV_BLOCKMODE,
IOV_BLOCKSIZE,
IOV_DMA,
IOV_USEINTS,
IOV_NUMINTS,
IOV_NUMLOCALINTS,
IOV_HOSTREG,
IOV_DEVREG,
IOV_DIVISOR,
IOV_SDMODE,
IOV_HISPEED,
IOV_HCIREGS,
IOV_POWER,
IOV_CLOCK,
IOV_RXCHAIN
};
const bcm_iovar_t sdioh_iovars[] = {
const struct brcmu_iovar sdioh_iovars[] = {
{"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0},
{"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0},
{"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0},/* ((fn << 16) |
size) */
{"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0},
{"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0},
{"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0},
{"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0},
{"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
,
{"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
,
{"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0}
,
{"sd_power", IOV_POWER, 0, IOVT_UINT32, 0}
,
{"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0}
,
{"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100}
,
{"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0}
,
{"sd_rxchain", IOV_RXCHAIN, 0, IOVT_BOOL, 0}
,
{NULL, 0, 0, 0, 0}
@ -401,7 +370,7 @@ int
sdioh_iovar_op(sdioh_info_t *si, const char *name,
void *params, int plen, void *arg, int len, bool set)
{
const bcm_iovar_t *vi = NULL;
const struct brcmu_iovar *vi = NULL;
int bcmerror = 0;
int val_size;
s32 int_val = 0;
@ -418,13 +387,13 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
sd_trace(("%s: Enter (%s %s)\n", __func__, (set ? "set" : "get"),
name));
vi = bcm_iovar_lookup(sdioh_iovars, name);
vi = brcmu_iovar_lookup(sdioh_iovars, name);
if (vi == NULL) {
bcmerror = -ENOTSUPP;
goto exit;
}
bcmerror = bcm_iovar_lencheck(vi, arg, len, set);
bcmerror = brcmu_iovar_lencheck(vi, arg, len, set);
if (bcmerror != 0)
goto exit;
@ -457,16 +426,6 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
sd_msglevel = int_val;
break;
case IOV_GVAL(IOV_BLOCKMODE):
int_val = (s32) si->sd_blockmode;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_BLOCKMODE):
si->sd_blockmode = (bool) int_val;
/* Haven't figured out how to make non-block mode with DMA */
break;
case IOV_GVAL(IOV_BLOCKSIZE):
if ((u32) int_val > si->num_funcs) {
bcmerror = -EINVAL;
@ -518,15 +477,6 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
memcpy(arg, &int_val, val_size);
break;
case IOV_GVAL(IOV_DMA):
int_val = (s32) si->sd_use_dma;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_DMA):
si->sd_use_dma = (bool) int_val;
break;
case IOV_GVAL(IOV_USEINTS):
int_val = (s32) si->use_client_ints;
memcpy(arg, &int_val, val_size);
@ -541,111 +491,11 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break;
case IOV_GVAL(IOV_DIVISOR):
int_val = (u32) sd_divisor;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_DIVISOR):
sd_divisor = int_val;
break;
case IOV_GVAL(IOV_POWER):
int_val = (u32) sd_power;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_POWER):
sd_power = int_val;
break;
case IOV_GVAL(IOV_CLOCK):
int_val = (u32) sd_clock;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_CLOCK):
sd_clock = int_val;
break;
case IOV_GVAL(IOV_SDMODE):
int_val = (u32) sd_sdmode;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_SDMODE):
sd_sdmode = int_val;
break;
case IOV_GVAL(IOV_HISPEED):
int_val = (u32) sd_hiok;
memcpy(arg, &int_val, val_size);
break;
case IOV_SVAL(IOV_HISPEED):
sd_hiok = int_val;
break;
case IOV_GVAL(IOV_NUMINTS):
int_val = (s32) si->intrcount;
memcpy(arg, &int_val, val_size);
break;
case IOV_GVAL(IOV_NUMLOCALINTS):
int_val = (s32) 0;
memcpy(arg, &int_val, val_size);
break;
case IOV_GVAL(IOV_HOSTREG):
{
sdreg_t *sd_ptr = (sdreg_t *) params;
if (sd_ptr->offset < SD_SysAddr
|| sd_ptr->offset > SD_MaxCurCap) {
sd_err(("%s: bad offset 0x%x\n", __func__,
sd_ptr->offset));
bcmerror = -EINVAL;
break;
}
sd_trace(("%s: rreg%d at offset %d\n", __func__,
(sd_ptr->offset & 1) ? 8
: ((sd_ptr->offset & 2) ? 16 : 32),
sd_ptr->offset));
if (sd_ptr->offset & 1)
int_val = 8; /* sdioh_sdmmc_rreg8(si,
sd_ptr->offset); */
else if (sd_ptr->offset & 2)
int_val = 16; /* sdioh_sdmmc_rreg16(si,
sd_ptr->offset); */
else
int_val = 32; /* sdioh_sdmmc_rreg(si,
sd_ptr->offset); */
memcpy(arg, &int_val, sizeof(int_val));
break;
}
case IOV_SVAL(IOV_HOSTREG):
{
sdreg_t *sd_ptr = (sdreg_t *) params;
if (sd_ptr->offset < SD_SysAddr
|| sd_ptr->offset > SD_MaxCurCap) {
sd_err(("%s: bad offset 0x%x\n", __func__,
sd_ptr->offset));
bcmerror = -EINVAL;
break;
}
sd_trace(("%s: wreg%d value 0x%08x at offset %d\n",
__func__, sd_ptr->value,
(sd_ptr->offset & 1) ? 8
: ((sd_ptr->offset & 2) ? 16 : 32),
sd_ptr->offset));
break;
}
case IOV_GVAL(IOV_DEVREG):
{
sdreg_t *sd_ptr = (sdreg_t *) params;
@ -792,7 +642,7 @@ sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
* Handle F2 enable
* as a special case.
*/
if (regaddr == SDIOD_CCCR_IOEN) {
if (regaddr == SDIO_CCCR_IOEx) {
if (gInstance->func[2]) {
sdio_claim_host(gInstance->func[2]);
if (*byte & SDIO_FUNC_ENABLE_2) {
@ -817,7 +667,7 @@ sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
}
#if defined(MMC_SDIO_ABORT)
/* to allow abort command through F1 */
else if (regaddr == SDIOD_CCCR_IOABORT) {
else if (regaddr == SDIO_CCCR_ABORT) {
sdio_claim_host(gInstance->func[func]);
/*
* this sdio_f0_writeb() can be replaced
@ -1039,9 +889,9 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
if (pkt == NULL) {
sd_data(("%s: Creating new %s Packet, len=%d\n",
__func__, write ? "TX" : "RX", buflen_u));
mypkt = bcm_pkt_buf_get_skb(buflen_u);
mypkt = brcmu_pkt_buf_get_skb(buflen_u);
if (!mypkt) {
sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
sd_err(("%s: brcmu_pkt_buf_get_skb failed: len %d\n",
__func__, buflen_u));
return SDIOH_API_RC_FAIL;
}
@ -1057,7 +907,7 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
if (!write)
memcpy(buffer, mypkt->data, buflen_u);
bcm_pkt_buf_free_skb(mypkt);
brcmu_pkt_buf_free_skb(mypkt);
} else if (((u32) (pkt->data) & DMA_ALIGN_MASK) != 0) {
/* Case 2: We have a packet, but it is unaligned. */
@ -1066,9 +916,9 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
sd_data(("%s: Creating aligned %s Packet, len=%d\n",
__func__, write ? "TX" : "RX", pkt->len));
mypkt = bcm_pkt_buf_get_skb(pkt->len);
mypkt = brcmu_pkt_buf_get_skb(pkt->len);
if (!mypkt) {
sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
sd_err(("%s: brcmu_pkt_buf_get_skb failed: len %d\n",
__func__, pkt->len));
return SDIOH_API_RC_FAIL;
}
@ -1084,7 +934,7 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
if (!write)
memcpy(pkt->data, mypkt->data, mypkt->len);
bcm_pkt_buf_free_skb(mypkt);
brcmu_pkt_buf_free_skb(mypkt);
} else { /* case 3: We have a packet and
it is aligned. */
sd_data(("%s: Aligned %s Packet, direct DMA\n",
@ -1105,8 +955,8 @@ extern int sdioh_abort(sdioh_info_t *sd, uint func)
sd_trace(("%s: Enter\n", __func__));
#if defined(MMC_SDIO_ABORT)
/* issue abort cmd52 command through F1 */
sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT,
/* issue abort cmd52 command through F0 */
sdioh_request_byte(sd, SDIOH_WRITE, SDIO_FUNC_0, SDIO_CCCR_ABORT,
&t_func);
#endif /* defined(MMC_SDIO_ABORT) */

2
drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.h
View File

@ -85,11 +85,9 @@ struct sdioh_info {
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == false => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
u8 num_funcs; /* Supported funcs on client */
u32 com_cis_ptr;

8
drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc_linux.c
View File

@ -16,9 +16,11 @@
#include <linux/types.h>
#include <linux/sched.h> /* request_irq() */
#include <linux/netdevice.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <sdio.h> /* SDIO Specs */
#include <net/cfg80211.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include "sdio_host.h"
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */

920
drivers/staging/brcm80211/brcmfmac/dhd.h
View File

@ -21,28 +21,348 @@
#ifndef _dhd_h_
#define _dhd_h_
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/random.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
#include <linux/suspend.h>
#include <asm/uaccess.h>
#include <asm/unaligned.h>
/* The kernel threading is sdio-specific */
#include <wlioctl.h>
/* Forward decls */
struct dhd_bus;
struct dhd_prot;
struct dhd_info;
#define WLC_UP 2
#define WLC_SET_PROMISC 10
#define WLC_GET_RATE 12
#define WLC_GET_INFRA 19
#define WLC_SET_INFRA 20
#define WLC_GET_AUTH 21
#define WLC_SET_AUTH 22
#define WLC_GET_BSSID 23
#define WLC_GET_SSID 25
#define WLC_SET_SSID 26
#define WLC_GET_CHANNEL 29
#define WLC_GET_SRL 31
#define WLC_GET_LRL 33
#define WLC_GET_RADIO 37
#define WLC_SET_RADIO 38
#define WLC_GET_PHYTYPE 39
#define WLC_SET_KEY 45
#define WLC_SET_PASSIVE_SCAN 49
#define WLC_SCAN 50
#define WLC_SCAN_RESULTS 51
#define WLC_DISASSOC 52
#define WLC_REASSOC 53
#define WLC_SET_ROAM_TRIGGER 55
#define WLC_SET_ROAM_DELTA 57
#define WLC_GET_DTIMPRD 77
#define WLC_SET_COUNTRY 84
#define WLC_GET_PM 85
#define WLC_SET_PM 86
#define WLC_GET_AP 117
#define WLC_SET_AP 118
#define WLC_GET_RSSI 127
#define WLC_GET_WSEC 133
#define WLC_SET_WSEC 134
#define WLC_GET_PHY_NOISE 135
#define WLC_GET_BSS_INFO 136
#define WLC_SET_SCAN_CHANNEL_TIME 185
#define WLC_SET_SCAN_UNASSOC_TIME 187
#define WLC_SCB_DEAUTHENTICATE_FOR_REASON 201
#define WLC_GET_VALID_CHANNELS 217
#define WLC_GET_KEY_PRIMARY 235
#define WLC_SET_KEY_PRIMARY 236
#define WLC_SET_SCAN_PASSIVE_TIME 258
#define WLC_GET_VAR 262 /* get value of named variable */
#define WLC_SET_VAR 263 /* set named variable to value */
/* phy types (returned by WLC_GET_PHYTPE) */
#define WLC_PHY_TYPE_A 0
#define WLC_PHY_TYPE_B 1
#define WLC_PHY_TYPE_G 2
#define WLC_PHY_TYPE_N 4
#define WLC_PHY_TYPE_LP 5
#define WLC_PHY_TYPE_SSN 6
#define WLC_PHY_TYPE_HT 7
#define WLC_PHY_TYPE_LCN 8
#define WLC_PHY_TYPE_NULL 0xf
#define WL_PKT_FILTER_FIXED_LEN offsetof(wl_pkt_filter_t, u)
#define WL_PKT_FILTER_PATTERN_FIXED_LEN offsetof(wl_pkt_filter_pattern_t, mask_and_pattern)
#define WL_EVENTING_MASK_LEN 16
#define TOE_TX_CSUM_OL 0x00000001
#define TOE_RX_CSUM_OL 0x00000002
/* maximum channels returned by the get valid channels iovar */
#define WL_NUMCHANNELS 64
#define WL_BSS_INFO_VERSION 108 /* current ver of wl_bss_info struct */
/* size of wl_scan_params not including variable length array */
#define WL_SCAN_PARAMS_FIXED_SIZE 64
/* masks for channel and ssid count */
#define WL_SCAN_PARAMS_COUNT_MASK 0x0000ffff
#define WL_SCAN_PARAMS_NSSID_SHIFT 16
#define WL_SCAN_ACTION_START 1
#define WL_SCAN_ACTION_CONTINUE 2
#define WL_SCAN_ACTION_ABORT 3
#define ISCAN_REQ_VERSION 1
/* wl_iscan_results status values */
#define WL_SCAN_RESULTS_SUCCESS 0
#define WL_SCAN_RESULTS_PARTIAL 1
#define WL_SCAN_RESULTS_PENDING 2
#define WL_SCAN_RESULTS_ABORTED 3
#define WL_SCAN_RESULTS_NO_MEM 4
#define MAX_CCA_CHANNELS 38 /* Max number of 20 Mhz wide channels */
#define MAX_CCA_SECS 60 /* CCA keeps this many seconds history */
#define IBSS_MED 15 /* Mediom in-bss congestion percentage */
#define IBSS_HI 25 /* Hi in-bss congestion percentage */
#define OBSS_MED 12
#define OBSS_HI 25
#define INTERFER_MED 5
#define INTERFER_HI 10
#define CCA_FLAG_2G_ONLY 0x01 /* Return a channel from 2.4 Ghz band */
#define CCA_FLAG_5G_ONLY 0x02 /* Return a channel from 2.4 Ghz band */
#define CCA_FLAG_IGNORE_DURATION 0x04 /* Ignore dwell time for each channel */
#define CCA_FLAGS_PREFER_1_6_11 0x10
#define CCA_FLAG_IGNORE_INTERFER 0x20 /* do not exlude channel based on interfer level */
#define CCA_ERRNO_BAND 1 /* After filtering for band pref, no choices left */
#define CCA_ERRNO_DURATION 2 /* After filtering for duration, no choices left */
#define CCA_ERRNO_PREF_CHAN 3 /* After filtering for chan pref, no choices left */
#define CCA_ERRNO_INTERFER 4 /* After filtering for interference, no choices left */
#define CCA_ERRNO_TOO_FEW 5 /* Only 1 channel was input */
#define WL_NUM_RPI_BINS 8
#define WL_RM_TYPE_BASIC 1
#define WL_RM_TYPE_CCA 2
#define WL_RM_TYPE_RPI 3
#define WL_RM_FLAG_PARALLEL (1<<0)
#define WL_RM_FLAG_LATE (1<<1)
#define WL_RM_FLAG_INCAPABLE (1<<2)
#define WL_RM_FLAG_REFUSED (1<<3)
#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
#define WL_IBSS_PEER_GROUP_KEY (1 << 6) /* Indicates a group key for a IBSS PEER */
#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
#define WLC_IOCTL_MEDLEN 1536 /* "med" length ioctl buffer required */
#define WLC_IOCTL_MAXLEN 8192
#define DHD_IF_VIF 0x01 /* Virtual IF (Hidden from user) */
/* optionally set by a module_param_string() */
#define MOD_PARAM_PATHLEN 2048
/* For supporting multiple interfaces */
#define DHD_MAX_IFS 16
#define DHD_DEL_IF -0xe
#define DHD_BAD_IF -0xf
#define DOT11_BSSTYPE_ANY 2
#define DOT11_MAX_DEFAULT_KEYS 4
#define BCM_EVENT_MSG_VERSION 1
#define BCM_MSG_IFNAME_MAX 16
#define WLC_EVENT_MSG_LINK 0x01
#define WLC_EVENT_MSG_FLUSHTXQ 0x02
#define WLC_EVENT_MSG_GROUP 0x04
typedef struct {
u16 version;
u16 flags;
u32 event_type;
u32 status;
u32 reason;
u32 auth_type;
u32 datalen;
u8 addr[ETH_ALEN];
char ifname[BCM_MSG_IFNAME_MAX];
} __attribute__((packed)) wl_event_msg_t;
typedef struct bcmeth_hdr {
u16 subtype;
u16 length;
u8 version;
u8 oui[3];
u16 usr_subtype;
} __attribute__((packed)) bcmeth_hdr_t;
#ifdef BRCM_FULLMAC
typedef struct bcm_event {
struct ethhdr eth;
bcmeth_hdr_t bcm_hdr;
wl_event_msg_t event;
} __attribute__((packed)) bcm_event_t;
#endif
#define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - \
sizeof(struct ether_header))
#define WLC_E_SET_SSID 0
#define WLC_E_JOIN 1
#define WLC_E_START 2
#define WLC_E_AUTH 3
#define WLC_E_AUTH_IND 4
#define WLC_E_DEAUTH 5
#define WLC_E_DEAUTH_IND 6
#define WLC_E_ASSOC 7
#define WLC_E_ASSOC_IND 8
#define WLC_E_REASSOC 9
#define WLC_E_REASSOC_IND 10
#define WLC_E_DISASSOC 11
#define WLC_E_DISASSOC_IND 12
#define WLC_E_QUIET_START 13
#define WLC_E_QUIET_END 14
#define WLC_E_BEACON_RX 15
#define WLC_E_LINK 16
#define WLC_E_MIC_ERROR 17
#define WLC_E_NDIS_LINK 18
#define WLC_E_ROAM 19
#define WLC_E_TXFAIL 20
#define WLC_E_PMKID_CACHE 21
#define WLC_E_RETROGRADE_TSF 22
#define WLC_E_PRUNE 23
#define WLC_E_AUTOAUTH 24
#define WLC_E_EAPOL_MSG 25
#define WLC_E_SCAN_COMPLETE 26
#define WLC_E_ADDTS_IND 27
#define WLC_E_DELTS_IND 28
#define WLC_E_BCNSENT_IND 29
#define WLC_E_BCNRX_MSG 30
#define WLC_E_BCNLOST_MSG 31
#define WLC_E_ROAM_PREP 32
#define WLC_E_PFN_NET_FOUND 33
#define WLC_E_PFN_NET_LOST 34
#define WLC_E_RESET_COMPLETE 35
#define WLC_E_JOIN_START 36
#define WLC_E_ROAM_START 37
#define WLC_E_ASSOC_START 38
#define WLC_E_IBSS_ASSOC 39
#define WLC_E_RADIO 40
#define WLC_E_PSM_WATCHDOG 41
#define WLC_E_PROBREQ_MSG 44
#define WLC_E_SCAN_CONFIRM_IND 45
#define WLC_E_PSK_SUP 46
#define WLC_E_COUNTRY_CODE_CHANGED 47
#define WLC_E_EXCEEDED_MEDIUM_TIME 48
#define WLC_E_ICV_ERROR 49
#define WLC_E_UNICAST_DECODE_ERROR 50
#define WLC_E_MULTICAST_DECODE_ERROR 51
#define WLC_E_TRACE 52
#define WLC_E_IF 54
#define WLC_E_RSSI 56
#define WLC_E_PFN_SCAN_COMPLETE 57
#define WLC_E_EXTLOG_MSG 58
#define WLC_E_ACTION_FRAME 59
#define WLC_E_ACTION_FRAME_COMPLETE 60
#define WLC_E_PRE_ASSOC_IND 61
#define WLC_E_PRE_REASSOC_IND 62
#define WLC_E_CHANNEL_ADOPTED 63
#define WLC_E_AP_STARTED 64
#define WLC_E_DFS_AP_STOP 65
#define WLC_E_DFS_AP_RESUME 66
#define WLC_E_RESERVED1 67
#define WLC_E_RESERVED2 68
#define WLC_E_ESCAN_RESULT 69
#define WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE 70
#define WLC_E_DCS_REQUEST 73
#define WLC_E_FIFO_CREDIT_MAP 74
#define WLC_E_LAST 75
#define WLC_E_STATUS_SUCCESS 0
#define WLC_E_STATUS_FAIL 1
#define WLC_E_STATUS_TIMEOUT 2
#define WLC_E_STATUS_NO_NETWORKS 3
#define WLC_E_STATUS_ABORT 4
#define WLC_E_STATUS_NO_ACK 5
#define WLC_E_STATUS_UNSOLICITED 6
#define WLC_E_STATUS_ATTEMPT 7
#define WLC_E_STATUS_PARTIAL 8
#define WLC_E_STATUS_NEWSCAN 9
#define WLC_E_STATUS_NEWASSOC 10
#define WLC_E_STATUS_11HQUIET 11
#define WLC_E_STATUS_SUPPRESS 12
#define WLC_E_STATUS_NOCHANS 13
#define WLC_E_STATUS_CS_ABORT 15
#define WLC_E_STATUS_ERROR 16
#define WLC_E_REASON_INITIAL_ASSOC 0
#define WLC_E_REASON_LOW_RSSI 1
#define WLC_E_REASON_DEAUTH 2
#define WLC_E_REASON_DISASSOC 3
#define WLC_E_REASON_BCNS_LOST 4
#define WLC_E_REASON_MINTXRATE 9
#define WLC_E_REASON_TXFAIL 10
#define WLC_E_REASON_FAST_ROAM_FAILED 5
#define WLC_E_REASON_DIRECTED_ROAM 6
#define WLC_E_REASON_TSPEC_REJECTED 7
#define WLC_E_REASON_BETTER_AP 8
#define WLC_E_PRUNE_ENCR_MISMATCH 1
#define WLC_E_PRUNE_BCAST_BSSID 2
#define WLC_E_PRUNE_MAC_DENY 3
#define WLC_E_PRUNE_MAC_NA 4
#define WLC_E_PRUNE_REG_PASSV 5
#define WLC_E_PRUNE_SPCT_MGMT 6
#define WLC_E_PRUNE_RADAR 7
#define WLC_E_RSN_MISMATCH 8
#define WLC_E_PRUNE_NO_COMMON_RATES 9
#define WLC_E_PRUNE_BASIC_RATES 10
#define WLC_E_PRUNE_CIPHER_NA 12
#define WLC_E_PRUNE_KNOWN_STA 13
#define WLC_E_PRUNE_WDS_PEER 15
#define WLC_E_PRUNE_QBSS_LOAD 16
#define WLC_E_PRUNE_HOME_AP 17
#define WLC_E_SUP_OTHER 0
#define WLC_E_SUP_DECRYPT_KEY_DATA 1
#define WLC_E_SUP_BAD_UCAST_WEP128 2
#define WLC_E_SUP_BAD_UCAST_WEP40 3
#define WLC_E_SUP_UNSUP_KEY_LEN 4
#define WLC_E_SUP_PW_KEY_CIPHER 5
#define WLC_E_SUP_MSG3_TOO_MANY_IE 6
#define WLC_E_SUP_MSG3_IE_MISMATCH 7
#define WLC_E_SUP_NO_INSTALL_FLAG 8
#define WLC_E_SUP_MSG3_NO_GTK 9
#define WLC_E_SUP_GRP_KEY_CIPHER 10
#define WLC_E_SUP_GRP_MSG1_NO_GTK 11
#define WLC_E_SUP_GTK_DECRYPT_FAIL 12
#define WLC_E_SUP_SEND_FAIL 13
#define WLC_E_SUP_DEAUTH 14
#define WLC_E_IF_ADD 1
#define WLC_E_IF_DEL 2
#define WLC_E_IF_CHANGE 3
#define WLC_E_IF_ROLE_STA 0
#define WLC_E_IF_ROLE_AP 1
#define WLC_E_IF_ROLE_WDS 2
#define WLC_E_LINK_BCN_LOSS 1
#define WLC_E_LINK_DISASSOC 2
#define WLC_E_LINK_ASSOC_REC 3
#define WLC_E_LINK_BSSCFG_DIS 4
enum cust_gpio_modes {
WLAN_RESET_ON,
WLAN_RESET_OFF,
WLAN_POWER_ON,
WLAN_POWER_OFF
};
/* The level of bus communication with the dongle */
enum dhd_bus_state {
DHD_BUS_DOWN, /* Not ready for frame transfers */
@ -50,6 +370,316 @@ enum dhd_bus_state {
DHD_BUS_DATA /* Ready for frame transfers */
};
/* Pattern matching filter. Specifies an offset within received packets to
* start matching, the pattern to match, the size of the pattern, and a bitmask
* that indicates which bits within the pattern should be matched.
*/
typedef struct wl_pkt_filter_pattern {
u32 offset; /* Offset within received packet to start pattern matching.
* Offset '0' is the first byte of the ethernet header.
*/
u32 size_bytes; /* Size of the pattern. Bitmask must be the same size. */
u8 mask_and_pattern[1]; /* Variable length mask and pattern data. mask starts
* at offset 0. Pattern immediately follows mask.
*/
} wl_pkt_filter_pattern_t;
/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
typedef struct wl_pkt_filter {
u32 id; /* Unique filter id, specified by app. */
u32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */
u32 negate_match; /* Negate the result of filter matches */
union { /* Filter definitions */
wl_pkt_filter_pattern_t pattern; /* Pattern matching filter */
} u;
} wl_pkt_filter_t;
/* IOVAR "pkt_filter_enable" parameter. */
typedef struct wl_pkt_filter_enable {
u32 id; /* Unique filter id */
u32 enable; /* Enable/disable bool */
} wl_pkt_filter_enable_t;
/* BSS info structure
* Applications MUST CHECK ie_offset field and length field to access IEs and
* next bss_info structure in a vector (in wl_scan_results_t)
*/
typedef struct wl_bss_info {
u32 version; /* version field */
u32 length; /* byte length of data in this record,
* starting at version and including IEs
*/
u8 BSSID[ETH_ALEN];
u16 beacon_period; /* units are Kusec */
u16 capability; /* Capability information */
u8 SSID_len;
u8 SSID[32];
struct {
uint count; /* # rates in this set */
u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
} rateset; /* supported rates */
chanspec_t chanspec; /* chanspec for bss */
u16 atim_window; /* units are Kusec */
u8 dtim_period; /* DTIM period */
s16 RSSI; /* receive signal strength (in dBm) */
s8 phy_noise; /* noise (in dBm) */
u8 n_cap; /* BSS is 802.11N Capable */
u32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */
u8 ctl_ch; /* 802.11N BSS control channel number */
u32 reserved32[1]; /* Reserved for expansion of BSS properties */
u8 flags; /* flags */
u8 reserved[3]; /* Reserved for expansion of BSS properties */
u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
u16 ie_offset; /* offset at which IEs start, from beginning */
u32 ie_length; /* byte length of Information Elements */
s16 SNR; /* average SNR of during frame reception */
/* Add new fields here */
/* variable length Information Elements */
} wl_bss_info_t;
typedef struct wlc_ssid {
u32 SSID_len;
unsigned char SSID[32];
} wlc_ssid_t;
typedef struct wl_scan_params {
wlc_ssid_t ssid; /* default: {0, ""} */
u8 bssid[ETH_ALEN]; /* default: bcast */
s8 bss_type; /* default: any,
* DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT
*/
u8 scan_type; /* flags, 0 use default */
s32 nprobes; /* -1 use default, number of probes per channel */
s32 active_time; /* -1 use default, dwell time per channel for
* active scanning
*/
s32 passive_time; /* -1 use default, dwell time per channel
* for passive scanning
*/
s32 home_time; /* -1 use default, dwell time for the home channel
* between channel scans
*/
s32 channel_num; /* count of channels and ssids that follow
*
* low half is count of channels in channel_list, 0
* means default (use all available channels)
*
* high half is entries in wlc_ssid_t array that
* follows channel_list, aligned for s32 (4 bytes)
* meaning an odd channel count implies a 2-byte pad
* between end of channel_list and first ssid
*
* if ssid count is zero, single ssid in the fixed
* parameter portion is assumed, otherwise ssid in
* the fixed portion is ignored
*/
u16 channel_list[1]; /* list of chanspecs */
} wl_scan_params_t;
/* incremental scan struct */
typedef struct wl_iscan_params {
u32 version;
u16 action;
u16 scan_duration;
wl_scan_params_t params;
} wl_iscan_params_t;
/* 3 fields + size of wl_scan_params, not including variable length array */
#define WL_ISCAN_PARAMS_FIXED_SIZE (offsetof(wl_iscan_params_t, params) + sizeof(wlc_ssid_t))
typedef struct wl_scan_results {
u32 buflen;
u32 version;
u32 count;
wl_bss_info_t bss_info[1];
} wl_scan_results_t;
typedef struct wl_rateset_args {
u32 count; /* # rates in this set */
u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */
} wl_rateset_args_t;
/* u32 list */
typedef struct wl_u32_list {
/* in - # of elements, out - # of entries */
u32 count;
/* variable length u32 list */
u32 element[1];
} wl_u32_list_t;
/* used for association with a specific BSSID and chanspec list */
typedef struct wl_assoc_params {
u8 bssid[ETH_ALEN]; /* 00:00:00:00:00:00: broadcast scan */
s32 chanspec_num; /* 0: all available channels,
* otherwise count of chanspecs in chanspec_list
*/
chanspec_t chanspec_list[1]; /* list of chanspecs */
} wl_assoc_params_t;
#define WL_ASSOC_PARAMS_FIXED_SIZE (sizeof(wl_assoc_params_t) - sizeof(chanspec_t))
/* used for reassociation/roam to a specific BSSID and channel */
typedef wl_assoc_params_t wl_reassoc_params_t;
#define WL_REASSOC_PARAMS_FIXED_SIZE WL_ASSOC_PARAMS_FIXED_SIZE
/* used for join with or without a specific bssid and channel list */
typedef struct wl_join_params {
wlc_ssid_t ssid;
wl_assoc_params_t params; /* optional field, but it must include the fixed portion
* of the wl_assoc_params_t struct when it does present.
*/
} wl_join_params_t;
#define WL_JOIN_PARAMS_FIXED_SIZE (sizeof(wl_join_params_t) - sizeof(chanspec_t))
/* size of wl_scan_results not including variable length array */
#define WL_SCAN_RESULTS_FIXED_SIZE (sizeof(wl_scan_results_t) - sizeof(wl_bss_info_t))
/* incremental scan results struct */
typedef struct wl_iscan_results {
u32 status;
wl_scan_results_t results;
} wl_iscan_results_t;
/* size of wl_iscan_results not including variable length array */
#define WL_ISCAN_RESULTS_FIXED_SIZE \
(WL_SCAN_RESULTS_FIXED_SIZE + offsetof(wl_iscan_results_t, results))
typedef struct {
u32 duration; /* millisecs spent sampling this channel */
u32 congest_ibss; /* millisecs in our bss (presumably this traffic will */
/* move if cur bss moves channels) */
u32 congest_obss; /* traffic not in our bss */
u32 interference; /* millisecs detecting a non 802.11 interferer. */
u32 timestamp; /* second timestamp */
} cca_congest_t;
typedef struct {
chanspec_t chanspec; /* Which channel? */
u8 num_secs; /* How many secs worth of data */
cca_congest_t secs[1]; /* Data */
} cca_congest_channel_req_t;
typedef struct wl_country {
char country_abbrev[WLC_CNTRY_BUF_SZ]; /* nul-terminated country code used in
* the Country IE
*/
s32 rev; /* revision specifier for ccode
* on set, -1 indicates unspecified.
* on get, rev >= 0
*/
char ccode[WLC_CNTRY_BUF_SZ]; /* nul-terminated built-in country code.
* variable length, but fixed size in
* struct allows simple allocation for
* expected country strings <= 3 chars.
*/
} wl_country_t;
typedef struct wl_channels_in_country {
u32 buflen;
u32 band;
char country_abbrev[WLC_CNTRY_BUF_SZ];
u32 count;
u32 channel[1];
} wl_channels_in_country_t;
typedef struct wl_country_list {
u32 buflen;
u32 band_set;
u32 band;
u32 count;
char country_abbrev[1];
} wl_country_list_t;
typedef struct wl_rm_req_elt {
s8 type;
s8 flags;
chanspec_t chanspec;
u32 token; /* token for this measurement */
u32 tsf_h; /* TSF high 32-bits of Measurement start time */
u32 tsf_l; /* TSF low 32-bits */
u32 dur; /* TUs */
} wl_rm_req_elt_t;
typedef struct wl_rm_req {
u32 token; /* overall measurement set token */
u32 count; /* number of measurement requests */
void *cb; /* completion callback function: may be NULL */
void *cb_arg; /* arg to completion callback function */
wl_rm_req_elt_t req[1]; /* variable length block of requests */
} wl_rm_req_t;
#define WL_RM_REQ_FIXED_LEN offsetof(wl_rm_req_t, req)
typedef struct wl_rm_rep_elt {
s8 type;
s8 flags;
chanspec_t chanspec;
u32 token; /* token for this measurement */
u32 tsf_h; /* TSF high 32-bits of Measurement start time */
u32 tsf_l; /* TSF low 32-bits */
u32 dur; /* TUs */
u32 len; /* byte length of data block */
u8 data[1]; /* variable length data block */
} wl_rm_rep_elt_t;
#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
#define WL_RPI_REP_BIN_NUM 8
typedef struct wl_rm_rpi_rep {
u8 rpi[WL_RPI_REP_BIN_NUM];
s8 rpi_max[WL_RPI_REP_BIN_NUM];
} wl_rm_rpi_rep_t;
typedef struct wl_rm_rep {
u32 token; /* overall measurement set token */
u32 len; /* length of measurement report block */
wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
} wl_rm_rep_t;
#define WL_RM_REP_FIXED_LEN 8
typedef struct wl_wsec_key {
u32 index; /* key index */
u32 len; /* key length */
u8 data[WLAN_MAX_KEY_LEN]; /* key data */
u32 pad_1[18];
u32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
u32 flags; /* misc flags */
u32 pad_2[2];
int pad_3;
int iv_initialized; /* has IV been initialized already? */
int pad_4;
/* Rx IV */
struct {
u32 hi; /* upper 32 bits of IV */
u16 lo; /* lower 16 bits of IV */
} rxiv;
u32 pad_5[2];
u8 ea[ETH_ALEN]; /* per station */
} wl_wsec_key_t;
/* Used to get specific STA parameters */
typedef struct {
u32 val;
u8 ea[ETH_ALEN];
} scb_val_t;
/* channel encoding */
typedef struct channel_info {
int hw_channel;
int target_channel;
int scan_channel;
} channel_info_t;
/* Linux network driver ioctl encoding */
typedef struct wl_ioctl {
uint cmd; /* common ioctl definition */
void *buf; /* pointer to user buffer */
uint len; /* length of user buffer */
u8 set; /* get or set request (optional) */
uint used; /* bytes read or written (optional) */
uint needed; /* bytes needed (optional) */
} wl_ioctl_t;
/* Common structure for module and instance linkage */
typedef struct dhd_pub {
/* Linkage ponters */
@ -122,6 +752,25 @@ typedef struct dhd_pub {
} dhd_pub_t;
typedef struct dhd_if_event {
u8 ifidx;
u8 action;
u8 flags;
u8 bssidx;
} dhd_if_event_t;
typedef struct {
u32 limit; /* Expiration time (usec) */
u32 increment; /* Current expiration increment (usec) */
u32 elapsed; /* Current elapsed time (usec) */
u32 tick; /* O/S tick time (usec) */
} dhd_timeout_t;
typedef struct {
uint event;
const char *name;
} bcmevent_name_t;
#if defined(CONFIG_PM_SLEEP)
extern atomic_t dhd_mmc_suspend;
#define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
@ -167,7 +816,72 @@ extern atomic_t dhd_mmc_suspend;
} while (0)
#endif /* defined(CONFIG_PM_SLEEP) */
#define DHD_IF_VIF 0x01 /* Virtual IF (Hidden from user) */
/*
* Insmod parameters for debug/test
*/
/* Watchdog timer interval */
extern uint dhd_watchdog_ms;
#if defined(DHD_DEBUG)
/* Console output poll interval */
extern uint dhd_console_ms;
#endif /* defined(DHD_DEBUG) */
/* Use interrupts */
extern uint dhd_intr;
/* Use polling */
extern uint dhd_poll;
/* ARP offload agent mode */
extern uint dhd_arp_mode;
/* ARP offload enable */
extern uint dhd_arp_enable;
/* Pkt filte enable control */
extern uint dhd_pkt_filter_enable;
/* Pkt filter init setup */
extern uint dhd_pkt_filter_init;
/* Pkt filter mode control */
extern uint dhd_master_mode;
/* Roaming mode control */
extern uint dhd_roam;
/* Roaming mode control */
extern uint dhd_radio_up;
/* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
extern int dhd_idletime;
#define DHD_IDLETIME_TICKS 1
/* SDIO Drive Strength */
extern uint dhd_sdiod_drive_strength;
/* Override to force tx queueing all the time */
extern uint dhd_force_tx_queueing;
#ifdef SDTEST
/* Echo packet generator (SDIO), pkts/s */
extern uint dhd_pktgen;
/* Echo packet len (0 => sawtooth, max 1800) */
extern uint dhd_pktgen_len;
#define MAX_PKTGEN_LEN 1800
#endif
extern char fw_path[MOD_PARAM_PATHLEN];
extern char nv_path[MOD_PARAM_PATHLEN];
extern u32 g_assert_type;
extern const bcmevent_name_t bcmevent_names[];
extern const int bcmevent_names_size;
static inline void MUTEX_LOCK_INIT(dhd_pub_t *dhdp)
{
@ -205,13 +919,6 @@ static inline void MUTEX_UNLOCK_WL_SCAN_SET(void)
{
}
typedef struct dhd_if_event {
u8 ifidx;
u8 action;
u8 flags;
u8 bssidx;
} dhd_if_event_t;
/*
* Exported from dhd OS modules (dhd_linux/dhd_ndis)
*/
@ -286,13 +993,6 @@ extern void dhd_os_sdtxunlock(dhd_pub_t *pub);
int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
typedef struct {
u32 limit; /* Expiration time (usec) */
u32 increment; /* Current expiration increment (usec) */
u32 elapsed; /* Current elapsed time (usec) */
u32 tick; /* O/S tick time (usec) */
} dhd_timeout_t;
extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
extern int dhd_timeout_expired(dhd_timeout_t *tmo);
@ -324,85 +1024,9 @@ extern int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag);
extern uint dhd_bus_status(dhd_pub_t *dhdp);
extern int dhd_bus_start(dhd_pub_t *dhdp);
enum cust_gpio_modes {
WLAN_RESET_ON,
WLAN_RESET_OFF,
WLAN_POWER_ON,
WLAN_POWER_OFF
};
/*
* Insmod parameters for debug/test
*/
/* Watchdog timer interval */
extern uint dhd_watchdog_ms;
#if defined(DHD_DEBUG)
/* Console output poll interval */
extern uint dhd_console_ms;
#endif /* defined(DHD_DEBUG) */
/* Use interrupts */
extern uint dhd_intr;
/* Use polling */
extern uint dhd_poll;
/* ARP offload agent mode */
extern uint dhd_arp_mode;
/* ARP offload enable */
extern uint dhd_arp_enable;
/* Pkt filte enable control */
extern uint dhd_pkt_filter_enable;
/* Pkt filter init setup */
extern uint dhd_pkt_filter_init;
/* Pkt filter mode control */
extern uint dhd_master_mode;
/* Roaming mode control */
extern uint dhd_roam;
/* Roaming mode control */
extern uint dhd_radio_up;
/* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
extern int dhd_idletime;
#define DHD_IDLETIME_TICKS 1
/* SDIO Drive Strength */
extern uint dhd_sdiod_drive_strength;
/* Override to force tx queueing all the time */
extern uint dhd_force_tx_queueing;
#ifdef SDTEST
/* Echo packet generator (SDIO), pkts/s */
extern uint dhd_pktgen;
/* Echo packet len (0 => sawtooth, max 1800) */
extern uint dhd_pktgen_len;
#define MAX_PKTGEN_LEN 1800
#endif
/* optionally set by a module_param_string() */
#define MOD_PARAM_PATHLEN 2048
extern char fw_path[MOD_PARAM_PATHLEN];
extern char nv_path[MOD_PARAM_PATHLEN];
/* For supporting multiple interfaces */
#define DHD_MAX_IFS 16
#define DHD_DEL_IF -0xe
#define DHD_BAD_IF -0xf
extern void dhd_wait_for_event(dhd_pub_t *dhd, bool * lockvar);
extern void dhd_wait_event_wakeup(dhd_pub_t *dhd);
extern u32 g_assert_type;
#ifdef BCMDBG
#define ASSERT(exp) \
do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
@ -411,4 +1035,84 @@ extern void osl_assert(char *exp, char *file, int line);
#define ASSERT(exp) do {} while (0)
#endif /* defined(BCMDBG) */
/* Linux network driver ioctl encoding */
typedef struct dhd_ioctl {
uint cmd; /* common ioctl definition */
void *buf; /* pointer to user buffer */
uint len; /* length of user buffer */
bool set; /* get or set request (optional) */
uint used; /* bytes read or written (optional) */
uint needed; /* bytes needed (optional) */
uint driver; /* to identify target driver */
} dhd_ioctl_t;
/* per-driver magic numbers */
#define DHD_IOCTL_MAGIC 0x00444944
/* bump this number if you change the ioctl interface */
#define DHD_IOCTL_VERSION 1
#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
/* common ioctl definitions */
#define DHD_GET_MAGIC 0
#define DHD_GET_VERSION 1
#define DHD_GET_VAR 2
#define DHD_SET_VAR 3
/* message levels */
#define DHD_ERROR_VAL 0x0001
#define DHD_TRACE_VAL 0x0002
#define DHD_INFO_VAL 0x0004
#define DHD_DATA_VAL 0x0008
#define DHD_CTL_VAL 0x0010
#define DHD_TIMER_VAL 0x0020
#define DHD_HDRS_VAL 0x0040
#define DHD_BYTES_VAL 0x0080
#define DHD_INTR_VAL 0x0100
#define DHD_LOG_VAL 0x0200
#define DHD_GLOM_VAL 0x0400
#define DHD_EVENT_VAL 0x0800
#define DHD_BTA_VAL 0x1000
#define DHD_ISCAN_VAL 0x2000
#ifdef SDTEST
/* For pktgen iovar */
typedef struct dhd_pktgen {
uint version; /* To allow structure change tracking */
uint freq; /* Max ticks between tx/rx attempts */
uint count; /* Test packets to send/rcv each attempt */
uint print; /* Print counts every <print> attempts */
uint total; /* Total packets (or bursts) */
uint minlen; /* Minimum length of packets to send */
uint maxlen; /* Maximum length of packets to send */
uint numsent; /* Count of test packets sent */
uint numrcvd; /* Count of test packets received */
uint numfail; /* Count of test send failures */
uint mode; /* Test mode (type of test packets) */
uint stop; /* Stop after this many tx failures */
} dhd_pktgen_t;
/* Version in case structure changes */
#define DHD_PKTGEN_VERSION 2
/* Type of test packets to use */
#define DHD_PKTGEN_ECHO 1 /* Send echo requests */
#define DHD_PKTGEN_SEND 2 /* Send discard packets */
#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */
#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous
tx dongle */
#endif /* SDTEST */
/* Enter idle immediately (no timeout) */
#define DHD_IDLE_IMMEDIATE (-1)
/* Values for idleclock iovar: other values are the sd_divisor to use
when idle */
#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change
when idle */
#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped
(and use SD1 mode) */
#endif /* _dhd_h_ */

2
drivers/staging/brcm80211/brcmfmac/dhd_bus.h
View File

@ -63,7 +63,7 @@ extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
bool set);
/* Add bus dump output to a buffer */
extern void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
extern void dhd_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf);
/* Clear any bus counters */
extern void dhd_bus_clearcounts(dhd_pub_t *dhdp);

85
drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
View File

@ -16,16 +16,70 @@
#include <linux/types.h>
#include <linux/netdevice.h>
#include <bcmdefs.h>
#include <linux/sched.h>
#include <defs.h>
#include <bcmutils.h>
#include <bcmcdc.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhd_proto.h>
#include <dhd_bus.h>
#include <dhd_dbg.h>
struct cdc_ioctl {
u32 cmd; /* ioctl command value */
u32 len; /* lower 16: output buflen;
* upper 16: input buflen (excludes header) */
u32 flags; /* flag defns given below */
u32 status; /* status code returned from the device */
};
/* Max valid buffer size that can be sent to the dongle */
#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
/* CDC flag definitions */
#define CDCF_IOC_ERROR 0x01 /* 1=ioctl cmd failed */
#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */
#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */
#define CDCF_IOC_IF_SHIFT 12
#define CDCF_IOC_ID_MASK 0xFFFF0000 /* id an ioctl pairing */
#define CDCF_IOC_ID_SHIFT 16 /* ID Mask shift bits */
#define CDC_IOC_ID(flags) \
(((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT)
#define CDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | \
((idx) << CDCF_IOC_IF_SHIFT)))
/*
* BDC header
* Used on data packets to convey priority across USB.
*/
#define BDC_HEADER_LEN 4
#define BDC_PROTO_VER 1 /* Protocol version */
#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
#define BDC_FLAG_SUM_GOOD 0x04 /* Good RX checksums */
#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
#define BDC_PRIORITY_MASK 0x7
#define BDC_FLAG2_IF_MASK 0x0f /* packet rx interface in APSTA */
#define BDC_FLAG2_IF_SHIFT 0
#define BDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
#define BDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \
((idx) << BDC_FLAG2_IF_SHIFT)))
struct bdc_header {
u8 flags;
u8 priority; /* 802.1d Priority, 4:7 flow control info for usb */
u8 flags2;
u8 rssi;
};
#ifdef CUSTOMER_HW2
int wifi_get_mac_addr(unsigned char *buf);
#endif
@ -56,14 +110,14 @@ typedef struct dhd_prot {
u8 pending;
u32 lastcmd;
u8 bus_header[BUS_HEADER_LEN];
cdc_ioctl_t msg;
struct cdc_ioctl msg;
unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
} dhd_prot_t;
static int dhdcdc_msg(dhd_pub_t *dhd)
{
dhd_prot_t *prot = dhd->prot;
int len = le32_to_cpu(prot->msg.len) + sizeof(cdc_ioctl_t);
int len = le32_to_cpu(prot->msg.len) + sizeof(struct cdc_ioctl);
DHD_TRACE(("%s: Enter\n", __func__));
@ -88,7 +142,7 @@ static int dhdcdc_cmplt(dhd_pub_t *dhd, u32 id, u32 len)
do {
ret =
dhd_bus_rxctl(dhd->bus, (unsigned char *)&prot->msg,
len + sizeof(cdc_ioctl_t));
len + sizeof(struct cdc_ioctl));
if (ret < 0)
break;
} while (CDC_IOC_ID(le32_to_cpu(prot->msg.flags)) != id);
@ -100,7 +154,7 @@ int
dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
{
dhd_prot_t *prot = dhd->prot;
cdc_ioctl_t *msg = &prot->msg;
struct cdc_ioctl *msg = &prot->msg;
void *info;
int ret = 0, retries = 0;
u32 id, flags = 0;
@ -120,7 +174,7 @@ dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
}
}
memset(msg, 0, sizeof(cdc_ioctl_t));
memset(msg, 0, sizeof(struct cdc_ioctl));
msg->cmd = cpu_to_le32(cmd);
msg->len = cpu_to_le32(len);
@ -180,14 +234,14 @@ done:
int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
{
dhd_prot_t *prot = dhd->prot;
cdc_ioctl_t *msg = &prot->msg;
struct cdc_ioctl *msg = &prot->msg;
int ret = 0;
u32 flags, id;
DHD_TRACE(("%s: Enter\n", __func__));
DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len));
memset(msg, 0, sizeof(cdc_ioctl_t));
memset(msg, 0, sizeof(struct cdc_ioctl));
msg->cmd = cpu_to_le32(cmd);
msg->len = cpu_to_le32(len);
@ -266,14 +320,14 @@ dhd_prot_ioctl(dhd_pub_t *dhd, int ifidx, wl_ioctl_t *ioc, void *buf, int len)
else {
ret = dhdcdc_query_ioctl(dhd, ifidx, ioc->cmd, buf, len);
if (ret > 0)
ioc->used = ret - sizeof(cdc_ioctl_t);
ioc->used = ret - sizeof(struct cdc_ioctl);
}
/* Too many programs assume ioctl() returns 0 on success */
if (ret >= 0)
ret = 0;
else {
cdc_ioctl_t *msg = &prot->msg;
struct cdc_ioctl *msg = &prot->msg;
/* len == needed when set/query fails from dongle */
ioc->needed = le32_to_cpu(msg->len);
}
@ -312,9 +366,9 @@ dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
return -ENOTSUPP;
}
void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
void dhd_prot_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
{
bcm_bprintf(strbuf, "Protocol CDC: reqid %d\n", dhdp->prot->reqid);
brcmu_bprintf(strbuf, "Protocol CDC: reqid %d\n", dhdp->prot->reqid);
}
void dhd_prot_hdrpush(dhd_pub_t *dhd, int ifidx, struct sk_buff *pktbuf)
@ -411,7 +465,8 @@ int dhd_prot_attach(dhd_pub_t *dhd)
#ifdef BDC
dhd->hdrlen += BDC_HEADER_LEN;
#endif
dhd->maxctl = WLC_IOCTL_MAXLEN + sizeof(cdc_ioctl_t) + ROUND_UP_MARGIN;
dhd->maxctl =
WLC_IOCTL_MAXLEN + sizeof(struct cdc_ioctl) + ROUND_UP_MARGIN;
return 0;
fail:

152
drivers/staging/brcm80211/brcmfmac/dhd_common.c
View File

@ -15,16 +15,21 @@
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <bcmdefs.h>
#include <linux/sched.h>
#include <defs.h>
#include <brcmu_wifi.h>
#include <linux/netdevice.h>
#include <bcmutils.h>
#include <asm/unaligned.h>
#include <brcmu_utils.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhd_bus.h>
#include <dhd_proto.h>
#include <dhd_dbg.h>
#include <msgtrace.h>
#include <wlioctl.h>
#define BRCM_OUI "\x00\x10\x18"
#define DOT11_OUI_LEN 3
#define BCMILCP_BCM_SUBTYPE_EVENT 1
int dhd_msg_level;
char fw_path[MOD_PARAM_PATHLEN];
@ -51,6 +56,8 @@ void dhd_iscan_unlock(void);
#endif
#define EPI_VERSION_STR "4.218.248.5"
#define MSGTRACE_VERSION 1
#ifdef DHD_DEBUG
const char dhd_version[] =
"Dongle Host Driver, version " EPI_VERSION_STR "\nCompiled on " __DATE__
@ -82,7 +89,7 @@ enum {
IOV_LAST
};
const bcm_iovar_t dhd_iovars[] = {
const struct brcmu_iovar dhd_iovars[] = {
{"version", IOV_VERSION, 0, IOVT_BUFFER, sizeof(dhd_version)}
,
#ifdef DHD_DEBUG
@ -112,6 +119,22 @@ const bcm_iovar_t dhd_iovars[] = {
{NULL, 0, 0, 0, 0}
};
/* Message trace header */
struct msgtrace_hdr {
u8 version;
u8 spare;
u16 len; /* Len of the trace */
u32 seqnum; /* Sequence number of message. Useful
* if the messsage has been lost
* because of DMA error or a bus reset
* (ex: SDIO Func2)
*/
u32 discarded_bytes; /* Number of discarded bytes because of
trace overflow */
u32 discarded_printf; /* Number of discarded printf
because of trace overflow */
} __packed;
void dhd_common_init(void)
{
/* Init global variables at run-time, not as part of the declaration.
@ -137,54 +160,54 @@ void dhd_common_init(void)
static int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
{
struct bcmstrbuf b;
struct bcmstrbuf *strbuf = &b;
struct brcmu_strbuf b;
struct brcmu_strbuf *strbuf = &b;
bcm_binit(strbuf, buf, buflen);
brcmu_binit(strbuf, buf, buflen);
/* Base DHD info */
bcm_bprintf(strbuf, "%s\n", dhd_version);
bcm_bprintf(strbuf, "\n");
bcm_bprintf(strbuf, "pub.up %d pub.txoff %d pub.busstate %d\n",
brcmu_bprintf(strbuf, "%s\n", dhd_version);
brcmu_bprintf(strbuf, "\n");
brcmu_bprintf(strbuf, "pub.up %d pub.txoff %d pub.busstate %d\n",
dhdp->up, dhdp->txoff, dhdp->busstate);
bcm_bprintf(strbuf, "pub.hdrlen %d pub.maxctl %d pub.rxsz %d\n",
brcmu_bprintf(strbuf, "pub.hdrlen %d pub.maxctl %d pub.rxsz %d\n",
dhdp->hdrlen, dhdp->maxctl, dhdp->rxsz);
bcm_bprintf(strbuf, "pub.iswl %d pub.drv_version %ld pub.mac %pM\n",
brcmu_bprintf(strbuf, "pub.iswl %d pub.drv_version %ld pub.mac %pM\n",
dhdp->iswl, dhdp->drv_version, &dhdp->mac);
bcm_bprintf(strbuf, "pub.bcmerror %d tickcnt %d\n", dhdp->bcmerror,
brcmu_bprintf(strbuf, "pub.bcmerror %d tickcnt %d\n", dhdp->bcmerror,
dhdp->tickcnt);
bcm_bprintf(strbuf, "dongle stats:\n");
bcm_bprintf(strbuf,
brcmu_bprintf(strbuf, "dongle stats:\n");
brcmu_bprintf(strbuf,
"tx_packets %ld tx_bytes %ld tx_errors %ld tx_dropped %ld\n",
dhdp->dstats.tx_packets, dhdp->dstats.tx_bytes,
dhdp->dstats.tx_errors, dhdp->dstats.tx_dropped);
bcm_bprintf(strbuf,
brcmu_bprintf(strbuf,
"rx_packets %ld rx_bytes %ld rx_errors %ld rx_dropped %ld\n",
dhdp->dstats.rx_packets, dhdp->dstats.rx_bytes,
dhdp->dstats.rx_errors, dhdp->dstats.rx_dropped);
bcm_bprintf(strbuf, "multicast %ld\n", dhdp->dstats.multicast);
brcmu_bprintf(strbuf, "multicast %ld\n", dhdp->dstats.multicast);
bcm_bprintf(strbuf, "bus stats:\n");
bcm_bprintf(strbuf, "tx_packets %ld tx_multicast %ld tx_errors %ld\n",
brcmu_bprintf(strbuf, "bus stats:\n");
brcmu_bprintf(strbuf, "tx_packets %ld tx_multicast %ld tx_errors %ld\n",
dhdp->tx_packets, dhdp->tx_multicast, dhdp->tx_errors);
bcm_bprintf(strbuf, "tx_ctlpkts %ld tx_ctlerrs %ld\n",
brcmu_bprintf(strbuf, "tx_ctlpkts %ld tx_ctlerrs %ld\n",
dhdp->tx_ctlpkts, dhdp->tx_ctlerrs);
bcm_bprintf(strbuf, "rx_packets %ld rx_multicast %ld rx_errors %ld\n",
brcmu_bprintf(strbuf, "rx_packets %ld rx_multicast %ld rx_errors %ld\n",
dhdp->rx_packets, dhdp->rx_multicast, dhdp->rx_errors);
bcm_bprintf(strbuf,
brcmu_bprintf(strbuf,
"rx_ctlpkts %ld rx_ctlerrs %ld rx_dropped %ld rx_flushed %ld\n",
dhdp->rx_ctlpkts, dhdp->rx_ctlerrs, dhdp->rx_dropped,
dhdp->rx_flushed);
bcm_bprintf(strbuf,
brcmu_bprintf(strbuf,
"rx_readahead_cnt %ld tx_realloc %ld fc_packets %ld\n",
dhdp->rx_readahead_cnt, dhdp->tx_realloc, dhdp->fc_packets);
bcm_bprintf(strbuf, "wd_dpc_sched %ld\n", dhdp->wd_dpc_sched);
bcm_bprintf(strbuf, "\n");
brcmu_bprintf(strbuf, "wd_dpc_sched %ld\n", dhdp->wd_dpc_sched);
brcmu_bprintf(strbuf, "\n");
/* Add any prot info */
dhd_prot_dump(dhdp, strbuf);
bcm_bprintf(strbuf, "\n");
brcmu_bprintf(strbuf, "\n");
/* Add any bus info */
dhd_bus_dump(dhdp, strbuf);
@ -193,7 +216,7 @@ static int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
}
static int
dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, u32 actionid,
dhd_doiovar(dhd_pub_t *dhd_pub, const struct brcmu_iovar *vi, u32 actionid,
const char *name, void *params, int plen, void *arg, int len,
int val_size)
{
@ -202,7 +225,7 @@ dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, u32 actionid,
DHD_TRACE(("%s: Enter\n", __func__));
bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
if (bcmerror != 0)
goto exit;
@ -316,7 +339,7 @@ bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, struct sk_buff *pkt,
* exceeding total queue length
*/
if (!pktq_pfull(q, prec) && !pktq_full(q)) {
bcm_pktq_penq(q, prec, pkt);
brcmu_pktq_penq(q, prec, pkt);
return true;
}
@ -324,7 +347,7 @@ bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, struct sk_buff *pkt,
if (pktq_pfull(q, prec))
eprec = prec;
else if (pktq_full(q)) {
p = bcm_pktq_peek_tail(q, &eprec);
p = brcmu_pktq_peek_tail(q, &eprec);
ASSERT(p);
if (eprec > prec)
return false;
@ -338,21 +361,21 @@ bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, struct sk_buff *pkt,
if (eprec == prec && !discard_oldest)
return false; /* refuse newer (incoming) packet */
/* Evict packet according to discard policy */
p = discard_oldest ? bcm_pktq_pdeq(q, eprec) :
bcm_pktq_pdeq_tail(q, eprec);
p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
brcmu_pktq_pdeq_tail(q, eprec);
if (p == NULL) {
DHD_ERROR(("%s: bcm_pktq_penq() failed, oldest %d.",
DHD_ERROR(("%s: brcmu_pktq_penq() failed, oldest %d.",
__func__, discard_oldest));
ASSERT(p);
}
bcm_pkt_buf_free_skb(p);
brcmu_pkt_buf_free_skb(p);
}
/* Enqueue */
p = bcm_pktq_penq(q, prec, pkt);
p = brcmu_pktq_penq(q, prec, pkt);
if (p == NULL) {
DHD_ERROR(("%s: bcm_pktq_penq() failed.", __func__));
DHD_ERROR(("%s: brcmu_pktq_penq() failed.", __func__));
ASSERT(p);
}
@ -365,7 +388,7 @@ dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
{
int bcmerror = 0;
int val_size;
const bcm_iovar_t *vi = NULL;
const struct brcmu_iovar *vi = NULL;
u32 actionid;
DHD_TRACE(("%s: Enter\n", __func__));
@ -379,7 +402,7 @@ dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
/* Set does NOT take qualifiers */
ASSERT(!set || (!params && !plen));
vi = bcm_iovar_lookup(dhd_iovars, name);
vi = brcmu_iovar_lookup(dhd_iovars, name);
if (vi == NULL) {
bcmerror = -ENOTSUPP;
goto exit;
@ -726,12 +749,12 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data)
case WLC_E_TRACE:
{
static u32 seqnum_prev;
msgtrace_hdr_t hdr;
struct msgtrace_hdr hdr;
u32 nblost;
char *s, *p;
buf = (unsigned char *) event_data;
memcpy(&hdr, buf, MSGTRACE_HDRLEN);
memcpy(&hdr, buf, sizeof(struct msgtrace_hdr));
if (hdr.version != MSGTRACE_VERSION) {
DHD_ERROR(
@ -745,7 +768,8 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data)
}
/* There are 2 bytes available at the end of data */
buf[MSGTRACE_HDRLEN + be16_to_cpu(hdr.len)] = '\0';
*(buf + sizeof(struct msgtrace_hdr)
+ be16_to_cpu(hdr.len)) = '\0';
if (be32_to_cpu(hdr.discarded_bytes)
|| be32_to_cpu(hdr.discarded_printf)) {
@ -768,7 +792,7 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data)
* avoid display big
* printf (issue with Linux printk )
*/
p = (char *)&buf[MSGTRACE_HDRLEN];
p = (char *)&buf[sizeof(struct msgtrace_hdr)];
while ((s = strstr(p, "\n")) != NULL) {
*s = '\0';
printk(KERN_DEBUG"%s\n", p);
@ -989,7 +1013,7 @@ dhd_pktfilter_offload_enable(dhd_pub_t *dhd, char *arg, int enable,
__func__, arg));
/* Contorl the master mode */
bcm_mkiovar("pkt_filter_mode", (char *)&master_mode, 4, buf,
brcmu_mkiovar("pkt_filter_mode", (char *)&master_mode, 4, buf,
sizeof(buf));
rc = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, buf, sizeof(buf));
rc = rc >= 0 ? 0 : rc;
@ -1143,7 +1167,7 @@ void dhd_arp_offload_set(dhd_pub_t *dhd, int arp_mode)
char iovbuf[32];
int retcode;
bcm_mkiovar("arp_ol", (char *)&arp_mode, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("arp_ol", (char *)&arp_mode, 4, iovbuf, sizeof(iovbuf));
retcode = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
retcode = retcode >= 0 ? 0 : retcode;
if (retcode)
@ -1159,7 +1183,7 @@ void dhd_arp_offload_enable(dhd_pub_t *dhd, int arp_enable)
char iovbuf[32];
int retcode;
bcm_mkiovar("arpoe", (char *)&arp_enable, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("arpoe", (char *)&arp_enable, 4, iovbuf, sizeof(iovbuf));
retcode = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
retcode = retcode >= 0 ? 0 : retcode;
if (retcode)
@ -1198,7 +1222,7 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
*/
ret = dhd_custom_get_mac_address(ea_addr);
if (!ret) {
bcm_mkiovar("cur_etheraddr", (void *)ea_addr, ETH_ALEN,
brcmu_mkiovar("cur_etheraddr", (void *)ea_addr, ETH_ALEN,
buf, sizeof(buf));
ret = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, buf, sizeof(buf));
if (ret < 0) {
@ -1223,7 +1247,7 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
/* query for 'ver' to get version info from firmware */
memset(buf, 0, sizeof(buf));
ptr = buf;
bcm_mkiovar("ver", 0, 0, buf, sizeof(buf));
brcmu_mkiovar("ver", 0, 0, buf, sizeof(buf));
dhdcdc_query_ioctl(dhd, 0, WLC_GET_VAR, buf, sizeof(buf));
strsep(&ptr, "\n");
/* Print fw version info */
@ -1234,23 +1258,23 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
sizeof(power_mode));
/* Match Host and Dongle rx alignment */
bcm_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
brcmu_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
/* disable glom option per default */
bcm_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
/* Setup timeout if Beacons are lost and roam is off to report
link down */
bcm_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf,
brcmu_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf,
sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
/* Enable/Disable build-in roaming to allowed ext supplicant to take
of romaing */
bcm_mkiovar("roam_off", (char *)&dhd_roam, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("roam_off", (char *)&dhd_roam, 4, iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
/* Force STA UP */
@ -1258,8 +1282,8 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
dhdcdc_set_ioctl(dhd, 0, WLC_UP, (char *)&up, sizeof(up));
/* Setup event_msgs */
bcm_mkiovar("event_msgs", dhd->eventmask, WL_EVENTING_MASK_LEN, iovbuf,
sizeof(iovbuf));
brcmu_mkiovar("event_msgs", dhd->eventmask, WL_EVENTING_MASK_LEN,
iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_SCAN_CHANNEL_TIME,
@ -1623,7 +1647,7 @@ int dhd_iscan_request(void *dhdp, u16 action)
params.action = action;
params.scan_duration = 0;
bcm_mkiovar("iscan", (char *)&params, sizeof(wl_iscan_params_t), buf,
brcmu_mkiovar("iscan", (char *)&params, sizeof(wl_iscan_params_t), buf,
WLC_IOCTL_SMLEN);
rc = dhd_wl_ioctl(dhdp, WLC_SET_VAR, buf, WLC_IOCTL_SMLEN);
@ -1659,8 +1683,9 @@ static int dhd_iscan_get_partial_result(void *dhdp, uint *scan_count)
memset(&list, 0, sizeof(list));
list.results.buflen = WLC_IW_ISCAN_MAXLEN;
bcm_mkiovar("iscanresults", (char *)&list, WL_ISCAN_RESULTS_FIXED_SIZE,
iscan_cur->iscan_buf, WLC_IW_ISCAN_MAXLEN);
brcmu_mkiovar("iscanresults", (char *)&list,
WL_ISCAN_RESULTS_FIXED_SIZE,
iscan_cur->iscan_buf, WLC_IW_ISCAN_MAXLEN);
rc = dhd_wl_ioctl(dhdp, WLC_GET_VAR, iscan_cur->iscan_buf,
WLC_IW_ISCAN_MAXLEN);
@ -1690,12 +1715,13 @@ int dhd_pno_clean(dhd_pub_t *dhd)
int ret;
/* Disable pfn */
iov_len =
bcm_mkiovar("pfn", (char *)&pfn_enabled, 4, iovbuf, sizeof(iovbuf));
iov_len = brcmu_mkiovar("pfn", (char *)&pfn_enabled, 4, iovbuf,
sizeof(iovbuf));
ret = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (ret >= 0) {
/* clear pfn */
iov_len = bcm_mkiovar("pfnclear", 0, 0, iovbuf, sizeof(iovbuf));
iov_len = brcmu_mkiovar("pfnclear", 0, 0, iovbuf,
sizeof(iovbuf));
if (iov_len) {
ret = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
iov_len);
@ -1724,7 +1750,7 @@ int dhd_pno_enable(dhd_pub_t *dhd, int pfn_enabled)
}
/* Enable/disable PNO */
ret = bcm_mkiovar("pfn", (char *)&pfn_enabled, 4, iovbuf,
ret = brcmu_mkiovar("pfn", (char *)&pfn_enabled, 4, iovbuf,
sizeof(iovbuf));
if (ret > 0) {
ret = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
@ -1797,7 +1823,7 @@ dhd_pno_set(dhd_pub_t *dhd, wlc_ssid_t *ssids_local, int nssid, unsigned char sc
if (scan_fr != 0)
pfn_param.scan_freq = scan_fr;
bcm_mkiovar("pfn_set", (char *)&pfn_param, sizeof(pfn_param), iovbuf,
brcmu_mkiovar("pfn_set", (char *)&pfn_param, sizeof(pfn_param), iovbuf,
sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
@ -1814,7 +1840,7 @@ dhd_pno_set(dhd_pub_t *dhd, wlc_ssid_t *ssids_local, int nssid, unsigned char sc
ssids_local[i].SSID_len);
pfn_element.ssid.SSID_len = ssids_local[i].SSID_len;
err = bcm_mkiovar("pfn_add", (char *)&pfn_element,
err = brcmu_mkiovar("pfn_add", (char *)&pfn_element,
sizeof(pfn_element), iovbuf, sizeof(iovbuf));
if (err > 0) {
err = dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,

8
drivers/staging/brcm80211/brcmfmac/dhd_custom_gpio.c
View File

@ -15,14 +15,14 @@
*/
#include <linux/netdevice.h>
#include <bcmutils.h>
#include <linux/sched.h>
#include <brcmu_utils.h>
#include <defs.h>
#include <brcmu_wifi.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <wlioctl.h>
#include <wl_iw.h>
#define WL_ERROR(fmt, args...) printk(fmt, ##args)
#define WL_TRACE(fmt, args...) no_printk(fmt, ##args)

3
drivers/staging/brcm80211/brcmfmac/dhd_dbg.h
View File

@ -97,7 +97,4 @@
#define DHD_NONE(args)
extern int dhd_msg_level;
/* Defines msg bits */
#include <dhdioctl.h>
#endif /* _dhd_dbg_ */

24
drivers/staging/brcm80211/brcmfmac/dhd_linux.c
View File

@ -31,8 +31,10 @@
#include <linux/fcntl.h>
#include <linux/fs.h>
#include <linux/uaccess.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <net/cfg80211.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <dngl_stats.h>
#include <dhd.h>
@ -483,7 +485,7 @@ static int dhd_set_suspend(int value, dhd_pub_t *dhd)
bcn_li_dtim = 3;
else
bcn_li_dtim = dhd->dtim_skip;
bcm_mkiovar("bcn_li_dtim", (char *)&bcn_li_dtim,
brcmu_mkiovar("bcn_li_dtim", (char *)&bcn_li_dtim,
4, iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
sizeof(iovbuf));
@ -491,7 +493,7 @@ static int dhd_set_suspend(int value, dhd_pub_t *dhd)
/* Disable build-in roaming to allowed \
* supplicant to take of romaing
*/
bcm_mkiovar("roam_off", (char *)&roamvar, 4,
brcmu_mkiovar("roam_off", (char *)&roamvar, 4,
iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
sizeof(iovbuf));
@ -511,14 +513,14 @@ static int dhd_set_suspend(int value, dhd_pub_t *dhd)
dhd_set_packet_filter(0, dhd);
/* restore pre-suspend setting for dtim_skip */
bcm_mkiovar("bcn_li_dtim", (char *)&dhd->dtim_skip,
brcmu_mkiovar("bcn_li_dtim", (char *)&dhd->dtim_skip,
4, iovbuf, sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
sizeof(iovbuf));
#ifdef CUSTOMER_HW2
roamvar = 0;
bcm_mkiovar("roam_off", (char *)&roamvar, 4, iovbuf,
brcmu_mkiovar("roam_off", (char *)&roamvar, 4, iovbuf,
sizeof(iovbuf));
dhdcdc_set_ioctl(dhd, 0, WLC_SET_VAR, iovbuf,
sizeof(iovbuf));
@ -748,7 +750,7 @@ static void _dhd_set_multicast_list(dhd_info_t *dhd, int ifidx)
}
allmulti = cpu_to_le32(allmulti);
if (!bcm_mkiovar
if (!brcmu_mkiovar
("allmulti", (void *)&allmulti, sizeof(allmulti), buf, buflen)) {
DHD_ERROR(("%s: mkiovar failed for allmulti, datalen %d "
"buflen %u\n", dhd_ifname(&dhd->pub, ifidx),
@ -800,7 +802,7 @@ _dhd_set_mac_address(dhd_info_t *dhd, int ifidx, u8 *addr)
int ret;
DHD_TRACE(("%s enter\n", __func__));
if (!bcm_mkiovar
if (!brcmu_mkiovar
("cur_etheraddr", (char *)addr, ETH_ALEN, buf, 32)) {
DHD_ERROR(("%s: mkiovar failed for cur_etheraddr\n",
dhd_ifname(&dhd->pub, ifidx)));
@ -2089,8 +2091,8 @@ int dhd_bus_start(dhd_pub_t *dhdp)
return -ENODEV;
}
#ifdef EMBEDDED_PLATFORM
bcm_mkiovar("event_msgs", dhdp->eventmask, WL_EVENTING_MASK_LEN, iovbuf,
sizeof(iovbuf));
brcmu_mkiovar("event_msgs", dhdp->eventmask, WL_EVENTING_MASK_LEN,
iovbuf, sizeof(iovbuf));
dhdcdc_query_ioctl(dhdp, 0, WLC_GET_VAR, iovbuf, sizeof(iovbuf));
memcpy(dhdp->eventmask, iovbuf, WL_EVENTING_MASK_LEN);
@ -2140,7 +2142,7 @@ dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf, uint cmd_len,
wl_ioctl_t ioc;
int ret;
len = bcm_mkiovar(name, cmd_buf, cmd_len, buf, len);
len = brcmu_mkiovar(name, cmd_buf, cmd_len, buf, len);
memset(&ioc, 0, sizeof(ioc));

5
drivers/staging/brcm80211/brcmfmac/dhd_proto.h
View File

@ -17,9 +17,6 @@
#ifndef _dhd_proto_h_
#define _dhd_proto_h_
#include <dhdioctl.h>
#include <wlioctl.h>
#ifndef IOCTL_RESP_TIMEOUT
#define IOCTL_RESP_TIMEOUT 2000 /* In milli second */
#endif
@ -64,7 +61,7 @@ extern int dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
bool set);
/* Add prot dump output to a buffer */
extern void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
extern void dhd_prot_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf);
/* Update local copy of dongle statistics */
extern void dhd_prot_dstats(dhd_pub_t *dhdp);

907
drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
View File

File diff suppressed because it is too large Load Diff

100
drivers/staging/brcm80211/brcmfmac/dhdioctl.h
View File

@ -1,100 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _dhdioctl_h_
#define _dhdioctl_h_
/* Linux network driver ioctl encoding */
typedef struct dhd_ioctl {
uint cmd; /* common ioctl definition */
void *buf; /* pointer to user buffer */
uint len; /* length of user buffer */
bool set; /* get or set request (optional) */
uint used; /* bytes read or written (optional) */
uint needed; /* bytes needed (optional) */
uint driver; /* to identify target driver */
} dhd_ioctl_t;
/* per-driver magic numbers */
#define DHD_IOCTL_MAGIC 0x00444944
/* bump this number if you change the ioctl interface */
#define DHD_IOCTL_VERSION 1
#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
/* common ioctl definitions */
#define DHD_GET_MAGIC 0
#define DHD_GET_VERSION 1
#define DHD_GET_VAR 2
#define DHD_SET_VAR 3
/* message levels */
#define DHD_ERROR_VAL 0x0001
#define DHD_TRACE_VAL 0x0002
#define DHD_INFO_VAL 0x0004
#define DHD_DATA_VAL 0x0008
#define DHD_CTL_VAL 0x0010
#define DHD_TIMER_VAL 0x0020
#define DHD_HDRS_VAL 0x0040
#define DHD_BYTES_VAL 0x0080
#define DHD_INTR_VAL 0x0100
#define DHD_LOG_VAL 0x0200
#define DHD_GLOM_VAL 0x0400
#define DHD_EVENT_VAL 0x0800
#define DHD_BTA_VAL 0x1000
#define DHD_ISCAN_VAL 0x2000
#ifdef SDTEST
/* For pktgen iovar */
typedef struct dhd_pktgen {
uint version; /* To allow structure change tracking */
uint freq; /* Max ticks between tx/rx attempts */
uint count; /* Test packets to send/rcv each attempt */
uint print; /* Print counts every <print> attempts */
uint total; /* Total packets (or bursts) */
uint minlen; /* Minimum length of packets to send */
uint maxlen; /* Maximum length of packets to send */
uint numsent; /* Count of test packets sent */
uint numrcvd; /* Count of test packets received */
uint numfail; /* Count of test send failures */
uint mode; /* Test mode (type of test packets) */
uint stop; /* Stop after this many tx failures */
} dhd_pktgen_t;
/* Version in case structure changes */
#define DHD_PKTGEN_VERSION 2
/* Type of test packets to use */
#define DHD_PKTGEN_ECHO 1 /* Send echo requests */
#define DHD_PKTGEN_SEND 2 /* Send discard packets */
#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */
#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous
tx dongle */
#endif /* SDTEST */
/* Enter idle immediately (no timeout) */
#define DHD_IDLE_IMMEDIATE (-1)
/* Values for idleclock iovar: other values are the sd_divisor to use
when idle */
#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change
when idle */
#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped
(and use SD1 mode) */
#endif /* _dhdioctl_h_ */

75
drivers/staging/brcm80211/brcmfmac/hndrte_armtrap.h
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@ -1,75 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndrte_armtrap_h
#define _hndrte_armtrap_h
/* ARM trap handling */
/* Trap types defined by ARM (see arminc.h) */
/* Trap locations in lo memory */
#define TRAP_STRIDE 4
#define FIRST_TRAP TR_RST
#define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
#if defined(__ARM_ARCH_4T__)
#define MAX_TRAP_TYPE (TR_FIQ + 1)
#elif defined(__ARM_ARCH_7M__)
#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
#endif /* __ARM_ARCH_7M__ */
/* The trap structure is defined here as offsets for assembly */
#define TR_TYPE 0x00
#define TR_EPC 0x04
#define TR_CPSR 0x08
#define TR_SPSR 0x0c
#define TR_REGS 0x10
#define TR_REG(n) (TR_REGS + (n) * 4)
#define TR_SP TR_REG(13)
#define TR_LR TR_REG(14)
#define TR_PC TR_REG(15)
#define TRAP_T_SIZE 80
#ifndef _LANGUAGE_ASSEMBLY
typedef struct _trap_struct {
u32 type;
u32 epc;
u32 cpsr;
u32 spsr;
u32 r0;
u32 r1;
u32 r2;
u32 r3;
u32 r4;
u32 r5;
u32 r6;
u32 r7;
u32 r8;
u32 r9;
u32 r10;
u32 r11;
u32 r12;
u32 r13;
u32 r14;
u32 pc;
} trap_t;
#endif /* !_LANGUAGE_ASSEMBLY */
#endif /* _hndrte_armtrap_h */

62
drivers/staging/brcm80211/brcmfmac/hndrte_cons.h
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@ -1,62 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndrte_cons_h
#define _hndrte_cons_h
#define CBUF_LEN (128)
#define LOG_BUF_LEN 1024
typedef struct {
u32 buf; /* Can't be pointer on (64-bit) hosts */
uint buf_size;
uint idx;
char *_buf_compat; /* Redundant pointer for backward compat. */
} hndrte_log_t;
typedef struct {
/* Virtual UART
* When there is no UART (e.g. Quickturn),
* the host should write a complete
* input line directly into cbuf and then write
* the length into vcons_in.
* This may also be used when there is a real UART
* (at risk of conflicting with
* the real UART). vcons_out is currently unused.
*/
volatile uint vcons_in;
volatile uint vcons_out;
/* Output (logging) buffer
* Console output is written to a ring buffer log_buf at index log_idx.
* The host may read the output when it sees log_idx advance.
* Output will be lost if the output wraps around faster than the host
* polls.
*/
hndrte_log_t log;
/* Console input line buffer
* Characters are read one at a time into cbuf
* until <CR> is received, then
* the buffer is processed as a command line.
* Also used for virtual UART.
*/
uint cbuf_idx;
char cbuf[CBUF_LEN];
} hndrte_cons_t;
#endif /* _hndrte_cons_h */

61
drivers/staging/brcm80211/brcmfmac/msgtrace.h
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@ -1,61 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MSGTRACE_H
#define _MSGTRACE_H
#define MSGTRACE_VERSION 1
/* Message trace header */
typedef struct msgtrace_hdr {
u8 version;
u8 spare;
u16 len; /* Len of the trace */
u32 seqnum; /* Sequence number of message. Useful
* if the messsage has been lost
* because of DMA error or a bus reset
* (ex: SDIO Func2)
*/
u32 discarded_bytes; /* Number of discarded bytes because of
trace overflow */
u32 discarded_printf; /* Number of discarded printf
because of trace overflow */
} __attribute__((packed)) msgtrace_hdr_t;
#define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t)
/* The hbus driver generates traces when sending a trace message.
* This causes endless traces.
* This flag must be set to true in any hbus traces.
* The flag is reset in the function msgtrace_put.
* This prevents endless traces but generates hasardous
* lost of traces only in bus device code.
* It is recommendat to set this flag in macro SD_TRACE
* but not in SD_ERROR for avoiding missing
* hbus error traces. hbus error trace should not generates endless traces.
*/
extern bool msgtrace_hbus_trace;
typedef void (*msgtrace_func_send_t) (void *hdl1, void *hdl2, u8 *hdr,
u16 hdrlen, u8 *buf,
u16 buflen);
extern void msgtrace_sent(void);
extern void msgtrace_put(char *buf, int count);
extern void msgtrace_init(void *hdl1, void *hdl2,
msgtrace_func_send_t func_send);
#endif /* _MSGTRACE_H */

2
drivers/staging/brcm80211/include/pcicfg.h → drivers/staging/brcm80211/brcmfmac/pcicfg.h
View File

@ -22,7 +22,7 @@
/* PCI configuration address space size */
#define PCI_SZPCR 256
/* Everything below is BRCM HND proprietary */
/* Everything below is Broadcom specific */
/* Brcm PCI configuration registers */
#define PCI_BAR0_WIN 0x80 /* backplane address space accessed by BAR0 */

373
drivers/staging/brcm80211/brcmfmac/sbsdio.h Normal file
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@ -0,0 +1,373 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SBSDIO_H
#define _SBSDIO_H
#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
/* function 1 miscellaneous registers */
#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
/* SBSDIO_SPROM_CS */
#define SBSDIO_SPROM_IDLE 0
#define SBSDIO_SPROM_WRITE 1
#define SBSDIO_SPROM_READ 2
#define SBSDIO_SPROM_WEN 4
#define SBSDIO_SPROM_WDS 7
#define SBSDIO_SPROM_DONE 8
/* SBSDIO_SPROM_INFO */
#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
#define SROM_OTP 0x80 /* OTP present */
/* SBSDIO_CHIP_CTRL */
#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
* 1: power on oscillator
* (for 4318 only)
*/
/* SBSDIO_WATERMARK */
#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
* to wait before sending data to host
*/
/* SBSDIO_DEVICE_CTL */
#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
* receiving CMD53
*/
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
* synchronous to the sdio clock
*/
#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
* except the chipActive (rev 8)
*/
#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
* external pads in tri-state; requires
* sdio bus power cycle to clear (rev 9)
*/
#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
/* SBSDIO_FUNC1_CHIPCLKCSR */
#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
/* In rev8, actual avail bits followed original docs */
#define SBSDIO_Rev8_HT_AVAIL 0x40
#define SBSDIO_Rev8_ALP_AVAIL 0x80
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
(alponly ? 1 : SBSDIO_HTAV(regval)))
/* SBSDIO_FUNC1_SDIOPULLUP */
#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
/* function 1 OCP space */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
/* some duplication with sbsdpcmdev.h here */
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
/* direct(mapped) cis space */
#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
* link bytes
*/
/* indirect cis access (in sprom) */
#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
* 8th byte
*/
#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
* data command
*/
#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
/* corecontrol */
#define CC_CISRDY (1 << 0) /* CIS Ready */
#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
#define CC_XMTDATAAVAIL_MODE (1 << 4)
#define CC_XMTDATAAVAIL_CTRL (1 << 5)
/* corestatus */
#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
/* intstatus */
#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
#define I_PC (1 << 10) /* descriptor error */
#define I_PD (1 << 11) /* data error */
#define I_DE (1 << 12) /* Descriptor protocol Error */
#define I_RU (1 << 13) /* Receive descriptor Underflow */
#define I_RO (1 << 14) /* Receive fifo Overflow */
#define I_XU (1 << 15) /* Transmit fifo Underflow */
#define I_RI (1 << 16) /* Receive Interrupt */
#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
#define I_XI (1 << 24) /* Transmit Interrupt */
#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
#define I_SRESET (1 << 30) /* CCCR RES interrupt */
#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
#define I_DMA (I_RI | I_XI | I_ERRORS)
/* sbintstatus */
#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
/* sdioaccess */
#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
#define SDA_WRITE 0x01000000 /* Write bit */
#define SDA_READ 0x00000000 /* Write bit cleared for Read */
#define SDA_BUSY 0x80000000 /* Busy bit */
/* sdioaccess-accessible register address spaces */
#define SDA_CCCR_SPACE 0x000 /* CCCR register space */
#define SDA_F1_FBR_SPACE 0x100 /* F1 FBR register space */
#define SDA_F2_FBR_SPACE 0x200 /* F2 FBR register space */
#define SDA_F1_REG_SPACE 0x300 /* F1 core-specific register space */
/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
#define SDA_SBADDRMID 0x00b /* SbAddrMid */
#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
/* SDA_F2WATERMARK */
#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
/* SDA_SBADDRLOW */
#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
/* SDA_SBADDRMID */
#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
/* SDA_SBADDRHIGH */
#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
/* SDA_FRAMECTRL */
#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
/* pcmciaframectrl */
#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
/* intrcvlazy */
#define IRL_TO_MASK 0x00ffffff /* timeout */
#define IRL_FC_MASK 0xff000000 /* frame count */
#define IRL_FC_SHIFT 24 /* frame count */
/* rx header flags */
#define RXF_CRC 0x0001 /* CRC error detected */
#define RXF_WOOS 0x0002 /* write frame out of sync */
#define RXF_WF_TERM 0x0004 /* write frame terminated */
#define RXF_ABORT 0x0008 /* write frame aborted */
#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT)
/* HW frame tag */
#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
/* core registers */
struct sdpcmd_regs {
u32 corecontrol; /* 0x00, rev8 */
u32 corestatus; /* rev8 */
u32 PAD[1];
u32 biststatus; /* rev8 */
/* PCMCIA access */
u16 pcmciamesportaladdr; /* 0x010, rev8 */
u16 PAD[1];
u16 pcmciamesportalmask; /* rev8 */
u16 PAD[1];
u16 pcmciawrframebc; /* rev8 */
u16 PAD[1];
u16 pcmciaunderflowtimer; /* rev8 */
u16 PAD[1];
/* interrupt */
u32 intstatus; /* 0x020, rev8 */
u32 hostintmask; /* rev8 */
u32 intmask; /* rev8 */
u32 sbintstatus; /* rev8 */
u32 sbintmask; /* rev8 */
u32 funcintmask; /* rev4 */
u32 PAD[2];
u32 tosbmailbox; /* 0x040, rev8 */
u32 tohostmailbox; /* rev8 */
u32 tosbmailboxdata; /* rev8 */
u32 tohostmailboxdata; /* rev8 */
/* synchronized access to registers in SDIO clock domain */
u32 sdioaccess; /* 0x050, rev8 */
u32 PAD[3];
/* PCMCIA frame control */
u8 pcmciaframectrl; /* 0x060, rev8 */
u8 PAD[3];
u8 pcmciawatermark; /* rev8 */
u8 PAD[155];
/* interrupt batching control */
u32 intrcvlazy; /* 0x100, rev8 */
u32 PAD[3];
/* counters */
u32 cmd52rd; /* 0x110, rev8 */
u32 cmd52wr; /* rev8 */
u32 cmd53rd; /* rev8 */
u32 cmd53wr; /* rev8 */
u32 abort; /* rev8 */
u32 datacrcerror; /* rev8 */
u32 rdoutofsync; /* rev8 */
u32 wroutofsync; /* rev8 */
u32 writebusy; /* rev8 */
u32 readwait; /* rev8 */
u32 readterm; /* rev8 */
u32 writeterm; /* rev8 */
u32 PAD[40];
u32 clockctlstatus; /* rev8 */
u32 PAD[7];
u32 PAD[128]; /* DMA engines */
/* SDIO/PCMCIA CIS region */
char cis[512]; /* 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* 0x600-6ff, rev6 */
u16 PAD[55];
/* PCMCIA backplane access */
u16 backplanecsr; /* 0x76E, rev6 */
u16 backplaneaddr0; /* rev6 */
u16 backplaneaddr1; /* rev6 */
u16 backplaneaddr2; /* rev6 */
u16 backplaneaddr3; /* rev6 */
u16 backplanedata0; /* rev6 */
u16 backplanedata1; /* rev6 */
u16 backplanedata2; /* rev6 */
u16 backplanedata3; /* rev6 */
u16 PAD[31];
/* sprom "size" & "blank" info */
u16 spromstatus; /* 0x7BE, rev2 */
u32 PAD[464];
u16 PAD[0x80];
};
#endif /* _SBSDIO_H */

27
drivers/staging/brcm80211/include/bcmsdh.h → drivers/staging/brcm80211/brcmfmac/sdio_host.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsdh_h_
#define _bcmsdh_h_
#ifndef _BRCM_SDH_H_
#define _BRCM_SDH_H_
#include <linux/skbuff.h>
#define BCMSDH_ERROR_VAL 0x0001 /* Error */
@ -38,6 +38,27 @@ extern const uint bcmsdh_msglevel;
#define BCMSDH_INFO(x)
#endif /* BCMDBG */
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIOD_FBR_SIZE 0x100
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02
#define SDIO_FUNC_ENABLE_2 0x04
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02
#define SDIO_FUNC_READY_2 0x04
/* intr_status */
#define INTR_STATUS_FUNC1 0x2
#define INTR_STATUS_FUNC2 0x4
/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS 7
/* forward declarations */
typedef struct bcmsdh_info bcmsdh_info_t;
typedef void (*bcmsdh_cb_fn_t) (void *);
@ -202,4 +223,4 @@ extern u32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev);
#endif /* _bcmsdh_h_ */
#endif /* _BRCM_SDH_H_ */

63
drivers/staging/brcm80211/brcmfmac/sdioh.h
View File

@ -1,63 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SDIOH_H
#define _SDIOH_H
#define SD_SysAddr 0x000
#define SD_BlockSize 0x004
#define SD_BlockCount 0x006
#define SD_Arg0 0x008
#define SD_Arg1 0x00A
#define SD_TransferMode 0x00C
#define SD_Command 0x00E
#define SD_Response0 0x010
#define SD_Response1 0x012
#define SD_Response2 0x014
#define SD_Response3 0x016
#define SD_Response4 0x018
#define SD_Response5 0x01A
#define SD_Response6 0x01C
#define SD_Response7 0x01E
#define SD_BufferDataPort0 0x020
#define SD_BufferDataPort1 0x022
#define SD_PresentState 0x024
#define SD_HostCntrl 0x028
#define SD_PwrCntrl 0x029
#define SD_BlockGapCntrl 0x02A
#define SD_WakeupCntrl 0x02B
#define SD_ClockCntrl 0x02C
#define SD_TimeoutCntrl 0x02E
#define SD_SoftwareReset 0x02F
#define SD_IntrStatus 0x030
#define SD_ErrorIntrStatus 0x032
#define SD_IntrStatusEnable 0x034
#define SD_ErrorIntrStatusEnable 0x036
#define SD_IntrSignalEnable 0x038
#define SD_ErrorIntrSignalEnable 0x03A
#define SD_CMD12ErrorStatus 0x03C
#define SD_Capabilities 0x040
#define SD_Capabilities_Reserved 0x044
#define SD_MaxCurCap 0x048
#define SD_MaxCurCap_Reserved 0x04C
#define SD_ADMA_SysAddr 0x58
#define SD_SlotInterruptStatus 0x0FC
#define SD_HostControllerVersion 0x0FE
/* SD specific registers in PCI config space */
#define SD_SlotInfo 0x40
#endif /* _SDIOH_H */

48
drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
View File

@ -16,15 +16,16 @@
#include <linux/kernel.h>
#include <linux/if_arp.h>
#include <linux/sched.h>
#include <bcmutils.h>
#include <brcmu_utils.h>
#include <defs.h>
#include <brcmu_wifi.h>
#include <asm/uaccess.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhdioctl.h>
#include <wlioctl.h>
#include <linux/kthread.h>
#include <linux/netdevice.h>
@ -45,7 +46,7 @@ static struct sdio_func *cfg80211_sdio_func;
static struct wl_dev *wl_cfg80211_dev;
static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
u32 wl_dbg_level = WL_DBG_ERR;
u32 brcmf_dbg_level = WL_DBG_ERR;
#define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4.bin"
#define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4.txt"
@ -643,7 +644,7 @@ wl_dev_iovar_setbuf(struct net_device *dev, s8 * iovar, void *param,
{
s32 iolen;
iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
BUG_ON(!iolen);
return wl_dev_ioctl(dev, WLC_SET_VAR, bufptr, iolen);
@ -655,7 +656,7 @@ wl_dev_iovar_getbuf(struct net_device *dev, s8 * iovar, void *param,
{
s32 iolen;
iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
BUG_ON(!iolen);
return wl_dev_ioctl(dev, WLC_GET_VAR, bufptr, buflen);
@ -843,7 +844,8 @@ static s32 wl_dev_intvar_set(struct net_device *dev, s8 *name, s32 val)
s32 err = 0;
val = cpu_to_le32(val);
len = bcm_mkiovar(name, (char *)(&val), sizeof(val), buf, sizeof(buf));
len = brcmu_mkiovar(name, (char *)(&val), sizeof(val), buf,
sizeof(buf));
BUG_ON(!len);
err = wl_dev_ioctl(dev, WLC_SET_VAR, buf, len);
@ -865,7 +867,7 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, s32 *retval)
s32 err = 0;
len =
bcm_mkiovar(name, (char *)(&data_null), 0, (char *)(&var),
brcmu_mkiovar(name, (char *)(&data_null), 0, (char *)(&var),
sizeof(var.buf));
BUG_ON(!len);
err = wl_dev_ioctl(dev, WLC_GET_VAR, &var, len);
@ -1518,7 +1520,7 @@ wl_cfg80211_set_tx_power(struct wiphy *wiphy,
else
txpwrmw = (u16) dbm;
err = wl_dev_intvar_set(ndev, "qtxpower",
(s32) (bcm_mw_to_qdbm(txpwrmw)));
(s32) (brcmu_mw_to_qdbm(txpwrmw)));
if (unlikely(err))
WL_ERR("qtxpower error (%d)\n", err);
wl->conf->tx_power = dbm;
@ -1546,7 +1548,7 @@ static s32 wl_cfg80211_get_tx_power(struct wiphy *wiphy, s32 *dbm)
}
result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
*dbm = (s32) bcm_qdbm_to_mw(result);
*dbm = (s32) brcmu_qdbm_to_mw(result);
done:
WL_TRACE("Exit\n");
@ -2668,7 +2670,7 @@ wl_dev_bufvar_set(struct net_device *dev, s8 *name, s8 *buf, s32 len)
struct wl_priv *wl = ndev_to_wl(dev);
u32 buflen;
buflen = bcm_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
buflen = brcmu_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
BUG_ON(!buflen);
return wl_dev_ioctl(dev, WLC_SET_VAR, wl->ioctl_buf, buflen);
@ -2682,7 +2684,7 @@ wl_dev_bufvar_get(struct net_device *dev, s8 *name, s8 *buf,
u32 len;
s32 err = 0;
len = bcm_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
len = brcmu_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
BUG_ON(!len);
err = wl_dev_ioctl(dev, WLC_GET_VAR, (void *)wl->ioctl_buf,
WL_IOCTL_LEN_MAX);
@ -2800,7 +2802,7 @@ static s32 wl_update_bss_info(struct wl_priv *wl)
{
struct wl_bss_info *bi;
struct wlc_ssid *ssid;
struct bcm_tlv *tim;
struct brcmu_tlv *tim;
u16 beacon_interval;
u8 dtim_period;
size_t ie_len;
@ -2830,7 +2832,7 @@ static s32 wl_update_bss_info(struct wl_priv *wl)
ie_len = bi->ie_length;
beacon_interval = cpu_to_le16(bi->beacon_period);
tim = bcm_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
tim = brcmu_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
if (tim)
dtim_period = tim->data[1];
else {
@ -3681,7 +3683,7 @@ wl_dongle_glom(struct net_device *ndev, u32 glom, u32 dongle_align)
s32 err = 0;
/* Match Host and Dongle rx alignment */
bcm_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
brcmu_mkiovar("bus:txglomalign", (char *)&dongle_align, 4, iovbuf,
sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {
@ -3689,7 +3691,7 @@ wl_dongle_glom(struct net_device *ndev, u32 glom, u32 dongle_align)
goto dongle_glom_out;
}
/* disable glom option per default */
bcm_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("bus:txglom", (char *)&glom, 4, iovbuf, sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {
WL_ERR("txglom error (%d)\n", err);
@ -3707,7 +3709,7 @@ wl_dongle_offload(struct net_device *ndev, s32 arpoe, s32 arp_ol)
s32 err = 0;
/* Set ARP offload */
bcm_mkiovar("arpoe", (char *)&arpoe, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("arpoe", (char *)&arpoe, 4, iovbuf, sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (err) {
if (err == -EOPNOTSUPP)
@ -3717,7 +3719,7 @@ wl_dongle_offload(struct net_device *ndev, s32 arpoe, s32 arp_ol)
goto dongle_offload_out;
}
bcm_mkiovar("arp_ol", (char *)&arp_ol, 4, iovbuf, sizeof(iovbuf));
brcmu_mkiovar("arp_ol", (char *)&arp_ol, 4, iovbuf, sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (err) {
if (err == -EOPNOTSUPP)
@ -3830,7 +3832,7 @@ static s32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode)
}
/* set mode to allow pattern */
bcm_mkiovar("pkt_filter_mode", (char *)&filter_mode, 4, iovbuf,
brcmu_mkiovar("pkt_filter_mode", (char *)&filter_mode, 4, iovbuf,
sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (err) {
@ -3857,7 +3859,7 @@ static s32 wl_dongle_eventmsg(struct net_device *ndev)
WL_TRACE("Enter\n");
/* Setup event_msgs */
bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
brcmu_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_GET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {
@ -3886,7 +3888,7 @@ static s32 wl_dongle_eventmsg(struct net_device *ndev)
setbit(eventmask, WLC_E_JOIN_START);
setbit(eventmask, WLC_E_SCAN_COMPLETE);
bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
brcmu_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {
@ -3912,7 +3914,7 @@ wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
* off to report link down
*/
if (roamvar) {
bcm_mkiovar("bcn_timeout", (char *)&bcn_timeout,
brcmu_mkiovar("bcn_timeout", (char *)&bcn_timeout,
sizeof(bcn_timeout), iovbuf, sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {
@ -3926,7 +3928,7 @@ wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
* to take care of roaming
*/
WL_INFO("Internal Roaming = %s\n", roamvar ? "Off" : "On");
bcm_mkiovar("roam_off", (char *)&roamvar,
brcmu_mkiovar("roam_off", (char *)&roamvar,
sizeof(roamvar), iovbuf, sizeof(iovbuf));
err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
if (unlikely(err)) {

15
drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
View File

@ -17,11 +17,6 @@
#ifndef _wl_cfg80211_h_
#define _wl_cfg80211_h_
#include <linux/wireless.h>
#include <linux/wireless.h>
#include <net/cfg80211.h>
#include <wlioctl.h>
struct wl_conf;
struct wl_iface;
struct wl_priv;
@ -39,7 +34,7 @@ struct wl_ibss;
#define WL_ERR(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_ERR) { \
if (brcmf_dbg_level & WL_DBG_ERR) { \
if (net_ratelimit()) { \
printk(KERN_ERR "ERROR @%s : " fmt, \
__func__, ##args); \
@ -50,7 +45,7 @@ do { \
#if (defined BCMDBG)
#define WL_INFO(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_INFO) { \
if (brcmf_dbg_level & WL_DBG_INFO) { \
if (net_ratelimit()) { \
printk(KERN_ERR "INFO @%s : " fmt, \
__func__, ##args); \
@ -60,7 +55,7 @@ do { \
#define WL_TRACE(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_TRACE) { \
if (brcmf_dbg_level & WL_DBG_TRACE) { \
if (net_ratelimit()) { \
printk(KERN_ERR "TRACE @%s : " fmt, \
__func__, ##args); \
@ -70,7 +65,7 @@ do { \
#define WL_SCAN(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_SCAN) { \
if (brcmf_dbg_level & WL_DBG_SCAN) { \
if (net_ratelimit()) { \
printk(KERN_ERR "SCAN @%s : " fmt, \
__func__, ##args); \
@ -80,7 +75,7 @@ do { \
#define WL_CONN(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_CONN) { \
if (brcmf_dbg_level & WL_DBG_CONN) { \
if (net_ratelimit()) { \
printk(KERN_ERR "CONN @%s : " fmt, \
__func__, ##args); \

66
drivers/staging/brcm80211/brcmfmac/wl_iw.c
View File

@ -16,25 +16,30 @@
#include <linux/kthread.h>
#include <linux/semaphore.h>
#include <bcmdefs.h>
#include <defs.h>
#include <linux/netdevice.h>
#include <wlioctl.h>
#include <linux/etherdevice.h>
#include <linux/wireless.h>
#include <bcmutils.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <linux/if_arp.h>
#include <asm/uaccess.h>
#include <dngl_stats.h>
#include <dhd.h>
#include <dhdioctl.h>
#include <linux/ieee80211.h>
typedef const struct si_pub si_t;
#include <wlioctl.h>
struct si_pub;
#include <dngl_stats.h>
#include <dhd.h>
#define WPA_OUI "\x00\x50\xF2"
#define DOT11_MNG_RSN_ID 48
#define DOT11_MNG_WPA_ID 221
#define WL_ERROR(fmt, args...) printk(fmt, ##args)
#define WL_TRACE(fmt, args...) no_printk(fmt, ##args)
#define WL_INFORM(fmt, args...) no_printk(fmt, ##args)
@ -113,6 +118,24 @@ typedef struct iscan_info {
} iscan_info_t;
iscan_info_t *g_iscan;
typedef enum sup_auth_status {
WLC_SUP_DISCONNECTED = 0,
WLC_SUP_CONNECTING,
WLC_SUP_IDREQUIRED,
WLC_SUP_AUTHENTICATING,
WLC_SUP_AUTHENTICATED,
WLC_SUP_KEYXCHANGE,
WLC_SUP_KEYED,
WLC_SUP_TIMEOUT,
WLC_SUP_LAST_BASIC_STATE,
WLC_SUP_KEYXCHANGE_WAIT_M1 = WLC_SUP_AUTHENTICATED,
WLC_SUP_KEYXCHANGE_PREP_M2 = WLC_SUP_KEYXCHANGE,
WLC_SUP_KEYXCHANGE_WAIT_M3 = WLC_SUP_LAST_BASIC_STATE,
WLC_SUP_KEYXCHANGE_PREP_M4,
WLC_SUP_KEYXCHANGE_WAIT_G1,
WLC_SUP_KEYXCHANGE_PREP_G2
} sup_auth_status_t;
static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
/* Global ASSERT type flag */
@ -205,7 +228,8 @@ static int dev_wlc_intvar_set(struct net_device *dev, char *name, int val)
uint len;
val = cpu_to_le32(val);
len = bcm_mkiovar(name, (char *)(&val), sizeof(val), buf, sizeof(buf));
len = brcmu_mkiovar(name, (char *)(&val), sizeof(val), buf,
sizeof(buf));
ASSERT(len);
return dev_wlc_ioctl(dev, WLC_SET_VAR, buf, len);
@ -219,7 +243,7 @@ dev_iw_iovar_setbuf(struct net_device *dev,
{
int iolen;
iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
ASSERT(iolen);
if (iolen == 0)
@ -235,7 +259,7 @@ dev_iw_iovar_getbuf(struct net_device *dev,
{
int iolen;
iolen = bcm_mkiovar(iovar, param, paramlen, bufptr, buflen);
iolen = brcmu_mkiovar(iovar, param, paramlen, bufptr, buflen);
ASSERT(iolen);
return dev_wlc_ioctl(dev, WLC_GET_VAR, bufptr, buflen);
@ -249,7 +273,7 @@ dev_wlc_bufvar_set(struct net_device *dev, char *name, char *buf, int len)
static char ioctlbuf[MAX_WLIW_IOCTL_LEN];
uint buflen;
buflen = bcm_mkiovar(name, buf, len, ioctlbuf, sizeof(ioctlbuf));
buflen = brcmu_mkiovar(name, buf, len, ioctlbuf, sizeof(ioctlbuf));
ASSERT(buflen);
return dev_wlc_ioctl(dev, WLC_SET_VAR, ioctlbuf, buflen);
@ -263,7 +287,7 @@ dev_wlc_bufvar_get(struct net_device *dev, char *name, char *buf, int buflen)
int error;
uint len;
len = bcm_mkiovar(name, NULL, 0, ioctlbuf, sizeof(ioctlbuf));
len = brcmu_mkiovar(name, NULL, 0, ioctlbuf, sizeof(ioctlbuf));
ASSERT(len);
error =
dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)ioctlbuf,
@ -286,7 +310,7 @@ static int dev_wlc_intvar_get(struct net_device *dev, char *name, int *retval)
uint data_null;
len =
bcm_mkiovar(name, (char *)(&data_null), 0, (char *)(&var),
brcmu_mkiovar(name, (char *)(&data_null), 0, (char *)(&var),
sizeof(var.buf));
ASSERT(len);
error = dev_wlc_ioctl(dev, WLC_GET_VAR, (void *)&var, len);
@ -371,7 +395,7 @@ wl_iw_set_freq(struct net_device *dev,
if (fwrq->m > 4000 && fwrq->m < 5000)
sf = WF_CHAN_FACTOR_4_G;
chan = bcm_mhz2channel(fwrq->m, sf);
chan = brcmu_mhz2channel(fwrq->m, sf);
}
chan = cpu_to_le32(chan);
@ -1422,11 +1446,11 @@ wl_iw_handle_scanresults_ies(char **event_p, char *end,
event = *event_p;
if (bi->ie_length) {
bcm_tlv_t *ie;
struct brcmu_tlv *ie;
u8 *ptr = ((u8 *) bi) + sizeof(wl_bss_info_t);
int ptr_len = bi->ie_length;
ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_RSN_ID);
ie = brcmu_parse_tlvs(ptr, ptr_len, DOT11_MNG_RSN_ID);
if (ie) {
iwe.cmd = IWEVGENIE;
iwe.u.data.length = ie->len + 2;
@ -1436,7 +1460,8 @@ wl_iw_handle_scanresults_ies(char **event_p, char *end,
}
ptr = ((u8 *) bi) + sizeof(wl_bss_info_t);
while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
while ((ie = brcmu_parse_tlvs(
ptr, ptr_len, DOT11_MNG_WPA_ID))) {
if (ie_is_wps_ie(((u8 **)&ie), &ptr, &ptr_len)) {
iwe.cmd = IWEVGENIE;
iwe.u.data.length = ie->len + 2;
@ -1449,7 +1474,8 @@ wl_iw_handle_scanresults_ies(char **event_p, char *end,
ptr = ((u8 *) bi) + sizeof(wl_bss_info_t);
ptr_len = bi->ie_length;
while ((ie = bcm_parse_tlvs(ptr, ptr_len, DOT11_MNG_WPA_ID))) {
while ((ie = brcmu_parse_tlvs(
ptr, ptr_len, DOT11_MNG_WPA_ID))) {
if (ie_is_wpa_ie(((u8 **)&ie), &ptr, &ptr_len)) {
iwe.cmd = IWEVGENIE;
iwe.u.data.length = ie->len + 2;
@ -2174,8 +2200,8 @@ wl_iw_set_txpow(struct net_device *dev,
else
txpwrmw = (u16) vwrq->value;
error =
dev_wlc_intvar_set(dev, "qtxpower", (int)(bcm_mw_to_qdbm(txpwrmw)));
error = dev_wlc_intvar_set(dev, "qtxpower",
(int)(brcmu_mw_to_qdbm(txpwrmw)));
return error;
}
@ -2199,7 +2225,7 @@ wl_iw_get_txpow(struct net_device *dev,
disable = le32_to_cpu(disable);
result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
vwrq->value = (s32) bcm_qdbm_to_mw(result);
vwrq->value = (s32) brcmu_qdbm_to_mw(result);
vwrq->fixed = 0;
vwrq->disabled =
(disable & (WL_RADIO_SW_DISABLE | WL_RADIO_HW_DISABLE)) ? 1 : 0;

4
drivers/staging/brcm80211/brcmfmac/wl_iw.h
View File

@ -17,10 +17,6 @@
#ifndef _wl_iw_h_
#define _wl_iw_h_
#include <linux/wireless.h>
#include <wlioctl.h>
#define WL_SCAN_PARAMS_SSID_MAX 10
#define GET_SSID "SSID="
#define GET_CHANNEL "CH="

45
drivers/staging/brcm80211/brcmsmac/Makefile
View File

@ -28,30 +28,29 @@ ccflags-y := \
-Idrivers/staging/brcm80211/include
BRCMSMAC_OFILES := \
wl_mac80211.o \
wl_ucode_loader.o \
wlc_alloc.o \
wlc_ampdu.o \
wlc_antsel.o \
wlc_bmac.o \
wlc_channel.o \
wlc_main.o \
wlc_phy_shim.o \
wlc_pmu.o \
wlc_rate.o \
wlc_stf.o \
mac80211_if.o \
ucode_loader.o \
alloc.o \
ampdu.o \
antsel.o \
bmac.o \
channel.o \
main.o \
phy_shim.o \
pmu.o \
rate.o \
stf.o \
aiutils.o \
phy/wlc_phy_cmn.o \
phy/wlc_phy_lcn.o \
phy/wlc_phy_n.o \
phy/wlc_phytbl_lcn.o \
phy/wlc_phytbl_n.o \
phy/wlc_phy_qmath.o \
bcmotp.o \
bcmsrom.o \
hnddma.o \
nicpci.o \
nvram.o
phy/phy_cmn.o \
phy/phy_lcn.o \
phy/phy_n.o \
phy/phytbl_lcn.o \
phy/phytbl_n.o \
phy/phy_qmath.o \
otp.o \
srom.o \
dma.o \
nicpci.o
MODULEPFX := brcmsmac

508
drivers/staging/brcm80211/brcmsmac/aiutils.c
View File

@ -17,32 +17,357 @@
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <bcmdefs.h>
#include <defs.h>
#include "types.h"
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmutils.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <bcmdevs.h>
#include <soc.h>
#include <chipcommon.h>
#include <brcm_hw_ids.h>
/* ********** from siutils.c *********** */
#include <pci_core.h>
#include <pcie_core.h>
#include <nicpci.h>
#include <bcmnvram.h>
#include <bcmsrom.h>
#include <wlc_pmu.h>
#include "srom.h"
#include <pmu.h>
#include <scb.h>
#include <pub.h>
/* slow_clk_ctl */
#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
* 0: LPO is enabled
*/
#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
* 0: power logic control
*/
#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
* PLL clock disable requests from core
*/
#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
* disable crystal when appropriate
*/
#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
#define SCC_CD_SHIFT 16
/* system_clk_ctl */
#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
#define SYCC_FP 0x00000004 /* ForcePLLOn */
#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
#define SYCC_HR 0x00000010 /* Force HT */
#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
#define SYCC_CD_SHIFT 16
#define CST4329_SPROM_OTP_SEL_MASK 0x00000003
#define CST4329_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
#define CST4329_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
#define CST4329_OTP_SEL 2 /* OTP is powered up, no SPROM */
#define CST4329_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
#define CST4329_SPI_SDIO_MODE_MASK 0x00000004
#define CST4329_SPI_SDIO_MODE_SHIFT 2
/* 43224 chip-specific ChipControl register bits */
#define CCTRL43224_GPIO_TOGGLE 0x8000
#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
/* 43236 Chip specific ChipStatus register bits */
#define CST43236_SFLASH_MASK 0x00000040
#define CST43236_OTP_MASK 0x00000080
#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
#define CST43236_BOOT_MASK 0x00001800
#define CST43236_BOOT_SHIFT 11
#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
#define CST43236_BOOT_FROM_INVALID 3
/* 4331 chip-specific ChipControl register bits */
#define CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
#define CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
#define CCTRL4331_EXT_LNA (1<<2) /* 0 disable */
#define CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */
#define CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */
#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */
#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */
#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */
#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */
#define CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */
#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */
#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */
#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */
/* 4331 Chip specific ChipStatus register bits */
#define CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
#define CST4331_SPROM_PRESENT 0x00000002
#define CST4331_OTP_PRESENT 0x00000004
#define CST4331_LDO_RF 0x00000008
#define CST4331_LDO_PAR 0x00000010
/* 4319 chip-specific ChipStatus register bits */
#define CST4319_SPI_CPULESSUSB 0x00000001
#define CST4319_SPI_CLK_POL 0x00000002
#define CST4319_SPI_CLK_PH 0x00000008
#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /* gpio [7:6], SDIO CIS selection */
#define CST4319_SPROM_OTP_SEL_SHIFT 6
#define CST4319_DEFCIS_SEL 0x00000000 /* use default CIS, OTP is powered up */
#define CST4319_SPROM_SEL 0x00000040 /* use SPROM, OTP is powered up */
#define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */
#define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */
#define CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
#define CST4319_REMAP_SEL_MASK 0x00000600
#define CST4319_ILPDIV_EN 0x00000800
#define CST4319_XTAL_PD_POL 0x00001000
#define CST4319_LPO_SEL 0x00002000
#define CST4319_RES_INIT_MODE 0x0000c000
#define CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
#define CST4319_CBUCK_MODE_MASK 0x00060000
#define CST4319_CBUCK_MODE_BURST 0x00020000
#define CST4319_CBUCK_MODE_LPBURST 0x00060000
#define CST4319_RCAL_VALID 0x01000000
#define CST4319_RCAL_VALUE_MASK 0x3e000000
#define CST4319_RCAL_VALUE_SHIFT 25
/* 4336 chip-specific ChipStatus register bits */
#define CST4336_SPI_MODE_MASK 0x00000001
#define CST4336_SPROM_PRESENT 0x00000002
#define CST4336_OTP_PRESENT 0x00000004
#define CST4336_ARMREMAP_0 0x00000008
#define CST4336_ILPDIV_EN_MASK 0x00000010
#define CST4336_ILPDIV_EN_SHIFT 4
#define CST4336_XTAL_PD_POL_MASK 0x00000020
#define CST4336_XTAL_PD_POL_SHIFT 5
#define CST4336_LPO_SEL_MASK 0x00000040
#define CST4336_LPO_SEL_SHIFT 6
#define CST4336_RES_INIT_MODE_MASK 0x00000180
#define CST4336_RES_INIT_MODE_SHIFT 7
#define CST4336_CBUCK_MODE_MASK 0x00000600
#define CST4336_CBUCK_MODE_SHIFT 9
/* 4313 chip-specific ChipStatus register bits */
#define CST4313_SPROM_PRESENT 1
#define CST4313_OTP_PRESENT 2
#define CST4313_SPROM_OTP_SEL_MASK 0x00000002
#define CST4313_SPROM_OTP_SEL_SHIFT 0
/* 4313 Chip specific ChipControl register bits */
#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
(sih->chiprev == 0) && \
(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
/* Manufacturer Ids */
#define MFGID_ARM 0x43b
#define MFGID_BRCM 0x4bf
#define MFGID_MIPS 0x4a7
/* Enumeration ROM registers */
#define ER_EROMENTRY 0x000
#define ER_REMAPCONTROL 0xe00
#define ER_REMAPSELECT 0xe04
#define ER_MASTERSELECT 0xe10
#define ER_ITCR 0xf00
#define ER_ITIP 0xf04
/* Erom entries */
#define ER_TAG 0xe
#define ER_TAG1 0x6
#define ER_VALID 1
#define ER_CI 0
#define ER_MP 2
#define ER_ADD 4
#define ER_END 0xe
#define ER_BAD 0xffffffff
/* EROM CompIdentA */
#define CIA_MFG_MASK 0xfff00000
#define CIA_MFG_SHIFT 20
#define CIA_CID_MASK 0x000fff00
#define CIA_CID_SHIFT 8
#define CIA_CCL_MASK 0x000000f0
#define CIA_CCL_SHIFT 4
/* EROM CompIdentB */
#define CIB_REV_MASK 0xff000000
#define CIB_REV_SHIFT 24
#define CIB_NSW_MASK 0x00f80000
#define CIB_NSW_SHIFT 19
#define CIB_NMW_MASK 0x0007c000
#define CIB_NMW_SHIFT 14
#define CIB_NSP_MASK 0x00003e00
#define CIB_NSP_SHIFT 9
#define CIB_NMP_MASK 0x000001f0
#define CIB_NMP_SHIFT 4
/* EROM AddrDesc */
#define AD_ADDR_MASK 0xfffff000
#define AD_SP_MASK 0x00000f00
#define AD_SP_SHIFT 8
#define AD_ST_MASK 0x000000c0
#define AD_ST_SHIFT 6
#define AD_ST_SLAVE 0x00000000
#define AD_ST_BRIDGE 0x00000040
#define AD_ST_SWRAP 0x00000080
#define AD_ST_MWRAP 0x000000c0
#define AD_SZ_MASK 0x00000030
#define AD_SZ_SHIFT 4
#define AD_SZ_4K 0x00000000
#define AD_SZ_8K 0x00000010
#define AD_SZ_16K 0x00000020
#define AD_SZ_SZD 0x00000030
#define AD_AG32 0x00000008
#define AD_ADDR_ALIGN 0x00000fff
#define AD_SZ_BASE 0x00001000 /* 4KB */
/* EROM SizeDesc */
#define SD_SZ_MASK 0xfffff000
#define SD_SG32 0x00000008
#define SD_SZ_ALIGN 0x00000fff
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
/* power control defines */
#define PLL_DELAY 150 /* us pll on delay */
#define FREF_DELAY 200 /* us fref change delay */
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
/* resetctrl */
#define AIRC_RESET 1
typedef volatile struct _aidmp {
u32 oobselina30; /* 0x000 */
u32 oobselina74; /* 0x004 */
u32 PAD[6];
u32 oobselinb30; /* 0x020 */
u32 oobselinb74; /* 0x024 */
u32 PAD[6];
u32 oobselinc30; /* 0x040 */
u32 oobselinc74; /* 0x044 */
u32 PAD[6];
u32 oobselind30; /* 0x060 */
u32 oobselind74; /* 0x064 */
u32 PAD[38];
u32 oobselouta30; /* 0x100 */
u32 oobselouta74; /* 0x104 */
u32 PAD[6];
u32 oobseloutb30; /* 0x120 */
u32 oobseloutb74; /* 0x124 */
u32 PAD[6];
u32 oobseloutc30; /* 0x140 */
u32 oobseloutc74; /* 0x144 */
u32 PAD[6];
u32 oobseloutd30; /* 0x160 */
u32 oobseloutd74; /* 0x164 */
u32 PAD[38];
u32 oobsynca; /* 0x200 */
u32 oobseloutaen; /* 0x204 */
u32 PAD[6];
u32 oobsyncb; /* 0x220 */
u32 oobseloutben; /* 0x224 */
u32 PAD[6];
u32 oobsyncc; /* 0x240 */
u32 oobseloutcen; /* 0x244 */
u32 PAD[6];
u32 oobsyncd; /* 0x260 */
u32 oobseloutden; /* 0x264 */
u32 PAD[38];
u32 oobaextwidth; /* 0x300 */
u32 oobainwidth; /* 0x304 */
u32 oobaoutwidth; /* 0x308 */
u32 PAD[5];
u32 oobbextwidth; /* 0x320 */
u32 oobbinwidth; /* 0x324 */
u32 oobboutwidth; /* 0x328 */
u32 PAD[5];
u32 oobcextwidth; /* 0x340 */
u32 oobcinwidth; /* 0x344 */
u32 oobcoutwidth; /* 0x348 */
u32 PAD[5];
u32 oobdextwidth; /* 0x360 */
u32 oobdinwidth; /* 0x364 */
u32 oobdoutwidth; /* 0x368 */
u32 PAD[37];
u32 ioctrlset; /* 0x400 */
u32 ioctrlclear; /* 0x404 */
u32 ioctrl; /* 0x408 */
u32 PAD[61];
u32 iostatus; /* 0x500 */
u32 PAD[127];
u32 ioctrlwidth; /* 0x700 */
u32 iostatuswidth; /* 0x704 */
u32 PAD[62];
u32 resetctrl; /* 0x800 */
u32 resetstatus; /* 0x804 */
u32 resetreadid; /* 0x808 */
u32 resetwriteid; /* 0x80c */
u32 PAD[60];
u32 errlogctrl; /* 0x900 */
u32 errlogdone; /* 0x904 */
u32 errlogstatus; /* 0x908 */
u32 errlogaddrlo; /* 0x90c */
u32 errlogaddrhi; /* 0x910 */
u32 errlogid; /* 0x914 */
u32 errloguser; /* 0x918 */
u32 errlogflags; /* 0x91c */
u32 PAD[56];
u32 intstatus; /* 0xa00 */
u32 PAD[127];
u32 config; /* 0xe00 */
u32 PAD[63];
u32 itcr; /* 0xf00 */
u32 PAD[3];
u32 itipooba; /* 0xf10 */
u32 itipoobb; /* 0xf14 */
u32 itipoobc; /* 0xf18 */
u32 itipoobd; /* 0xf1c */
u32 PAD[4];
u32 itipoobaout; /* 0xf30 */
u32 itipoobbout; /* 0xf34 */
u32 itipoobcout; /* 0xf38 */
u32 itipoobdout; /* 0xf3c */
u32 PAD[4];
u32 itopooba; /* 0xf50 */
u32 itopoobb; /* 0xf54 */
u32 itopoobc; /* 0xf58 */
u32 itopoobd; /* 0xf5c */
u32 PAD[4];
u32 itopoobain; /* 0xf70 */
u32 itopoobbin; /* 0xf74 */
u32 itopoobcin; /* 0xf78 */
u32 itopoobdin; /* 0xf7c */
u32 PAD[4];
u32 itopreset; /* 0xf90 */
u32 PAD[15];
u32 peripherialid4; /* 0xfd0 */
u32 peripherialid5; /* 0xfd4 */
u32 peripherialid6; /* 0xfd8 */
u32 peripherialid7; /* 0xfdc */
u32 peripherialid0; /* 0xfe0 */
u32 peripherialid1; /* 0xfe4 */
u32 peripherialid2; /* 0xfe8 */
u32 peripherialid3; /* 0xfec */
u32 componentid0; /* 0xff0 */
u32 componentid1; /* 0xff4 */
u32 componentid2; /* 0xff8 */
u32 componentid3; /* 0xffc */
} aidmp_t;
/* EROM parsing */
static u32
get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
get_erom_ent(struct si_pub *sih, u32 **eromptr, u32 mask, u32 match)
{
u32 ent;
uint inv = 0, nom = 0;
@ -77,7 +402,7 @@ get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
}
static u32
get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
get_asd(struct si_pub *sih, u32 **eromptr, uint sp, uint ad, uint st,
u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
{
u32 asd, sz, szd;
@ -116,7 +441,7 @@ static void ai_hwfixup(si_info_t *sii)
}
/* parse the enumeration rom to identify all cores */
void ai_scan(si_t *sih, void *regs, uint devid)
void ai_scan(struct si_pub *sih, void *regs, uint devid)
{
si_info_t *sii = SI_INFO(sih);
chipcregs_t *cc = (chipcregs_t *) regs;
@ -319,7 +644,7 @@ void ai_scan(si_t *sih, void *regs, uint devid)
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
void *ai_setcoreidx(si_t *sih, uint coreidx)
void *ai_setcoreidx(struct si_pub *sih, uint coreidx)
{
si_info_t *sii = SI_INFO(sih);
u32 addr = sii->coresba[coreidx];
@ -368,13 +693,13 @@ void *ai_setcoreidx(si_t *sih, uint coreidx)
}
/* Return the number of address spaces in current core */
int ai_numaddrspaces(si_t *sih)
int ai_numaddrspaces(struct si_pub *sih)
{
return 2;
}
/* Return the address of the nth address space in the current core */
u32 ai_addrspace(si_t *sih, uint asidx)
u32 ai_addrspace(struct si_pub *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@ -393,7 +718,7 @@ u32 ai_addrspace(si_t *sih, uint asidx)
}
/* Return the size of the nth address space in the current core */
u32 ai_addrspacesize(si_t *sih, uint asidx)
u32 ai_addrspacesize(struct si_pub *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@ -411,7 +736,7 @@ u32 ai_addrspacesize(si_t *sih, uint asidx)
}
}
uint ai_flag(si_t *sih)
uint ai_flag(struct si_pub *sih)
{
si_info_t *sii;
aidmp_t *ai;
@ -426,11 +751,11 @@ uint ai_flag(si_t *sih)
return R_REG(&ai->oobselouta30) & 0x1f;
}
void ai_setint(si_t *sih, int siflag)
void ai_setint(struct si_pub *sih, int siflag)
{
}
uint ai_corevendor(si_t *sih)
uint ai_corevendor(struct si_pub *sih)
{
si_info_t *sii;
u32 cia;
@ -440,7 +765,7 @@ uint ai_corevendor(si_t *sih)
return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
}
uint ai_corerev(si_t *sih)
uint ai_corerev(struct si_pub *sih)
{
si_info_t *sii;
u32 cib;
@ -450,7 +775,7 @@ uint ai_corerev(si_t *sih)
return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
}
bool ai_iscoreup(si_t *sih)
bool ai_iscoreup(struct si_pub *sih)
{
si_info_t *sii;
aidmp_t *ai;
@ -463,7 +788,7 @@ bool ai_iscoreup(si_t *sih)
&& ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
}
void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
@ -485,7 +810,7 @@ void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
}
}
u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
@ -508,7 +833,7 @@ u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
return R_REG(&ai->ioctrl);
}
u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val)
{
si_info_t *sii;
aidmp_t *ai;
@ -542,7 +867,8 @@ static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
static void ai_nvram_process(si_info_t *sii, char *pvars);
/* dev path concatenation util */
static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name);
static char *ai_devpathvar(struct si_pub *sih, char *var, int len,
const char *name);
static bool _ai_clkctl_cc(si_info_t *sii, uint mode);
static bool ai_ispcie(si_info_t *sii);
@ -558,7 +884,7 @@ static u32 ai_gpioreservation;
* vars - pointer to a pointer area for "environment" variables
* varsz - pointer to int to return the size of the vars
*/
si_t *ai_attach(uint devid, void *regs, uint bustype,
struct si_pub *ai_attach(uint devid, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz)
{
si_info_t *sii;
@ -578,7 +904,7 @@ si_t *ai_attach(uint devid, void *regs, uint bustype,
sii->vars = vars ? *vars : NULL;
sii->varsz = varsz ? *varsz : 0;
return (si_t *) sii;
return (struct si_pub *) sii;
}
/* global kernel resource */
@ -859,9 +1185,6 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid,
udelay(10);
}
/* Init nvram from flash if it exists */
nvram_init();
/* Init nvram from sprom/otp if they exist */
if (srom_var_init
(&sii->pub, bustype, regs, vars, varsz)) {
@ -950,13 +1273,13 @@ static si_info_t *ai_doattach(si_info_t *sii, uint devid,
}
/* may be called with core in reset */
void ai_detach(si_t *sih)
void ai_detach(struct si_pub *sih)
{
si_info_t *sii;
uint idx;
struct si_pub *si_local = NULL;
bcopy(&sih, &si_local, sizeof(si_t **));
memcpy(&si_local, &sih, sizeof(struct si_pub **));
sii = SI_INFO(sih);
@ -970,8 +1293,6 @@ void ai_detach(si_t *sih)
sii->regs[idx] = NULL;
}
nvram_exit(); /* free up nvram buffers */
if (sih->bustype == PCI_BUS) {
if (sii->pch)
pcicore_deinit(sii->pch);
@ -984,7 +1305,8 @@ void ai_detach(si_t *sih)
/* register driver interrupt disabling and restoring callback functions */
void
ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg)
{
si_info_t *sii;
@ -1000,7 +1322,7 @@ ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
sii->dev_coreid = sii->coreid[sii->curidx];
}
void ai_deregister_intr_callback(si_t *sih)
void ai_deregister_intr_callback(struct si_pub *sih)
{
si_info_t *sii;
@ -1008,7 +1330,7 @@ void ai_deregister_intr_callback(si_t *sih)
sii->intrsoff_fn = NULL;
}
uint ai_coreid(si_t *sih)
uint ai_coreid(struct si_pub *sih)
{
si_info_t *sii;
@ -1016,7 +1338,7 @@ uint ai_coreid(si_t *sih)
return sii->coreid[sii->curidx];
}
uint ai_coreidx(si_t *sih)
uint ai_coreidx(struct si_pub *sih)
{
si_info_t *sii;
@ -1024,13 +1346,13 @@ uint ai_coreidx(si_t *sih)
return sii->curidx;
}
bool ai_backplane64(si_t *sih)
bool ai_backplane64(struct si_pub *sih)
{
return (sih->cccaps & CC_CAP_BKPLN64) != 0;
}
/* return index of coreid or BADIDX if not found */
uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit)
uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit)
{
si_info_t *sii;
uint found;
@ -1056,7 +1378,7 @@ uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit)
* Moreover, callers should keep interrupts off during switching
* out of and back to d11 core.
*/
void *ai_setcore(si_t *sih, uint coreid, uint coreunit)
void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit)
{
uint idx;
@ -1068,7 +1390,8 @@ void *ai_setcore(si_t *sih, uint coreid, uint coreunit)
}
/* Turn off interrupt as required by ai_setcore, before switch core */
void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
uint *intr_val)
{
void *cc;
si_info_t *sii;
@ -1093,7 +1416,7 @@ void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
}
/* restore coreidx and restore interrupt */
void ai_restore_core(si_t *sih, uint coreid, uint intr_val)
void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val)
{
si_info_t *sii;
@ -1106,7 +1429,7 @@ void ai_restore_core(si_t *sih, uint coreid, uint intr_val)
INTR_RESTORE(sii, intr_val);
}
void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val)
void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val)
{
si_info_t *sii = SI_INFO(sih);
u32 *w = (u32 *) sii->curwrap;
@ -1124,7 +1447,8 @@ void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val)
* Also, when using pci/pcie, we can optimize away the core switching for pci
* registers and (on newer pci cores) chipcommon registers.
*/
uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
uint val)
{
uint origidx = 0;
u32 *r = NULL;
@ -1208,7 +1532,7 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
return w;
}
void ai_core_disable(si_t *sih, u32 bits)
void ai_core_disable(struct si_pub *sih, u32 bits)
{
si_info_t *sii;
u32 dummy;
@ -1235,7 +1559,7 @@ void ai_core_disable(si_t *sih, u32 bits)
* bits - core specific bits that are set during and after reset sequence
* resetbits - core specific bits that are set only during reset sequence
*/
void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits)
{
si_info_t *sii;
aidmp_t *ai;
@ -1352,7 +1676,7 @@ static void ai_clkctl_setdelay(si_info_t *sii, void *chipcregs)
}
/* initialize power control delay registers */
void ai_clkctl_init(si_t *sih)
void ai_clkctl_init(struct si_pub *sih)
{
si_info_t *sii;
uint origidx = 0;
@ -1390,7 +1714,7 @@ void ai_clkctl_init(si_t *sih)
* return the value suitable for writing to the
* dot11 core FAST_PWRUP_DELAY register
*/
u16 ai_clkctl_fast_pwrup_delay(si_t *sih)
u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
{
si_info_t *sii;
uint origidx = 0;
@ -1438,7 +1762,7 @@ u16 ai_clkctl_fast_pwrup_delay(si_t *sih)
}
/* turn primary xtal and/or pll off/on */
int ai_clkctl_xtal(si_t *sih, uint what, bool on)
int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
{
si_info_t *sii;
u32 in, out, outen;
@ -1515,7 +1839,7 @@ int ai_clkctl_xtal(si_t *sih, uint what, bool on)
* this is a wrapper over the next internal function
* to allow flexible policy settings for outside caller
*/
bool ai_clkctl_cc(si_t *sih, uint mode)
bool ai_clkctl_cc(struct si_pub *sih, uint mode)
{
si_info_t *sii;
@ -1624,7 +1948,7 @@ static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
}
/* Build device path. Support SI, PCI, and JTAG for now. */
int ai_devpath(si_t *sih, char *path, int size)
int ai_devpath(struct si_pub *sih, char *path, int size)
{
int slen;
@ -1657,7 +1981,7 @@ int ai_devpath(si_t *sih, char *path, int size)
}
/* Get a variable, but only if it has a devpath prefix */
char *ai_getdevpathvar(si_t *sih, const char *name)
char *ai_getdevpathvar(struct si_pub *sih, const char *name)
{
char varname[SI_DEVPATH_BUFSZ + 32];
@ -1667,7 +1991,7 @@ char *ai_getdevpathvar(si_t *sih, const char *name)
}
/* Get a variable, but only if it has a devpath prefix */
int ai_getdevpathintvar(si_t *sih, const char *name)
int ai_getdevpathintvar(struct si_pub *sih, const char *name)
{
#if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
return getintvar(NULL, name);
@ -1680,7 +2004,7 @@ int ai_getdevpathintvar(si_t *sih, const char *name)
#endif
}
char *ai_getnvramflvar(si_t *sih, const char *name)
char *ai_getnvramflvar(struct si_pub *sih, const char *name)
{
return getvar(NULL, name);
}
@ -1690,7 +2014,8 @@ char *ai_getnvramflvar(si_t *sih, const char *name)
* len == 0 or var is NULL, var is still returned. On overflow, the
* first char will be set to '\0'.
*/
static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name)
static char *ai_devpathvar(struct si_pub *sih, char *var, int len,
const char *name)
{
uint path_len;
@ -1726,7 +2051,7 @@ static __used bool ai_ispcie(si_info_t *sii)
return true;
}
bool ai_pci_war16165(si_t *sih)
bool ai_pci_war16165(struct si_pub *sih)
{
si_info_t *sii;
@ -1735,7 +2060,7 @@ bool ai_pci_war16165(si_t *sih)
return PCI(sii) && (sih->buscorerev <= 10);
}
void ai_pci_up(si_t *sih)
void ai_pci_up(struct si_pub *sih)
{
si_info_t *sii;
@ -1754,7 +2079,7 @@ void ai_pci_up(si_t *sih)
}
/* Unconfigure and/or apply various WARs when system is going to sleep mode */
void ai_pci_sleep(si_t *sih)
void ai_pci_sleep(struct si_pub *sih)
{
si_info_t *sii;
@ -1764,7 +2089,7 @@ void ai_pci_sleep(si_t *sih)
}
/* Unconfigure and/or apply various WARs when going down */
void ai_pci_down(si_t *sih)
void ai_pci_down(struct si_pub *sih)
{
si_info_t *sii;
@ -1785,10 +2110,10 @@ void ai_pci_down(si_t *sih)
* Configure the pci core for pci client (NIC) action
* coremask is the bitvec of cores by index to be enabled.
*/
void ai_pci_setup(si_t *sih, uint coremask)
void ai_pci_setup(struct si_pub *sih, uint coremask)
{
si_info_t *sii;
struct sbpciregs *pciregs = NULL;
void *regs = NULL;
u32 siflag = 0, w;
uint idx = 0;
@ -1805,7 +2130,7 @@ void ai_pci_setup(si_t *sih, uint coremask)
siflag = ai_flag(sih);
/* switch over to pci core */
pciregs = ai_setcoreidx(sih, sii->pub.buscoreidx);
regs = ai_setcoreidx(sih, sii->pub.buscoreidx);
}
/*
@ -1823,16 +2148,7 @@ void ai_pci_setup(si_t *sih, uint coremask)
}
if (PCI(sii)) {
OR_REG(&pciregs->sbtopci2,
(SBTOPCI_PREF | SBTOPCI_BURST));
if (sii->pub.buscorerev >= 11) {
OR_REG(&pciregs->sbtopci2,
SBTOPCI_RC_READMULTI);
w = R_REG(&pciregs->clkrun);
W_REG(&pciregs->clkrun,
(w | PCI_CLKRUN_DSBL));
w = R_REG(&pciregs->clkrun);
}
pcicore_pci_setup(sii->pch, regs);
/* switch back to previous core */
ai_setcoreidx(sih, idx);
@ -1843,13 +2159,10 @@ void ai_pci_setup(si_t *sih, uint coremask)
* Fixup SROMless PCI device's configuration.
* The current core may be changed upon return.
*/
int ai_pci_fixcfg(si_t *sih)
int ai_pci_fixcfg(struct si_pub *sih)
{
uint origidx, pciidx;
struct sbpciregs *pciregs = NULL;
sbpcieregs_t *pcieregs = NULL;
uint origidx;
void *regs = NULL;
u16 val16, *reg16 = NULL;
si_info_t *sii = SI_INFO(sih);
@ -1858,23 +2171,8 @@ int ai_pci_fixcfg(si_t *sih)
origidx = ai_coreidx(&sii->pub);
/* check 'pi' is correct and fix it if not */
if (sii->pub.buscoretype == PCIE_CORE_ID) {
pcieregs = ai_setcore(&sii->pub, PCIE_CORE_ID, 0);
regs = pcieregs;
reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
} else if (sii->pub.buscoretype == PCI_CORE_ID) {
pciregs = ai_setcore(&sii->pub, PCI_CORE_ID, 0);
regs = pciregs;
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
}
pciidx = ai_coreidx(&sii->pub);
val16 = R_REG(reg16);
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
val16 =
(u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
~SRSH_PI_MASK);
W_REG(reg16, val16);
}
regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0);
pcicore_fixcfg(sii->pch, regs);
/* restore the original index */
ai_setcoreidx(&sii->pub, origidx);
@ -1884,7 +2182,7 @@ int ai_pci_fixcfg(si_t *sih)
}
/* mask&set gpiocontrol bits */
u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
{
uint regoff;
@ -1904,7 +2202,7 @@ u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
}
void ai_chipcontrl_epa4331(si_t *sih, bool on)
void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
{
si_info_t *sii;
chipcregs_t *cc;
@ -1938,7 +2236,7 @@ void ai_chipcontrl_epa4331(si_t *sih, bool on)
}
/* Enable BT-COEX & Ex-PA for 4313 */
void ai_epa_4313war(si_t *sih)
void ai_epa_4313war(struct si_pub *sih)
{
si_info_t *sii;
chipcregs_t *cc;
@ -1957,7 +2255,7 @@ void ai_epa_4313war(si_t *sih)
}
/* check if the device is removed */
bool ai_deviceremoved(si_t *sih)
bool ai_deviceremoved(struct si_pub *sih)
{
u32 w;
si_info_t *sii;
@ -1974,7 +2272,7 @@ bool ai_deviceremoved(si_t *sih)
return false;
}
bool ai_is_sprom_available(si_t *sih)
bool ai_is_sprom_available(struct si_pub *sih)
{
if (sih->ccrev >= 31) {
si_info_t *sii;
@ -2011,7 +2309,7 @@ bool ai_is_sprom_available(si_t *sih)
}
}
bool ai_is_otp_disabled(si_t *sih)
bool ai_is_otp_disabled(struct si_pub *sih)
{
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -2039,14 +2337,14 @@ bool ai_is_otp_disabled(si_t *sih)
}
}
bool ai_is_otp_powered(si_t *sih)
bool ai_is_otp_powered(struct si_pub *sih)
{
if (PMUCTL_ENAB(sih))
return si_pmu_is_otp_powered(sih);
return true;
}
void ai_otp_power(si_t *sih, bool on)
void ai_otp_power(struct si_pub *sih, bool on)
{
if (PMUCTL_ENAB(sih))
si_pmu_otp_power(sih, on);

216
drivers/staging/brcm80211/brcmsmac/aiutils.h
View File

@ -14,18 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _aiutils_h_
#define _aiutils_h_
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
/* Include the soci specific files */
#include <aidmp.h>
#ifndef _BRCM_AIUTILS_H_
#define _BRCM_AIUTILS_H_
/*
* SOC Interconnect Address Map.
@ -158,9 +148,7 @@
* maps all unused address ranges
*/
/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
* and chipcommon being the first core:
*/
/* chipcommon being the first core: */
#define SI_CC_IDX 0
/* SOC Interconnect types (aka chip types) */
@ -225,7 +213,70 @@
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
#define SI_INFO(sih) (si_info_t *)sih
#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
/* gpiotimerval */
#define GPIO_ONTIME_SHIFT 16
/* Fields in clkdiv */
#define CLKD_OTP 0x000f0000
#define CLKD_OTP_SHIFT 16
/* When Srom support present, fields in sromcontrol */
#define SRC_START 0x80000000
#define SRC_BUSY 0x80000000
#define SRC_OPCODE 0x60000000
#define SRC_OP_READ 0x00000000
#define SRC_OP_WRITE 0x20000000
#define SRC_OP_WRDIS 0x40000000
#define SRC_OP_WREN 0x60000000
#define SRC_OTPSEL 0x00000010
#define SRC_LOCK 0x00000008
#define SRC_SIZE_MASK 0x00000006
#define SRC_SIZE_1K 0x00000000
#define SRC_SIZE_4K 0x00000002
#define SRC_SIZE_16K 0x00000004
#define SRC_SIZE_SHIFT 1
#define SRC_PRESENT 0x00000001
/* 4330 chip-specific ChipStatus register bits */
#define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */
#define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */
#define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */
#define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */
#define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */
#define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */
#define CST4330_OTP_PRESENT 0x00000010
#define CST4330_LPO_AUTODET_EN 0x00000020
#define CST4330_ARMREMAP_0 0x00000040
#define CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */
#define CST4330_ILPDIV_EN 0x00000100
#define CST4330_LPO_SEL 0x00000200
#define CST4330_RES_INIT_MODE_SHIFT 10
#define CST4330_RES_INIT_MODE_MASK 0x00000c00
#define CST4330_CBUCK_MODE_SHIFT 12
#define CST4330_CBUCK_MODE_MASK 0x00003000
#define CST4330_CBUCK_POWER_OK 0x00004000
#define CST4330_BB_PLL_LOCKED 0x00008000
/* Package IDs */
#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
#define BCM4717_PKG_ID 9 /* 4717 package id */
#define BCM4718_PKG_ID 10 /* 4718 package id */
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
/* these are router chips */
#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
#define SI_INFO(sih) ((si_info_t *)sih)
#define GOODCOREADDR(x, b) \
(((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
@ -314,13 +365,6 @@ struct si_pub {
};
/*
* for HIGH_ONLY driver, the si_t must be writable to allow states sync from
* BMAC to HIGH driver for monolithic driver, it is readonly to prevent accident
* change
*/
typedef const struct si_pub si_t;
/*
* Many of the routines below take an 'sih' handle as their first arg.
* Allocate this by calling si_attach(). Free it by calling si_detach().
@ -453,94 +497,94 @@ typedef struct si_info {
} si_info_t;
/* AMBA Interconnect exported externs */
extern void ai_scan(si_t *sih, void *regs, uint devid);
extern void ai_scan(struct si_pub *sih, void *regs, uint devid);
extern uint ai_flag(si_t *sih);
extern void ai_setint(si_t *sih, int siflag);
extern uint ai_coreidx(si_t *sih);
extern uint ai_corevendor(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern bool ai_iscoreup(si_t *sih);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
extern uint ai_flag(struct si_pub *sih);
extern void ai_setint(struct si_pub *sih, int siflag);
extern uint ai_coreidx(struct si_pub *sih);
extern uint ai_corevendor(struct si_pub *sih);
extern uint ai_corerev(struct si_pub *sih);
extern bool ai_iscoreup(struct si_pub *sih);
extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(si_t *sih, u32 bits);
extern int ai_numaddrspaces(si_t *sih);
extern u32 ai_addrspace(si_t *sih, uint asidx);
extern u32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(struct si_pub *sih, u32 bits);
extern int ai_numaddrspaces(struct si_pub *sih);
extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
/* === exported functions === */
extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
extern struct si_pub *ai_attach(uint pcidev, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern void ai_detach(si_t *sih);
extern bool ai_pci_war16165(si_t *sih);
extern void ai_detach(struct si_pub *sih);
extern bool ai_pci_war16165(struct si_pub *sih);
extern uint ai_coreid(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
extern uint ai_coreid(struct si_pub *sih);
extern uint ai_corerev(struct si_pub *sih);
extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val);
extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
extern bool ai_iscoreup(si_t *sih);
extern uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern void *ai_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *ai_switch_core(si_t *sih, uint coreid, uint *origidx,
extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
extern bool ai_iscoreup(struct si_pub *sih);
extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
extern void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
extern void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
uint *intr_val);
extern void ai_restore_core(si_t *sih, uint coreid, uint intr_val);
extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(si_t *sih, u32 bits);
extern u32 ai_alp_clock(si_t *sih);
extern u32 ai_ilp_clock(si_t *sih);
extern void ai_pci_setup(si_t *sih, uint coremask);
extern void ai_setint(si_t *sih, int siflag);
extern bool ai_backplane64(si_t *sih);
extern void ai_register_intr_callback(si_t *sih, void *intrsoff_fn,
extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(struct si_pub *sih, u32 bits);
extern u32 ai_alp_clock(struct si_pub *sih);
extern u32 ai_ilp_clock(struct si_pub *sih);
extern void ai_pci_setup(struct si_pub *sih, uint coremask);
extern void ai_setint(struct si_pub *sih, int siflag);
extern bool ai_backplane64(struct si_pub *sih);
extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern void ai_deregister_intr_callback(si_t *sih);
extern void ai_clkctl_init(si_t *sih);
extern u16 ai_clkctl_fast_pwrup_delay(si_t *sih);
extern bool ai_clkctl_cc(si_t *sih, uint mode);
extern int ai_clkctl_xtal(si_t *sih, uint what, bool on);
extern bool ai_deviceremoved(si_t *sih);
extern u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val,
extern void ai_deregister_intr_callback(struct si_pub *sih);
extern void ai_clkctl_init(struct si_pub *sih);
extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
extern bool ai_deviceremoved(struct si_pub *sih);
extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
u8 priority);
/* OTP status */
extern bool ai_is_otp_disabled(si_t *sih);
extern bool ai_is_otp_powered(si_t *sih);
extern void ai_otp_power(si_t *sih, bool on);
extern bool ai_is_otp_disabled(struct si_pub *sih);
extern bool ai_is_otp_powered(struct si_pub *sih);
extern void ai_otp_power(struct si_pub *sih, bool on);
/* SPROM availability */
extern bool ai_is_sprom_available(si_t *sih);
extern bool ai_is_sprom_available(struct si_pub *sih);
/*
* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
* The returned path is NULL terminated and has trailing '/'.
* Return 0 on success, nonzero otherwise.
*/
extern int ai_devpath(si_t *sih, char *path, int size);
extern int ai_devpath(struct si_pub *sih, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *ai_getdevpathvar(si_t *sih, const char *name);
extern int ai_getdevpathintvar(si_t *sih, const char *name);
extern char *ai_getdevpathvar(struct si_pub *sih, const char *name);
extern int ai_getdevpathintvar(struct si_pub *sih, const char *name);
extern void ai_pci_sleep(si_t *sih);
extern void ai_pci_down(si_t *sih);
extern void ai_pci_up(si_t *sih);
extern int ai_pci_fixcfg(si_t *sih);
extern void ai_pci_sleep(struct si_pub *sih);
extern void ai_pci_down(struct si_pub *sih);
extern void ai_pci_up(struct si_pub *sih);
extern int ai_pci_fixcfg(struct si_pub *sih);
extern void ai_chipcontrl_epa4331(si_t *sih, bool on);
extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
/* Enable Ex-PA for 4313 */
extern void ai_epa_4313war(si_t *sih);
extern void ai_epa_4313war(struct si_pub *sih);
char *ai_getnvramflvar(si_t *sih, const char *name);
char *ai_getnvramflvar(struct si_pub *sih, const char *name);
#endif /* _aiutils_h_ */
#endif /* _BRCM_AIUTILS_H_ */

38
drivers/staging/brcm80211/brcmsmac/wlc_alloc.c → drivers/staging/brcm80211/brcmsmac/alloc.c
View File

@ -16,25 +16,20 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
#include "dma.h"
#include "d11.h"
#include "wlc_types.h"
#include "wlc_cfg.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_key.h"
#include "wlc_alloc.h"
#include "wl_dbg.h"
#include "wlc_rate.h"
#include "wlc_bsscfg.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "types.h"
#include "scb.h"
#include "pub.h"
#include "alloc.h"
#include "rate.h"
#include "phy/phy_hal.h"
#include "channel.h"
#include "main.h"
static struct wlc_bsscfg *wlc_bsscfg_malloc(uint unit);
static void wlc_bsscfg_mfree(struct wlc_bsscfg *cfg);
@ -152,8 +147,6 @@ struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid)
goto fail;
}
wlc->hwrxoff = WL_HWRXOFF;
/* allocate struct wlc_pub state structure */
wlc->pub = wlc_pub_malloc(unit, err, devid);
if (wlc->pub == NULL) {
@ -206,14 +199,6 @@ struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid)
}
wlc_bsscfg_ID_assign(wlc, wlc->cfg);
wlc->pkt_callback = kzalloc(sizeof(struct pkt_cb) *
(wlc->pub->tunables->maxpktcb + 1),
GFP_ATOMIC);
if (wlc->pkt_callback == NULL) {
*err = 1013;
goto fail;
}
wlc->wsec_def_keys[0] =
kzalloc(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS, GFP_ATOMIC);
if (wlc->wsec_def_keys[0] == NULL) {
@ -284,7 +269,6 @@ void wlc_detach_mfree(struct wlc_info *wlc)
wlc_pub_mfree(wlc->pub);
kfree(wlc->modulecb);
kfree(wlc->default_bss);
kfree(wlc->pkt_callback);
kfree(wlc->wsec_def_keys[0]);
kfree(wlc->protection);
kfree(wlc->stf);

0
drivers/staging/brcm80211/brcmsmac/wlc_alloc.h → drivers/staging/brcm80211/brcmsmac/alloc.h
View File

48
drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c → drivers/staging/brcm80211/brcmsmac/ampdu.c
View File

@ -16,27 +16,21 @@
#include <linux/kernel.h>
#include <net/mac80211.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
#include <hnddma.h>
#include "dma.h"
#include <d11.h>
#include "wlc_types.h"
#include "wlc_cfg.h"
#include "wlc_rate.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_key.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_antsel.h"
#include "wl_export.h"
#include "wl_dbg.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "wlc_ampdu.h"
#include "types.h"
#include "rate.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "antsel.h"
#include "channel.h"
#include "main.h"
#include "ampdu.h"
#define AMPDU_MAX_MPDU 32 /* max number of mpdus in an ampdu */
#define AMPDU_NUM_MPDU_LEGACY 16 /* max number of mpdus in an ampdu to a legacy */
@ -499,10 +493,6 @@ wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
wlc_ampdu_agg(ampdu, scb, p, tid);
if (wlc->block_datafifo) {
wiphy_err(wiphy, "%s: Fifo blocked\n", __func__);
return -EBUSY;
}
rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
ampdu_len = 0;
dma_len = 0;
@ -598,7 +588,7 @@ wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
len = roundup(len, 4);
ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
dma_len += (u16) bcm_pkttotlen(p);
dma_len += (u16) brcmu_pkttotlen(p);
BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
" seg_cnt %d null delim %d\n",
@ -693,8 +683,8 @@ wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
((u8) (p->priority) == tid)) {
plen =
bcm_pkttotlen(p) + AMPDU_MAX_MPDU_OVERHEAD;
plen = brcmu_pkttotlen(p) +
AMPDU_MAX_MPDU_OVERHEAD;
plen = max(scb_ampdu->min_len, plen);
if ((plen + ampdu_len) > maxlen) {
@ -711,7 +701,7 @@ wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
p = NULL;
continue;
}
p = bcm_pktq_pdeq(&qi->q, prec);
p = brcmu_pktq_pdeq(&qi->q, prec);
} else {
p = NULL;
}
@ -871,7 +861,7 @@ wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
tx_info = IEEE80211_SKB_CB(p);
txh = (d11txh_t *) p->data;
mcl = le16_to_cpu(txh->MacTxControlLow);
bcm_pkt_buf_free_skb(p);
brcmu_pkt_buf_free_skb(p);
/* break out if last packet of ampdu */
if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
TXC_AMPDU_LAST)
@ -1000,7 +990,7 @@ wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
txs->phyerr);
if (WL_ERROR_ON()) {
bcm_prpkt("txpkt (AMPDU)", p);
brcmu_prpkt("txpkt (AMPDU)", p);
wlc_print_txdesc((d11txh_t *) p->data);
}
wlc_print_txstatus(txs);
@ -1246,7 +1236,7 @@ void wlc_ampdu_flush(struct wlc_info *wlc,
ampdu_pars.sta = sta;
ampdu_pars.tid = tid;
for (prec = 0; prec < pq->num_prec; prec++) {
bcm_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
brcmu_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
(void *)&ampdu_pars);
}
wlc_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);

6
drivers/staging/brcm80211/brcmsmac/wlc_ampdu.h → drivers/staging/brcm80211/brcmsmac/ampdu.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_ampdu_h_
#define _wlc_ampdu_h_
#ifndef _BRCM_AMPDU_H_
#define _BRCM_AMPDU_H_
extern struct ampdu_info *wlc_ampdu_attach(struct wlc_info *wlc);
extern void wlc_ampdu_detach(struct ampdu_info *ampdu);
@ -26,4 +26,4 @@ extern void wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
extern void wlc_ampdu_macaddr_upd(struct wlc_info *wlc);
extern void wlc_ampdu_shm_upd(struct ampdu_info *ampdu);
#endif /* _wlc_ampdu_h_ */
#endif /* _BRCM_AMPDU_H_ */

39
drivers/staging/brcm80211/brcmsmac/wlc_antsel.c → drivers/staging/brcm80211/brcmsmac/antsel.c
View File

@ -14,33 +14,32 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <wlc_cfg.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
#include <wlioctl.h>
#include <brcm_hw_ids.h>
#include "dma.h"
#include "d11.h"
#include "wlc_rate.h"
#include "wlc_key.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wl_dbg.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_bmac.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "wl_export.h"
#include "wlc_phy_shim.h"
#include "wlc_antsel.h"
#include "rate.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "bmac.h"
#include "channel.h"
#include "main.h"
#include "antsel.h"
#define ANT_SELCFG_AUTO 0x80 /* bit indicates antenna sel AUTO */
#define ANT_SELCFG_MASK 0x33 /* antenna configuration mask */
#define ANT_SELCFG_TX_UNICAST 0 /* unicast tx antenna configuration */
#define ANT_SELCFG_RX_UNICAST 1 /* unicast rx antenna configuration */
#define ANT_SELCFG_TX_DEF 2 /* default tx antenna configuration */
#define ANT_SELCFG_RX_DEF 3 /* default rx antenna configuration */
/* useful macros */
#define WLC_ANTSEL_11N_0(ant) ((((ant) & ANT_SELCFG_MASK) >> 4) & 0xf)

6
drivers/staging/brcm80211/brcmsmac/wlc_antsel.h → drivers/staging/brcm80211/brcmsmac/antsel.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_antsel_h_
#define _wlc_antsel_h_
#ifndef _BRCM_ANTSEL_H_
#define _BRCM_ANTSEL_H_
extern struct antsel_info *wlc_antsel_attach(struct wlc_info *wlc);
extern void wlc_antsel_detach(struct antsel_info *asi);
@ -26,4 +26,4 @@ extern void wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef,
u8 *fbantcfg);
extern u8 wlc_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
#endif /* _wlc_antsel_h_ */
#endif /* _BRCM_ANTSEL_H_ */

714
drivers/staging/brcm80211/brcmsmac/bcmsrom.c
View File

@ -1,714 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/etherdevice.h>
#include <bcmdefs.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <stdarg.h>
#include <bcmutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <bcmdevs.h>
#include <pcicfg.h>
#include <aiutils.h>
#include <bcmsrom.h>
#include <bcmsrom_tbl.h>
#include <bcmnvram.h>
#include <bcmotp.h>
#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
(((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
#if defined(BCMDBG)
#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
#endif
typedef struct varbuf {
char *base; /* pointer to buffer base */
char *buf; /* pointer to current position */
unsigned int size; /* current (residual) size in bytes */
} varbuf_t;
extern char *_vars;
extern uint _varsz;
static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *count);
static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count);
static int initvars_flash_si(si_t *sih, char **vars, uint *count);
static int sprom_read_pci(si_t *sih, u16 *sprom,
uint wordoff, u16 *buf, uint nwords, bool check_crc);
#if defined(BCMNVRAMR)
static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz);
#endif
static u16 srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
uint wordoff, u16 data);
static int initvars_table(char *start, char *end,
char **vars, uint *count);
static int initvars_flash(si_t *sih, char **vp,
uint len);
/* Initialization of varbuf structure */
static void varbuf_init(varbuf_t *b, char *buf, uint size)
{
b->size = size;
b->base = b->buf = buf;
}
/* append a null terminated var=value string */
static int varbuf_append(varbuf_t *b, const char *fmt, ...)
{
va_list ap;
int r;
size_t len;
char *s;
if (b->size < 2)
return 0;
va_start(ap, fmt);
r = vsnprintf(b->buf, b->size, fmt, ap);
va_end(ap);
/* C99 snprintf behavior returns r >= size on overflow,
* others return -1 on overflow.
* All return -1 on format error.
* We need to leave room for 2 null terminations, one for the current var
* string, and one for final null of the var table. So check that the
* strlen written, r, leaves room for 2 chars.
*/
if ((r == -1) || (r > (int)(b->size - 2))) {
b->size = 0;
return 0;
}
/* Remove any earlier occurrence of the same variable */
s = strchr(b->buf, '=');
if (s != NULL) {
len = (size_t) (s - b->buf);
for (s = b->base; s < b->buf;) {
if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
len = strlen(s) + 1;
memmove(s, (s + len),
((b->buf + r + 1) - (s + len)));
b->buf -= len;
b->size += (unsigned int)len;
break;
}
while (*s++)
;
}
}
/* skip over this string's null termination */
r++;
b->size -= r;
b->buf += r;
return r;
}
/*
* Initialize local vars from the right source for this platform.
* Return 0 on success, nonzero on error.
*/
int srom_var_init(si_t *sih, uint bustype, void *curmap,
char **vars, uint *count)
{
uint len;
len = 0;
if (vars == NULL || count == NULL)
return 0;
*vars = NULL;
*count = 0;
switch (bustype) {
case SI_BUS:
case JTAG_BUS:
return initvars_srom_si(sih, curmap, vars, count);
case PCI_BUS:
if (curmap == NULL)
return -1;
return initvars_srom_pci(sih, curmap, vars, count);
default:
break;
}
return -1;
}
/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
* not in the bus cores.
*/
static u16
srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
uint wordoff, u16 data)
{
chipcregs_t *cc = (chipcregs_t *) ccregs;
uint wait_cnt = 1000;
if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
W_REG(&cc->sromaddress, wordoff * 2);
if (cmd == SRC_OP_WRITE)
W_REG(&cc->sromdata, data);
}
W_REG(&cc->sromcontrol, SRC_START | cmd);
while (wait_cnt--) {
if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
break;
}
if (!wait_cnt) {
return 0xffff;
}
if (cmd == SRC_OP_READ)
return (u16) R_REG(&cc->sromdata);
else
return 0xffff;
}
static inline void ltoh16_buf(u16 *buf, unsigned int size)
{
for (size /= 2; size; size--)
*(buf + size) = le16_to_cpu(*(buf + size));
}
static inline void htol16_buf(u16 *buf, unsigned int size)
{
for (size /= 2; size; size--)
*(buf + size) = cpu_to_le16(*(buf + size));
}
/*
* Read in and validate sprom.
* Return 0 on success, nonzero on error.
*/
static int
sprom_read_pci(si_t *sih, u16 *sprom, uint wordoff,
u16 *buf, uint nwords, bool check_crc)
{
int err = 0;
uint i;
void *ccregs = NULL;
/* read the sprom */
for (i = 0; i < nwords; i++) {
if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
/* use indirect since direct is too slow on QT */
if ((sih->cccaps & CC_CAP_SROM) == 0)
return 1;
ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
buf[i] =
srom_cc_cmd(sih, ccregs, SRC_OP_READ,
wordoff + i, 0);
} else {
if (ISSIM_ENAB(sih))
buf[i] = R_REG(&sprom[wordoff + i]);
buf[i] = R_REG(&sprom[wordoff + i]);
}
}
/* bypass crc checking for simulation to allow srom hack */
if (ISSIM_ENAB(sih))
return err;
if (check_crc) {
if (buf[0] == 0xffff) {
/* The hardware thinks that an srom that starts with 0xffff
* is blank, regardless of the rest of the content, so declare
* it bad.
*/
return 1;
}
/* fixup the endianness so crc8 will pass */
htol16_buf(buf, nwords * 2);
if (bcm_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
CRC8_GOOD_VALUE) {
/* DBG only pci always read srom4 first, then srom8/9 */
err = 1;
}
/* now correct the endianness of the byte array */
ltoh16_buf(buf, nwords * 2);
}
return err;
}
#if defined(BCMNVRAMR)
static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz)
{
u8 *otp;
uint sz = OTP_SZ_MAX / 2; /* size in words */
int err = 0;
otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
if (otp == NULL) {
return -EBADE;
}
err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
memcpy(buf, otp, bufsz);
kfree(otp);
/* Check CRC */
if (buf[0] == 0xffff) {
/* The hardware thinks that an srom that starts with 0xffff
* is blank, regardless of the rest of the content, so declare
* it bad.
*/
return 1;
}
/* fixup the endianness so crc8 will pass */
htol16_buf(buf, bufsz);
if (bcm_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
CRC8_GOOD_VALUE) {
err = 1;
}
/* now correct the endianness of the byte array */
ltoh16_buf(buf, bufsz);
return err;
}
#endif /* defined(BCMNVRAMR) */
/*
* Create variable table from memory.
* Return 0 on success, nonzero on error.
*/
static int initvars_table(char *start, char *end,
char **vars, uint *count)
{
int c = (int)(end - start);
/* do it only when there is more than just the null string */
if (c > 1) {
char *vp = kmalloc(c, GFP_ATOMIC);
if (!vp)
return -ENOMEM;
memcpy(vp, start, c);
*vars = vp;
*count = c;
} else {
*vars = NULL;
*count = 0;
}
return 0;
}
/*
* Find variables with <devpath> from flash. 'base' points to the beginning
* of the table upon enter and to the end of the table upon exit when success.
* Return 0 on success, nonzero on error.
*/
static int initvars_flash(si_t *sih, char **base, uint len)
{
char *vp = *base;
char *flash;
int err;
char *s;
uint l, dl, copy_len;
char devpath[SI_DEVPATH_BUFSZ];
/* allocate memory and read in flash */
flash = kmalloc(NVRAM_SPACE, GFP_ATOMIC);
if (!flash)
return -ENOMEM;
err = nvram_getall(flash, NVRAM_SPACE);
if (err)
goto exit;
ai_devpath(sih, devpath, sizeof(devpath));
/* grab vars with the <devpath> prefix in name */
dl = strlen(devpath);
for (s = flash; s && *s; s += l + 1) {
l = strlen(s);
/* skip non-matching variable */
if (strncmp(s, devpath, dl))
continue;
/* is there enough room to copy? */
copy_len = l - dl + 1;
if (len < copy_len) {
err = -EOVERFLOW;
goto exit;
}
/* no prefix, just the name=value */
strncpy(vp, &s[dl], copy_len);
vp += copy_len;
len -= copy_len;
}
/* add null string as terminator */
if (len < 1) {
err = -EOVERFLOW;
goto exit;
}
*vp++ = '\0';
*base = vp;
exit: kfree(flash);
return err;
}
/*
* Initialize nonvolatile variable table from flash.
* Return 0 on success, nonzero on error.
*/
static int initvars_flash_si(si_t *sih, char **vars, uint *count)
{
char *vp, *base;
int err;
base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
if (!vp)
return -ENOMEM;
err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
if (err == 0)
err = initvars_table(base, vp, vars, count);
kfree(base);
return err;
}
/* Parse SROM and create name=value pairs. 'srom' points to
* the SROM word array. 'off' specifies the offset of the
* first word 'srom' points to, which should be either 0 or
* SROM3_SWRG_OFF (full SROM or software region).
*/
static uint mask_shift(u16 mask)
{
uint i;
for (i = 0; i < (sizeof(mask) << 3); i++) {
if (mask & (1 << i))
return i;
}
return 0;
}
static uint mask_width(u16 mask)
{
int i;
for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
if (mask & (1 << i))
return (uint) (i - mask_shift(mask) + 1);
}
return 0;
}
static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
{
u16 w;
u32 val;
const sromvar_t *srv;
uint width;
uint flags;
u32 sr = (1 << sromrev);
varbuf_append(b, "sromrev=%d", sromrev);
for (srv = pci_sromvars; srv->name != NULL; srv++) {
const char *name;
if ((srv->revmask & sr) == 0)
continue;
if (srv->off < off)
continue;
flags = srv->flags;
name = srv->name;
/* This entry is for mfgc only. Don't generate param for it, */
if (flags & SRFL_NOVAR)
continue;
if (flags & SRFL_ETHADDR) {
u8 ea[ETH_ALEN];
ea[0] = (srom[srv->off - off] >> 8) & 0xff;
ea[1] = srom[srv->off - off] & 0xff;
ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
ea[3] = srom[srv->off + 1 - off] & 0xff;
ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
ea[5] = srom[srv->off + 2 - off] & 0xff;
varbuf_append(b, "%s=%pM", name, ea);
} else {
w = srom[srv->off - off];
val = (w & srv->mask) >> mask_shift(srv->mask);
width = mask_width(srv->mask);
while (srv->flags & SRFL_MORE) {
srv++;
if (srv->off == 0 || srv->off < off)
continue;
w = srom[srv->off - off];
val +=
((w & srv->mask) >> mask_shift(srv->
mask)) <<
width;
width += mask_width(srv->mask);
}
if ((flags & SRFL_NOFFS)
&& ((int)val == (1 << width) - 1))
continue;
if (flags & SRFL_CCODE) {
if (val == 0)
varbuf_append(b, "ccode=");
else
varbuf_append(b, "ccode=%c%c",
(val >> 8), (val & 0xff));
}
/* LED Powersave duty cycle has to be scaled:
*(oncount >> 24) (offcount >> 8)
*/
else if (flags & SRFL_LEDDC) {
u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
(((val & 0xff)) << 8); /* offcount */
varbuf_append(b, "leddc=%d", w32);
} else if (flags & SRFL_PRHEX)
varbuf_append(b, "%s=0x%x", name, val);
else if ((flags & SRFL_PRSIGN)
&& (val & (1 << (width - 1))))
varbuf_append(b, "%s=%d", name,
(int)(val | (~0 << width)));
else
varbuf_append(b, "%s=%u", name, val);
}
}
if (sromrev >= 4) {
/* Do per-path variables */
uint p, pb, psz;
if (sromrev >= 8) {
pb = SROM8_PATH0;
psz = SROM8_PATH1 - SROM8_PATH0;
} else {
pb = SROM4_PATH0;
psz = SROM4_PATH1 - SROM4_PATH0;
}
for (p = 0; p < MAX_PATH_SROM; p++) {
for (srv = perpath_pci_sromvars; srv->name != NULL;
srv++) {
if ((srv->revmask & sr) == 0)
continue;
if (pb + srv->off < off)
continue;
/* This entry is for mfgc only. Don't generate param for it, */
if (srv->flags & SRFL_NOVAR)
continue;
w = srom[pb + srv->off - off];
val = (w & srv->mask) >> mask_shift(srv->mask);
width = mask_width(srv->mask);
/* Cheating: no per-path var is more than 1 word */
if ((srv->flags & SRFL_NOFFS)
&& ((int)val == (1 << width) - 1))
continue;
if (srv->flags & SRFL_PRHEX)
varbuf_append(b, "%s%d=0x%x", srv->name,
p, val);
else
varbuf_append(b, "%s%d=%d", srv->name,
p, val);
}
pb += psz;
}
}
}
/*
* Initialize nonvolatile variable table from sprom.
* Return 0 on success, nonzero on error.
*/
static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count)
{
u16 *srom, *sromwindow;
u8 sromrev = 0;
u32 sr;
varbuf_t b;
char *vp, *base = NULL;
bool flash = false;
int err = 0;
/*
* Apply CRC over SROM content regardless SROM is present or not,
* and use variable <devpath>sromrev's existence in flash to decide
* if we should return an error when CRC fails or read SROM variables
* from flash.
*/
srom = kmalloc(SROM_MAX, GFP_ATOMIC);
if (!srom)
return -2;
sromwindow = (u16 *) SROM_OFFSET(sih);
if (ai_is_sprom_available(sih)) {
err =
sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
true);
if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
(((sih->buscoretype == PCIE_CORE_ID)
&& (sih->buscorerev >= 6))
|| ((sih->buscoretype == PCI_CORE_ID)
&& (sih->buscorerev >= 0xe)))) {
/* sromrev >= 4, read more */
err =
sprom_read_pci(sih, sromwindow, 0, srom,
SROM4_WORDS, true);
sromrev = srom[SROM4_CRCREV] & 0xff;
} else if (err == 0) {
/* srom is good and is rev < 4 */
/* top word of sprom contains version and crc8 */
sromrev = srom[SROM_CRCREV] & 0xff;
/* bcm4401 sroms misprogrammed */
if (sromrev == 0x10)
sromrev = 1;
}
}
#if defined(BCMNVRAMR)
/* Use OTP if SPROM not available */
else {
err = otp_read_pci(sih, srom, SROM_MAX);
if (err == 0)
/* OTP only contain SROM rev8/rev9 for now */
sromrev = srom[SROM4_CRCREV] & 0xff;
else
err = 1;
}
#else
else
err = 1;
#endif
/*
* We want internal/wltest driver to come up with default
* sromvars so we can program a blank SPROM/OTP.
*/
if (err) {
char *value;
u32 val;
val = 0;
value = ai_getdevpathvar(sih, "sromrev");
if (value) {
sromrev = (u8) simple_strtoul(value, NULL, 0);
flash = true;
goto varscont;
}
value = ai_getnvramflvar(sih, "sromrev");
if (value) {
err = 0;
goto errout;
}
{
err = -1;
goto errout;
}
}
varscont:
/* Bitmask for the sromrev */
sr = 1 << sromrev;
/* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
if ((sr & 0x33e) == 0) {
err = -2;
goto errout;
}
base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
if (!vp) {
err = -2;
goto errout;
}
/* read variables from flash */
if (flash) {
err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
if (err)
goto errout;
goto varsdone;
}
varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
/* parse SROM into name=value pairs. */
_initvars_srom_pci(sromrev, srom, 0, &b);
/* final nullbyte terminator */
vp = b.buf;
*vp++ = '\0';
varsdone:
err = initvars_table(base, vp, vars, count);
errout:
if (base)
kfree(base);
kfree(srom);
return err;
}
static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *varsz)
{
/* Search flash nvram section for srom variables */
return initvars_flash_si(sih, vars, varsz);
}

108
drivers/staging/brcm80211/brcmsmac/wlc_bmac.c → drivers/staging/brcm80211/brcmsmac/bmac.c
View File

@ -21,41 +21,31 @@
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <proto/802.11.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmwifi.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <brcmu_wifi.h>
#include <aiutils.h>
#include <bcmsrom.h>
#include <bcmotp.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <wlioctl.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <sbhnddma.h>
#include <hnddma.h>
#include "srom.h"
#include "otp.h"
#include <brcmu_utils.h>
#include <chipcommon.h>
#include <nicpci.h>
#include "dma.h"
#include "wlc_types.h"
#include "wlc_pmu.h"
#include "types.h"
#include "pmu.h"
#include "d11.h"
#include "wlc_cfg.h"
#include "wlc_rate.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_key.h"
#include "wlc_phy_shim.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "wl_export.h"
#include "wl_ucode.h"
#include "wlc_antsel.h"
#include "pcie_core.h"
#include "wlc_alloc.h"
#include "wl_dbg.h"
#include "wlc_bmac.h"
#include "rate.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "channel.h"
#include "main.h"
#include "ucode_loader.h"
#include "antsel.h"
#include "alloc.h"
#include "bmac.h"
#include "mac80211_if.h"
#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
@ -78,6 +68,9 @@
(void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
(void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
#define APHY_SLOT_TIME 9
#define BPHY_SLOT_TIME 20
/*
* The following table lists the buffer memory allocated to xmt fifos in HW.
* the size is in units of 256bytes(one block), total size is HW dependent
@ -241,7 +234,7 @@ static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
/* disable interrupts */
macintmask = wl_intrsoff(wlc->wl);
macintmask = brcms_intrsoff(wlc->wl);
/* radio off */
wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
@ -318,7 +311,7 @@ bool wlc_dpc(struct wlc_info *wlc, bool bounded)
if (DEVICEREMOVED(wlc)) {
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
__func__);
wl_down(wlc->wl);
brcms_down(wlc->wl);
return false;
}
@ -333,7 +326,7 @@ bool wlc_dpc(struct wlc_info *wlc, bool bounded)
/* BCN template is available */
/* ZZZ: Use AP_ACTIVE ? */
if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
&& (macintstatus & MI_BCNTPL)) {
wlc_update_beacon(wlc);
}
@ -389,7 +382,7 @@ bool wlc_dpc(struct wlc_info *wlc, bool bounded)
__func__, wlc_hw->sih->chip,
wlc_hw->sih->chiprev);
/* big hammer */
wl_init(wlc->wl);
brcms_init(wlc->wl);
}
/* gptimer timeout */
@ -400,7 +393,7 @@ bool wlc_dpc(struct wlc_info *wlc, bool bounded)
if (macintstatus & MI_RFDISABLE) {
BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
" RF Disable Input\n", wlc_hw->unit);
wl_rfkill_set_hw_state(wlc->wl);
brcms_rfkill_set_hw_state(wlc->wl);
}
/* send any enq'd tx packets. Just makes sure to jump start tx */
@ -411,7 +404,7 @@ bool wlc_dpc(struct wlc_info *wlc, bool bounded)
return wlc->macintstatus != 0;
fatal:
wl_init(wlc->wl);
brcms_init(wlc->wl);
return wlc->macintstatus != 0;
}
@ -529,7 +522,7 @@ static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
NULL), DMAREG(wlc_hw, DMA_RX, 0),
(wme ? tune->ntxd : 0), tune->nrxd,
tune->rxbufsz, -1, tune->nrxbufpost,
WL_HWRXOFF, &wl_msg_level);
WL_HWRXOFF, &brcm_msg_level);
dma_attach_err |= (NULL == wlc_hw->di[0]);
/*
@ -541,7 +534,7 @@ static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 1), NULL,
tune->ntxd, 0, 0, -1, 0, 0,
&wl_msg_level);
&brcm_msg_level);
dma_attach_err |= (NULL == wlc_hw->di[1]);
/*
@ -552,7 +545,7 @@ static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 2), NULL,
tune->ntxd, 0, 0, -1, 0, 0,
&wl_msg_level);
&brcm_msg_level);
dma_attach_err |= (NULL == wlc_hw->di[2]);
/*
* FIFO 3
@ -562,7 +555,7 @@ static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 3),
NULL, tune->ntxd, 0, 0, -1,
0, 0, &wl_msg_level);
0, 0, &brcm_msg_level);
dma_attach_err |= (NULL == wlc_hw->di[3]);
/* Cleaner to leave this as if with AP defined */
@ -743,7 +736,8 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
wlc->war16165 = true;
/* check device id(srom, nvram etc.) to set bands */
if (wlc_hw->deviceid == BCM43224_D11N_ID) {
if (wlc_hw->deviceid == BCM43224_D11N_ID ||
wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
/* Dualband boards */
wlc_hw->_nbands = 2;
} else
@ -925,7 +919,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
err = 21;
goto fail;
}
bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
is_zero_ether_addr(wlc_hw->etheraddr)) {
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
@ -1052,7 +1046,7 @@ wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
wlc_clkctl_clk(wlc_hw, CLK_FAST);
/* disable interrupts */
macintmask = wl_intrsoff(wlc->wl);
macintmask = brcms_intrsoff(wlc->wl);
/* set up the specified band and chanspec */
wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
@ -1072,7 +1066,7 @@ wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
wlc_bmac_bsinit(wlc, chanspec);
/* restore macintmask */
wl_intrsrestore(wlc->wl, macintmask);
brcms_intrsrestore(wlc->wl, macintmask);
/* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
* and wlc_enable_mac() will clear this override bit.
@ -1142,7 +1136,7 @@ int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
/* FULLY enable dynamic power control and d11 core interrupt */
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
wl_intrson(wlc_hw->wlc->wl);
brcms_intrson(wlc_hw->wlc->wl);
return 0;
}
@ -1163,7 +1157,7 @@ int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
wlc_hw->wlc->macintmask = 0;
else {
/* now disable interrupts */
wl_intrsoff(wlc_hw->wlc->wl);
brcms_intrsoff(wlc_hw->wlc->wl);
/* ensure we're running on the pll clock again */
wlc_clkctl_clk(wlc_hw, CLK_FAST);
@ -1203,7 +1197,7 @@ int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
if (R_REG(&wlc_hw->regs->maccontrol) &
MCTL_EN_MAC)
wlc_suspend_mac_and_wait(wlc_hw->wlc);
callbacks += wl_reset(wlc_hw->wlc->wl);
callbacks += brcms_reset(wlc_hw->wlc->wl);
wlc_coredisable(wlc_hw);
}
@ -1887,7 +1881,7 @@ WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
wlc->macintstatus = MI_DMAINT;
/* restore macintmask */
wl_intrsrestore(wlc->wl, macintmask);
brcms_intrsrestore(wlc->wl, macintmask);
/* ucode should still be suspended.. */
WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
@ -2065,7 +2059,7 @@ void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
{
struct hnddma_pub *di = wlc_hw->di[fifo];
struct dma_pub *di = wlc_hw->di[fifo];
return dma_rxreset(di);
}
@ -2685,7 +2679,7 @@ static u32 wlc_wlintrsoff(struct wlc_info *wlc)
if (!wlc->hw->up)
return 0;
return wl_intrsoff(wlc->wl);
return brcms_intrsoff(wlc->wl);
}
static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
@ -2693,7 +2687,7 @@ static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
if (!wlc->hw->up)
return;
wl_intrsrestore(wlc->wl, macintmask);
brcms_intrsrestore(wlc->wl, macintmask);
}
u32 wlc_intrsoff(struct wlc_info *wlc)
@ -3067,7 +3061,7 @@ void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
if (mc == 0xffffffff) {
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
__func__);
wl_down(wlc->wl);
brcms_down(wlc->wl);
return;
}
WARN_ON(mc & MCTL_PSM_JMP_0);
@ -3078,7 +3072,7 @@ void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
if (mi == 0xffffffff) {
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
__func__);
wl_down(wlc->wl);
brcms_down(wlc->wl);
return;
}
WARN_ON(mi & MI_MACSSPNDD);
@ -3103,7 +3097,7 @@ void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
if (mc == 0xffffffff) {
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
__func__);
wl_down(wlc->wl);
brcms_down(wlc->wl);
return;
}
WARN_ON(mc & MCTL_PSM_JMP_0);
@ -3418,7 +3412,7 @@ static void wlc_flushqueues(struct wlc_info *wlc)
/* free any posted tx packets */
for (i = 0; i < NFIFO; i++)
if (wlc_hw->di[i]) {
dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
TXPKTPENDCLR(wlc, i);
BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
}

17
drivers/staging/brcm80211/brcmsmac/wlc_bmac.h → drivers/staging/brcm80211/brcmsmac/bmac.h
View File

@ -13,19 +13,8 @@
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_bmac_h_
#define _wlc_bmac_h_
/* XXXXX this interface is under wlc.c by design
* http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/WlBmacDesign
*
* high driver files(e.g. wlc_ampdu.c etc)
* wlc.h/wlc.c
* wlc_bmac.h/wlc_bmac.c
*
* So don't include this in files other than wlc.c, wlc_bmac* wl_rte.c(dongle port) and wl_phy.c
* create wrappers in wlc.c if needed
*/
#ifndef _BRCM_BOTTOM_MAC_H_
#define _BRCM_BOTTOM_MAC_H_
/* dup state between BMAC(struct wlc_hw_info) and HIGH(struct wlc_info)
driver */
@ -175,4 +164,4 @@ extern void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw);
extern u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate);
extern void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail);
#endif /* _wlc_bmac_h_ */
#endif /* _BRCM_BOTTOM_MAC_H_ */

31
drivers/staging/brcm80211/brcmsmac/wlc_channel.c → drivers/staging/brcm80211/brcmsmac/channel.c
View File

@ -19,26 +19,21 @@
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <sbhnddma.h>
#include <wlioctl.h>
#include "dma.h"
#include "wlc_types.h"
#include "types.h"
#include "d11.h"
#include "wlc_cfg.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_key.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_bmac.h"
#include "wlc_rate.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "wlc_stf.h"
#include "wl_dbg.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "bmac.h"
#include "rate.h"
#include "channel.h"
#include "main.h"
#include "stf.h"
#define VALID_CHANNEL20_DB(wlc, val) wlc_valid_channel20_db((wlc)->cmi, val)
#define VALID_CHANNEL20_IN_BAND(wlc, bandunit, val) \
@ -1496,7 +1491,7 @@ wlc_valid_chanspec_ext(wlc_cm_info_t *wlc_cm, chanspec_t chspec, bool dualband)
u8 channel = CHSPEC_CHANNEL(chspec);
/* check the chanspec */
if (bcm_chspec_malformed(chspec)) {
if (brcmu_chspec_malformed(chspec)) {
wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
wlc->pub->unit, chspec);
return false;

11
drivers/staging/brcm80211/brcmsmac/wlc_channel.h → drivers/staging/brcm80211/brcmsmac/channel.h
View File

@ -14,11 +14,12 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WLC_CHANNEL_H_
#define _WLC_CHANNEL_H_
#ifndef _BRCM_CHANNEL_H_
#define _BRCM_CHANNEL_H_
#define WLC_TXPWR_DB_FACTOR 4 /* conversion for phy txpwr cacluations that use .25 dB units */
struct wlc_info;
/* maxpwr mapping to 5GHz band channels:
@ -50,6 +51,12 @@ struct wlc_info;
#define WLC_MAXPWR_TBL_SIZE 6 /* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
#define WLC_MAXPWR_MIMO_TBL_SIZE 14 /* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
#define NBANDS(wlc) ((wlc)->pub->_nbands)
#define NBANDS_PUB(pub) ((pub)->_nbands)
#define NBANDS_HW(hw) ((hw)->_nbands)
#define IS_SINGLEBAND_5G(device) 0
/* locale channel and power info. */
typedef struct {
u32 valid_channels;

49
drivers/staging/brcm80211/brcmsmac/d11.h
View File

@ -14,23 +14,10 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _D11_H
#define _D11_H
#ifndef _BRCM_D11_H_
#define _BRCM_D11_H_
#include <sbconfig.h>
#ifndef WL_RSSI_ANT_MAX
#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
#elif WL_RSSI_ANT_MAX != 4
#error "WL_RSSI_ANT_MAX does not match"
#endif
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
#include <linux/ieee80211.h>
#define BCN_TMPL_LEN 512 /* length of the BCN template area */
@ -56,6 +43,12 @@
#define TX_DATA_FIFO TX_AC_BE_FIFO
#define TX_CTL_FIFO TX_AC_VO_FIFO
#ifndef WL_RSSI_ANT_MAX
#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
#elif WL_RSSI_ANT_MAX != 4
#error "WL_RSSI_ANT_MAX does not match"
#endif
typedef volatile struct {
u32 intstatus;
u32 intmask;
@ -112,8 +105,6 @@ typedef volatile struct {
/*
* Host Interface Registers
* - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
* - but definitely not complete
*/
typedef volatile struct _d11regs {
/* Device Control ("semi-standard host registers") */
@ -439,9 +430,6 @@ typedef volatile struct _d11regs {
/* SHM *//* 0x800 - 0xEFE */
u16 PAD[0x380]; /* 0x800 - 0xEFE */
/* SB configuration registers: 0xF00 */
sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
} d11regs_t;
#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
@ -1770,4 +1758,21 @@ typedef struct macstat {
#define SHM_BYT_CNT 0x2 /* IHR location */
#define MAX_BYT_CNT 0x600 /* Maximum frame len */
#endif /* _D11_H */
typedef struct d11cnt {
u32 txfrag;
u32 txmulti;
u32 txfail;
u32 txretry;
u32 txretrie;
u32 rxdup;
u32 txrts;
u32 txnocts;
u32 txnoack;
u32 rxfrag;
u32 rxmulti;
u32 rxcrc;
u32 txfrmsnt;
u32 rxundec;
} d11cnt_t;
#endif /* _BRCM_D11_H_ */

293
drivers/staging/brcm80211/brcmsmac/hnddma.c → drivers/staging/brcm80211/brcmsmac/dma.c
View File

@ -18,22 +18,148 @@
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <hndsoc.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include <soc.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <sbhnddma.h>
#include <hnddma.h>
#include "types.h"
#include "dma.h"
#if defined(__mips__)
#include <asm/addrspace.h>
#endif
#ifdef BRCM_FULLMAC
#error "hnddma.c shouldn't be needed for FULLMAC"
#endif
/*
* Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical address.
*/
#define D64RINGALIGN_BITS 13
#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
#define D64RINGALIGN (1 << D64RINGALIGN_BITS)
#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
/* transmit channel control */
#define D64_XC_XE 0x00000001 /* transmit enable */
#define D64_XC_SE 0x00000002 /* transmit suspend request */
#define D64_XC_LE 0x00000004 /* loopback enable */
#define D64_XC_FL 0x00000010 /* flush request */
#define D64_XC_PD 0x00000800 /* parity check disable */
#define D64_XC_AE 0x00030000 /* address extension bits */
#define D64_XC_AE_SHIFT 16
/* transmit descriptor table pointer */
#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
/* transmit channel status */
#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
#define D64_XS0_XS_SHIFT 28
#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
#define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
#define D64_XS1_XE_SHIFT 28
#define D64_XS1_XE_NOERR 0x00000000 /* no error */
#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
#define D64_XS1_XE_COREE 0x50000000 /* core error */
/* receive channel control */
#define D64_RC_RE 0x00000001 /* receive enable */
#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
#define D64_RC_RO_SHIFT 1
#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
#define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */
#define D64_RC_OC 0x00000400 /* overflow continue */
#define D64_RC_PD 0x00000800 /* parity check disable */
#define D64_RC_AE 0x00030000 /* address extension bits */
#define D64_RC_AE_SHIFT 16
/* flags for dma controller */
#define DMA_CTRL_PEN (1 << 0) /* partity enable */
#define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */
#define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */
#define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */
/* receive descriptor table pointer */
#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
/* receive channel status */
#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
#define D64_RS0_RS_SHIFT 28
#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
#define D64_RS1_RE_SHIFT 28
#define D64_RS1_RE_NOERR 0x00000000 /* no error */
#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
#define D64_RS1_RE_COREE 0x50000000 /* core error */
/* fifoaddr */
#define D64_FA_OFF_MASK 0xffff /* offset */
#define D64_FA_SEL_MASK 0xf0000 /* select */
#define D64_FA_SEL_SHIFT 16
#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
/* descriptor control flags 1 */
#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
#define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
#define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
#define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
#define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
/* descriptor control flags 2 */
#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */
#define D64_CTRL2_AE 0x00030000 /* address extension bits */
#define D64_CTRL2_AE_SHIFT 16
#define D64_CTRL2_PARITY 0x00040000 /* parity bit */
/* control flags in the range [27:20] are core-specific and not defined here */
#define D64_CTRL_CORE_MASK 0x0ff00000
#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */
#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
* There is a compile time check in wlc.c which ensure that this value is at least as big
* as TXOFF. This value is used in dma_rxfill (dma.c).
*/
#define BCMEXTRAHDROOM 172
/* debug/trace */
#ifdef BCMDBG
@ -58,6 +184,15 @@
#define DMA_NONE(args)
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa) = (_val); \
} while (0)
#define d64txregs dregs.d64_u.txregs_64
#define d64rxregs dregs.d64_u.rxregs_64
#define txd64 dregs.d64_u.txd_64
@ -73,9 +208,33 @@ static uint dma_msg_level;
#define R_SM(r) (*(r))
#define W_SM(r, v) (*(r) = (v))
/* One physical DMA segment */
typedef struct {
dmaaddr_t addr;
u32 length;
} dma_seg_t;
typedef struct {
void *oshdmah; /* Opaque handle for OSL to store its information */
uint origsize; /* Size of the virtual packet */
uint nsegs;
dma_seg_t segs[MAX_DMA_SEGS];
} dma_seg_map_t;
/*
* DMA Descriptor
* Descriptors are only read by the hardware, never written back.
*/
typedef volatile struct {
u32 ctrl1; /* misc control bits & bufcount */
u32 ctrl2; /* buffer count and address extension */
u32 addrlow; /* memory address of the date buffer, bits 31:0 */
u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
} dma64dd_t;
/* dma engine software state */
typedef struct dma_info {
struct hnddma_pub hnddma; /* exported structure */
struct dma_pub dma; /* exported structure */
uint *msg_level; /* message level pointer */
char name[MAXNAMEL]; /* callers name for diag msgs */
@ -99,7 +258,7 @@ typedef struct dma_info {
u16 txin; /* index of next descriptor to reclaim */
u16 txout; /* index of next descriptor to post */
void **txp; /* pointer to parallel array of pointers to packets */
hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */
dma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */
dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
u16 txdalign; /* #bytes added to alloc'd mem to align txd */
@ -113,7 +272,7 @@ typedef struct dma_info {
u16 rxin; /* index of next descriptor to reclaim */
u16 rxout; /* index of next descriptor to post */
void **rxp; /* pointer to parallel array of pointers to packets */
hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */
dma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */
dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
@ -274,7 +433,7 @@ const di_fcn_t dma64proc = {
39
};
struct hnddma_pub *dma_attach(char *name, si_t *sih,
struct dma_pub *dma_attach(char *name, struct si_pub *sih,
void *dmaregstx, void *dmaregsrx, uint ntxd,
uint nrxd, uint rxbufsize, int rxextheadroom,
uint nrxpost, uint rxoffset, uint *msg_level)
@ -299,20 +458,20 @@ struct hnddma_pub *dma_attach(char *name, si_t *sih,
/* init dma reg pointer */
di->d64txregs = (dma64regs_t *) dmaregstx;
di->d64rxregs = (dma64regs_t *) dmaregsrx;
di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
di->dma.di_fn = (const di_fcn_t *)&dma64proc;
/* Default flags (which can be changed by the driver calling dma_ctrlflags
* before enable): For backwards compatibility both Rx Overflow Continue
* and Parity are DISABLED.
* supports it.
*/
di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN,
0);
di->dma.di_fn->ctrlflags(&di->dma, DMA_CTRL_ROC | DMA_CTRL_PEN,
0);
DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
"rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
"dmaregstx %p dmaregsrx %p\n", name, "DMA64",
di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize,
di->dma.dmactrlflags, ntxd, nrxd, rxbufsize,
rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
/* make a private copy of our callers name */
@ -427,21 +586,21 @@ struct hnddma_pub *dma_attach(char *name, si_t *sih,
/* allocate DMA mapping vectors */
if (DMASGLIST_ENAB) {
if (ntxd) {
size = ntxd * sizeof(hnddma_seg_map_t);
size = ntxd * sizeof(dma_seg_map_t);
di->txp_dmah = kzalloc(size, GFP_ATOMIC);
if (di->txp_dmah == NULL)
goto fail;
}
if (nrxd) {
size = nrxd * sizeof(hnddma_seg_map_t);
size = nrxd * sizeof(dma_seg_map_t);
di->rxp_dmah = kzalloc(size, GFP_ATOMIC);
if (di->rxp_dmah == NULL)
goto fail;
}
}
return (struct hnddma_pub *) di;
return (struct dma_pub *) di;
fail:
_dma_detach(di);
@ -497,7 +656,7 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
}
if (di->hnddma.dmactrlflags & DMA_CTRL_PEN) {
if (di->dma.dmactrlflags & DMA_CTRL_PEN) {
if (DMA64_DD_PARITY(&ddring[outidx])) {
W_SM(&ddring[outidx].ctrl2,
BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY));
@ -678,7 +837,7 @@ static void _dma_rxinit(dma_info_t *di)
static void _dma_rxenable(dma_info_t *di)
{
uint dmactrlflags = di->hnddma.dmactrlflags;
uint dmactrlflags = di->dma.dmactrlflags;
u32 control;
DMA_TRACE(("%s: dma_rxenable\n", di->name));
@ -760,11 +919,11 @@ static void *_dma_rx(dma_info_t *di)
}
#endif /* BCMDBG */
if ((di->hnddma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
di->name, len));
bcm_pkt_buf_free_skb(head);
di->hnddma.rxgiants++;
brcmu_pkt_buf_free_skb(head);
di->dma.rxgiants++;
goto next_frame;
}
}
@ -811,7 +970,7 @@ static bool _dma_rxfill(dma_info_t *di)
size to be allocated
*/
p = bcm_pkt_buf_get_skb(di->rxbufsize + extra_offset);
p = brcmu_pkt_buf_get_skb(di->rxbufsize + extra_offset);
if (p == NULL) {
DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
@ -821,7 +980,7 @@ static bool _dma_rxfill(dma_info_t *di)
di->name));
ring_empty = true;
}
di->hnddma.rxnobuf++;
di->dma.rxnobuf++;
break;
}
/* reserve an extra headroom, if applicable */
@ -835,7 +994,7 @@ static bool _dma_rxfill(dma_info_t *di)
if (DMASGLIST_ENAB)
memset(&di->rxp_dmah[rxout], 0,
sizeof(hnddma_seg_map_t));
sizeof(dma_seg_map_t));
pa = pci_map_single(di->pbus, p->data,
di->rxbufsize, PCI_DMA_FROMDEVICE);
@ -909,7 +1068,7 @@ static void _dma_rxreclaim(dma_info_t *di)
DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
while ((p = _dma_getnextrxp(di, true)))
bcm_pkt_buf_free_skb(p);
brcmu_pkt_buf_free_skb(p);
}
static void *_dma_getnextrxp(dma_info_t *di, bool forceall)
@ -922,12 +1081,12 @@ static void *_dma_getnextrxp(dma_info_t *di, bool forceall)
static void _dma_txblock(dma_info_t *di)
{
di->hnddma.txavail = 0;
di->dma.txavail = 0;
}
static void _dma_txunblock(dma_info_t *di)
{
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
}
static uint _dma_txactive(dma_info_t *di)
@ -968,14 +1127,14 @@ static uint _dma_rxactive(dma_info_t *di)
static void _dma_counterreset(dma_info_t *di)
{
/* reset all software counter */
di->hnddma.rxgiants = 0;
di->hnddma.rxnobuf = 0;
di->hnddma.txnobuf = 0;
di->dma.rxgiants = 0;
di->dma.rxnobuf = 0;
di->dma.txnobuf = 0;
}
static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
{
uint dmactrlflags = di->hnddma.dmactrlflags;
uint dmactrlflags = di->dma.dmactrlflags;
if (di == NULL) {
DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
@ -1004,7 +1163,7 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
}
}
di->hnddma.dmactrlflags = dmactrlflags;
di->dma.dmactrlflags = dmactrlflags;
return dmactrlflags;
}
@ -1013,7 +1172,7 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
static unsigned long _dma_getvar(dma_info_t *di, const char *name)
{
if (!strcmp(name, "&txavail"))
return (unsigned long)&(di->hnddma.txavail);
return (unsigned long)&(di->dma.txavail);
return 0;
}
@ -1069,7 +1228,7 @@ static void dma64_txinit(dma_info_t *di)
return;
di->txin = di->txout = 0;
di->hnddma.txavail = di->ntxd - 1;
di->dma.txavail = di->ntxd - 1;
/* clear tx descriptor ring */
memset((void *)di->txd64, '\0', (di->ntxd * sizeof(dma64dd_t)));
@ -1080,7 +1239,7 @@ static void dma64_txinit(dma_info_t *di)
if (!di->aligndesc_4k)
_dma_ddtable_init(di, DMA_TX, di->txdpa);
if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0)
control |= D64_XC_PD;
OR_REG(&di->d64txregs->control, control);
@ -1132,9 +1291,9 @@ static void dma64_txreclaim(dma_info_t *di, txd_range_t range)
void *p;
DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
(range == HNDDMA_RANGE_ALL) ? "all" :
(range == DMA_RANGE_ALL) ? "all" :
((range ==
HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
DMA_RANGE_TRANSMITTED) ? "transmitted" :
"transferred")));
if (di->txin == di->txout)
@ -1142,8 +1301,8 @@ static void dma64_txreclaim(dma_info_t *di, txd_range_t range)
while ((p = dma64_getnexttxp(di, range))) {
/* For unframed data, we don't have any packets to free */
if (!(di->hnddma.dmactrlflags & DMA_CTRL_UNFRAMED))
bcm_pkt_buf_free_skb(p);
if (!(di->dma.dmactrlflags & DMA_CTRL_UNFRAMED))
brcmu_pkt_buf_free_skb(p);
}
}
@ -1316,7 +1475,7 @@ static void *dma64_getpos(dma_info_t *di, bool direction)
/* TX of unframed data
*
* Adds a DMA ring descriptor for the data pointed to by "buf".
* This is for DMA of a buffer of data and is unlike other hnddma TX functions
* This is for DMA of a buffer of data and is unlike other dma TX functions
* that take a pointer to a "packet"
* Each call to this is results in a single descriptor being added for "len" bytes of
* data starting at "buf", it doesn't handle chained buffers.
@ -1359,14 +1518,14 @@ static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
}
/* tx flow control */
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
return 0;
outoftxd:
DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
di->hnddma.txavail = 0;
di->hnddma.txnobuf++;
di->dma.txavail = 0;
di->dma.txnobuf++;
return -1;
}
@ -1394,7 +1553,7 @@ static int dma64_txfast(dma_info_t *di, struct sk_buff *p0,
*/
for (p = p0; p; p = next) {
uint nsegs, j;
hnddma_seg_map_t *map;
dma_seg_map_t *map;
data = p->data;
len = p->len;
@ -1410,7 +1569,7 @@ static int dma64_txfast(dma_info_t *di, struct sk_buff *p0,
/* get physical address of buffer start */
if (DMASGLIST_ENAB)
memset(&di->txp_dmah[txout], 0,
sizeof(hnddma_seg_map_t));
sizeof(dma_seg_map_t));
pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE);
@ -1474,26 +1633,26 @@ static int dma64_txfast(dma_info_t *di, struct sk_buff *p0,
di->xmtptrbase + I2B(txout, dma64dd_t));
/* tx flow control */
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
return 0;
outoftxd:
DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
bcm_pkt_buf_free_skb(p0);
di->hnddma.txavail = 0;
di->hnddma.txnobuf++;
brcmu_pkt_buf_free_skb(p0);
di->dma.txavail = 0;
di->dma.txnobuf++;
return -1;
}
/*
* Reclaim next completed txd (txds if using chained buffers) in the range
* specified and return associated packet.
* If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
* If range is DMA_RANGE_TRANSMITTED, reclaim descriptors that have be
* transmitted as noted by the hardware "CurrDescr" pointer.
* If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
* If range is DMA_RANGE_TRANSFERED, reclaim descriptors that have be
* transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
* If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
* If range is DMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
* return associated packet regardless of the value of hardware pointers.
*/
static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
@ -1503,9 +1662,9 @@ static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
void *txp;
DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
(range == HNDDMA_RANGE_ALL) ? "all" :
(range == DMA_RANGE_ALL) ? "all" :
((range ==
HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
DMA_RANGE_TRANSMITTED) ? "transmitted" :
"transferred")));
if (di->ntxd == 0)
@ -1514,7 +1673,7 @@ static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
txp = NULL;
start = di->txin;
if (range == HNDDMA_RANGE_ALL)
if (range == DMA_RANGE_ALL)
end = di->txout;
else {
dma64regs_t *dregs = di->d64txregs;
@ -1525,7 +1684,7 @@ static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
D64_XS0_CD_MASK) -
di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t));
if (range == HNDDMA_RANGE_TRANSFERED) {
if (range == DMA_RANGE_TRANSFERED) {
active_desc =
(u16) (R_REG(&dregs->status1) &
D64_XS1_AD_MASK);
@ -1542,7 +1701,7 @@ static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
for (i = start; i != end && !txp; i = NEXTTXD(i)) {
dmaaddr_t pa;
hnddma_seg_map_t *map = NULL;
dma_seg_map_t *map = NULL;
uint size, j, nsegs;
PHYSADDRLOSET(pa,
@ -1579,7 +1738,7 @@ static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
di->txin = i;
/* tx flow control */
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
return txp;
@ -1696,8 +1855,8 @@ static void dma64_txrotate(dma_info_t *di)
/* Move the map */
if (DMASGLIST_ENAB) {
memcpy(&di->txp_dmah[new], &di->txp_dmah[old],
sizeof(hnddma_seg_map_t));
memset(&di->txp_dmah[old], 0, sizeof(hnddma_seg_map_t));
sizeof(dma_seg_map_t));
memset(&di->txp_dmah[old], 0, sizeof(dma_seg_map_t));
}
di->txp[old] = NULL;
@ -1706,14 +1865,14 @@ static void dma64_txrotate(dma_info_t *di)
/* update txin and txout */
di->txin = ad;
di->txout = TXD(di->txout + rot);
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
/* kick the chip */
W_REG(&di->d64txregs->ptr,
di->xmtptrbase + I2B(di->txout, dma64dd_t));
}
uint dma_addrwidth(si_t *sih, void *dmaregs)
uint dma_addrwidth(struct si_pub *sih, void *dmaregs)
{
/* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
/* DMA engine is 64-bit capable */
@ -1736,7 +1895,7 @@ uint dma_addrwidth(si_t *sih, void *dmaregs)
* engine. This function calls a caller-supplied function for each packet in
* the caller specified dma chain.
*/
void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
(void *pkt, void *arg_a), void *arg_a)
{
dma_info_t *di = (dma_info_t *) dmah;

139
drivers/staging/brcm80211/include/hnddma.h → drivers/staging/brcm80211/brcmsmac/dma.h
View File

@ -14,13 +14,42 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hnddma_h_
#define _hnddma_h_
#ifndef _BRCM_DMA_H_
#define _BRCM_DMA_H_
#ifndef _hnddma_pub_
#define _hnddma_pub_
struct hnddma_pub;
#endif /* _hnddma_pub_ */
#include "types.h" /* forward structure declarations */
#ifndef _dma_pub_
#define _dma_pub_
struct dma_pub;
#endif /* _dma_pub_ */
/* DMA structure:
* support two DMA engines: 32 bits address or 64 bit addressing
* basic DMA register set is per channel(transmit or receive)
* a pair of channels is defined for convenience
*/
/* 32 bits addressing */
typedef volatile struct { /* diag access */
u32 fifoaddr; /* diag address */
u32 fifodatalow; /* low 32bits of data */
u32 fifodatahigh; /* high 32bits of data */
u32 pad; /* reserved */
} dma32diag_t;
/* 64 bits addressing */
/* dma registers per channel(xmt or rcv) */
typedef volatile struct {
u32 control; /* enable, et al */
u32 ptr; /* last descriptor posted to chip */
u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
u32 status0; /* current descriptor, xmt state */
u32 status1; /* active descriptor, xmt error */
} dma64regs_t;
/* map/unmap direction */
#define DMA_TX 1 /* TX direction for DMA */
@ -29,60 +58,60 @@ struct hnddma_pub;
/* range param for dma_getnexttxp() and dma_txreclaim */
typedef enum txd_range {
HNDDMA_RANGE_ALL = 1,
HNDDMA_RANGE_TRANSMITTED,
HNDDMA_RANGE_TRANSFERED
DMA_RANGE_ALL = 1,
DMA_RANGE_TRANSMITTED,
DMA_RANGE_TRANSFERED
} txd_range_t;
/* dma function type */
typedef void (*di_detach_t) (struct hnddma_pub *dmah);
typedef bool(*di_txreset_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxreset_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxidle_t) (struct hnddma_pub *dmah);
typedef void (*di_txinit_t) (struct hnddma_pub *dmah);
typedef bool(*di_txenabled_t) (struct hnddma_pub *dmah);
typedef void (*di_rxinit_t) (struct hnddma_pub *dmah);
typedef void (*di_txsuspend_t) (struct hnddma_pub *dmah);
typedef void (*di_txresume_t) (struct hnddma_pub *dmah);
typedef bool(*di_txsuspended_t) (struct hnddma_pub *dmah);
typedef bool(*di_txsuspendedidle_t) (struct hnddma_pub *dmah);
typedef int (*di_txfast_t) (struct hnddma_pub *dmah, struct sk_buff *p,
typedef void (*di_detach_t) (struct dma_pub *dmah);
typedef bool(*di_txreset_t) (struct dma_pub *dmah);
typedef bool(*di_rxreset_t) (struct dma_pub *dmah);
typedef bool(*di_rxidle_t) (struct dma_pub *dmah);
typedef void (*di_txinit_t) (struct dma_pub *dmah);
typedef bool(*di_txenabled_t) (struct dma_pub *dmah);
typedef void (*di_rxinit_t) (struct dma_pub *dmah);
typedef void (*di_txsuspend_t) (struct dma_pub *dmah);
typedef void (*di_txresume_t) (struct dma_pub *dmah);
typedef bool(*di_txsuspended_t) (struct dma_pub *dmah);
typedef bool(*di_txsuspendedidle_t) (struct dma_pub *dmah);
typedef int (*di_txfast_t) (struct dma_pub *dmah, struct sk_buff *p,
bool commit);
typedef int (*di_txunframed_t) (struct hnddma_pub *dmah, void *p, uint len,
typedef int (*di_txunframed_t) (struct dma_pub *dmah, void *p, uint len,
bool commit);
typedef void *(*di_getpos_t) (struct hnddma_pub *di, bool direction);
typedef void (*di_fifoloopbackenable_t) (struct hnddma_pub *dmah);
typedef bool(*di_txstopped_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxstopped_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxenable_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxenabled_t) (struct hnddma_pub *dmah);
typedef void *(*di_rx_t) (struct hnddma_pub *dmah);
typedef bool(*di_rxfill_t) (struct hnddma_pub *dmah);
typedef void (*di_txreclaim_t) (struct hnddma_pub *dmah, txd_range_t range);
typedef void (*di_rxreclaim_t) (struct hnddma_pub *dmah);
typedef unsigned long (*di_getvar_t) (struct hnddma_pub *dmah,
typedef void *(*di_getpos_t) (struct dma_pub *di, bool direction);
typedef void (*di_fifoloopbackenable_t) (struct dma_pub *dmah);
typedef bool(*di_txstopped_t) (struct dma_pub *dmah);
typedef bool(*di_rxstopped_t) (struct dma_pub *dmah);
typedef bool(*di_rxenable_t) (struct dma_pub *dmah);
typedef bool(*di_rxenabled_t) (struct dma_pub *dmah);
typedef void *(*di_rx_t) (struct dma_pub *dmah);
typedef bool(*di_rxfill_t) (struct dma_pub *dmah);
typedef void (*di_txreclaim_t) (struct dma_pub *dmah, txd_range_t range);
typedef void (*di_rxreclaim_t) (struct dma_pub *dmah);
typedef unsigned long (*di_getvar_t) (struct dma_pub *dmah,
const char *name);
typedef void *(*di_getnexttxp_t) (struct hnddma_pub *dmah, txd_range_t range);
typedef void *(*di_getnextrxp_t) (struct hnddma_pub *dmah, bool forceall);
typedef void *(*di_peeknexttxp_t) (struct hnddma_pub *dmah);
typedef void *(*di_peeknextrxp_t) (struct hnddma_pub *dmah);
typedef void (*di_rxparam_get_t) (struct hnddma_pub *dmah, u16 *rxoffset,
typedef void *(*di_getnexttxp_t) (struct dma_pub *dmah, txd_range_t range);
typedef void *(*di_getnextrxp_t) (struct dma_pub *dmah, bool forceall);
typedef void *(*di_peeknexttxp_t) (struct dma_pub *dmah);
typedef void *(*di_peeknextrxp_t) (struct dma_pub *dmah);
typedef void (*di_rxparam_get_t) (struct dma_pub *dmah, u16 *rxoffset,
u16 *rxbufsize);
typedef void (*di_txblock_t) (struct hnddma_pub *dmah);
typedef void (*di_txunblock_t) (struct hnddma_pub *dmah);
typedef uint(*di_txactive_t) (struct hnddma_pub *dmah);
typedef void (*di_txrotate_t) (struct hnddma_pub *dmah);
typedef void (*di_counterreset_t) (struct hnddma_pub *dmah);
typedef uint(*di_ctrlflags_t) (struct hnddma_pub *dmah, uint mask, uint flags);
typedef char *(*di_dump_t) (struct hnddma_pub *dmah, struct bcmstrbuf *b,
typedef void (*di_txblock_t) (struct dma_pub *dmah);
typedef void (*di_txunblock_t) (struct dma_pub *dmah);
typedef uint(*di_txactive_t) (struct dma_pub *dmah);
typedef void (*di_txrotate_t) (struct dma_pub *dmah);
typedef void (*di_counterreset_t) (struct dma_pub *dmah);
typedef uint(*di_ctrlflags_t) (struct dma_pub *dmah, uint mask, uint flags);
typedef char *(*di_dump_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
bool dumpring);
typedef char *(*di_dumptx_t) (struct hnddma_pub *dmah, struct bcmstrbuf *b,
typedef char *(*di_dumptx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
bool dumpring);
typedef char *(*di_dumprx_t) (struct hnddma_pub *dmah, struct bcmstrbuf *b,
typedef char *(*di_dumprx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
bool dumpring);
typedef uint(*di_rxactive_t) (struct hnddma_pub *dmah);
typedef uint(*di_txpending_t) (struct hnddma_pub *dmah);
typedef uint(*di_txcommitted_t) (struct hnddma_pub *dmah);
typedef uint(*di_rxactive_t) (struct dma_pub *dmah);
typedef uint(*di_txpending_t) (struct dma_pub *dmah);
typedef uint(*di_txcommitted_t) (struct dma_pub *dmah);
/* dma opsvec */
typedef struct di_fcn_s {
@ -136,7 +165,7 @@ typedef struct di_fcn_s {
* Exported data structure (read-only)
*/
/* export structure */
struct hnddma_pub {
struct dma_pub {
const di_fcn_t *di_fn; /* DMA function pointers */
uint txavail; /* # free tx descriptors */
uint dmactrlflags; /* dma control flags */
@ -148,7 +177,7 @@ struct hnddma_pub {
uint txnobuf; /* tx out of dma descriptors */
};
extern struct hnddma_pub *dma_attach(char *name, si_t *sih,
extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
void *dmaregstx, void *dmaregsrx, uint ntxd,
uint nrxd, uint rxbufsize, int rxextheadroom,
uint nrxpost, uint rxoffset, uint *msg_level);
@ -201,8 +230,8 @@ extern const di_fcn_t dma64proc;
* SB attach provides ability to probe backplane and dma core capabilities
* This info is needed by DMA_ALLOC_CONSISTENT in dma attach
*/
extern uint dma_addrwidth(si_t *sih, void *dmaregs);
void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
extern uint dma_addrwidth(struct si_pub *sih, void *dmaregs);
void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
(void *pkt, void *arg_a), void *arg_a);
/*
@ -223,4 +252,4 @@ static inline void dma_spin_for_len(uint len, struct sk_buff *head)
#endif /* defined(__mips__) */
}
#endif /* _hnddma_h_ */
#endif /* _BRCM_DMA_H_ */

704
drivers/staging/brcm80211/brcmsmac/wl_mac80211.c → drivers/staging/brcm80211/brcmsmac/mac80211_if.c
View File

File diff suppressed because it is too large Load Diff

74
drivers/staging/brcm80211/brcmsmac/wl_mac80211.h → drivers/staging/brcm80211/brcmsmac/mac80211_if.h
View File

@ -14,41 +14,45 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_mac80211_h_
#define _wl_mac80211_h_
#ifndef _BRCM_MAC80211_IF_H_
#define _BRCM_MAC80211_IF_H_
/* softmac ioctl definitions */
#define WLC_SET_SHORTSLOT_OVERRIDE 146
/* BMAC Note: High-only driver is no longer working in softirq context as it needs to block and
* sleep so perimeter lock has to be a semaphore instead of spinlock. This requires timers to be
* submitted to workqueue instead of being on kernel timer
*/
struct wl_timer {
struct brcms_timer {
struct timer_list timer;
struct wl_info *wl;
struct brcms_info *wl;
void (*fn) (void *);
void *arg; /* argument to fn */
uint ms;
bool periodic;
bool set;
struct wl_timer *next;
struct brcms_timer *next;
#ifdef BCMDBG
char *name; /* Description of the timer */
#endif
};
struct wl_if {
struct brcms_if {
uint subunit; /* WDS/BSS unit */
struct pci_dev *pci_dev;
};
#define WL_MAX_FW 4
struct wl_firmware {
#define MAX_FW_IMAGES 4
struct brcms_firmware {
u32 fw_cnt;
const struct firmware *fw_bin[WL_MAX_FW];
const struct firmware *fw_hdr[WL_MAX_FW];
u32 hdr_num_entries[WL_MAX_FW];
const struct firmware *fw_bin[MAX_FW_IMAGES];
const struct firmware *fw_hdr[MAX_FW_IMAGES];
u32 hdr_num_entries[MAX_FW_IMAGES];
};
struct wl_info {
struct brcms_info {
struct wlc_pub *pub; /* pointer to public wlc state */
void *wlc; /* pointer to private common os-independent data */
u32 magic;
@ -57,29 +61,49 @@ struct wl_info {
spinlock_t lock; /* per-device perimeter lock */
spinlock_t isr_lock; /* per-device ISR synchronization lock */
/* bus type and regsva for unmap in brcms_free() */
uint bcm_bustype; /* bus type */
bool piomode; /* set from insmod argument */
void *regsva; /* opaque chip registers virtual address */
/* timer related fields */
atomic_t callbacks; /* # outstanding callback functions */
struct wl_timer *timers; /* timer cleanup queue */
struct brcms_timer *timers; /* timer cleanup queue */
struct tasklet_struct tasklet; /* dpc tasklet */
bool resched; /* dpc needs to be and is rescheduled */
#ifdef LINUXSTA_PS
u32 pci_psstate[16]; /* pci ps-state save/restore */
#endif
struct wl_firmware fw;
struct brcms_firmware fw;
struct wiphy *wiphy;
};
#define WL_LOCK(wl) spin_lock_bh(&(wl)->lock)
#define WL_UNLOCK(wl) spin_unlock_bh(&(wl)->lock)
/* misc callbacks */
struct brcms_info;
struct brcms_if;
struct wlc_if;
extern void brcms_init(struct brcms_info *wl);
extern uint brcms_reset(struct brcms_info *wl);
extern void brcms_intrson(struct brcms_info *wl);
extern u32 brcms_intrsoff(struct brcms_info *wl);
extern void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
extern int brcms_up(struct brcms_info *wl);
extern void brcms_down(struct brcms_info *wl);
extern void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
bool state, int prio);
extern bool wl_alloc_dma_resources(struct brcms_info *wl, uint dmaddrwidth);
extern bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
/* locking from inside wl_isr */
#define WL_ISRLOCK(wl, flags) do {spin_lock(&(wl)->isr_lock); (void)(flags); } while (0)
#define WL_ISRUNLOCK(wl, flags) do {spin_unlock(&(wl)->isr_lock); (void)(flags); } while (0)
/* timer functions */
struct brcms_timer;
extern struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
void (*fn) (void *arg), void *arg,
const char *name);
extern void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *timer);
extern void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *timer,
uint ms, int periodic);
extern bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *timer);
extern void brcms_msleep(struct brcms_info *wl, uint ms);
/* locking under WL_LOCK() to synchronize with wl_isr */
#define INT_LOCK(wl, flags) spin_lock_irqsave(&(wl)->isr_lock, flags)
#define INT_UNLOCK(wl, flags) spin_unlock_irqrestore(&(wl)->isr_lock, flags)
#endif /* _wl_mac80211_h_ */
#endif /* _BRCM_MAC80211_IF_H_ */

2102
drivers/staging/brcm80211/brcmsmac/wlc_main.c → drivers/staging/brcm80211/brcmsmac/main.c
View File

File diff suppressed because it is too large Load Diff

322
drivers/staging/brcm80211/brcmsmac/wlc_main.h → drivers/staging/brcm80211/brcmsmac/main.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_h_
#define _wlc_h_
#ifndef _BRCM_MAIN_H_
#define _BRCM_MAIN_H_
#define MA_WINDOW_SZ 8 /* moving average window size */
#define WL_HWRXOFF 38 /* chip rx buffer offset */
@ -23,7 +23,19 @@
#define MAXCOREREV 28 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
#define WLC_MAXMODULES 22 /* max # wlc_module_register() calls */
#define WLC_BITSCNT(x) bcm_bitcount((u8 *)&(x), sizeof(u8))
#define SEQNUM_SHIFT 4
#define AMPDU_DELIMITER_LEN 4
#define SEQNUM_MAX 0x1000
#define APHY_CWMIN 15
#define PHY_CWMAX 1023
#define EDCF_AIFSN_MIN 1
#define FRAGNUM_MASK 0xF
#define NTXRATE 64 /* # tx MPDUs rate is reported for */
#define WLC_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
/* Maximum wait time for a MAC suspend */
#define WLC_MAX_MAC_SUSPEND 83000 /* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */
@ -35,6 +47,26 @@
/* transmit buffer max headroom for protocol headers */
#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
#define AC_COUNT 4
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
* #define <NAME>_S 4
* ...
* regval = R_REG(osh, &regs->regfoo);
* field = GFIELD(regval, <NAME>);
* regval = SFIELD(regval, <NAME>, 1);
* W_REG(osh, &regs->regfoo, regval);
*/
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
/* For managing scan result lists */
struct wlc_bss_list {
uint count;
@ -136,7 +168,7 @@ extern const u8 prio2fifo[];
#define MAXTXFRAMEBURST 8 /* vanilla xpress mode: max frames/burst */
#define MAXFRAMEBURST_TXOP 10000 /* Frameburst TXOP in usec */
/* Per-AC retry limit register definitions; uses bcmdefs.h bitfield macros */
/* Per-AC retry limit register definitions; uses defs.h bitfield macros */
#define EDCF_SHORT_S 0
#define EDCF_SFB_S 4
#define EDCF_LONG_S 8
@ -146,6 +178,8 @@ extern const u8 prio2fifo[];
#define EDCF_LONG_M BITFIELD_MASK(4)
#define EDCF_LFB_M BITFIELD_MASK(4)
#define NFIFO 6 /* # tx/rx fifopairs */
#define WLC_WME_RETRY_SHORT_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SHORT)
#define WLC_WME_RETRY_SFB_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SFB)
#define WLC_WME_RETRY_LONG_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_LONG)
@ -208,19 +242,6 @@ struct wlc_protection {
s8 nongf_override; /* override for use of GF protection */
s8 n_pam_override; /* override for preamble: MM or GF */
bool n_obss; /* indicated OBSS Non-HT STA present */
uint longpre_detect_timeout; /* #sec until long preamble bcns gone */
uint barker_detect_timeout; /* #sec until bcns signaling Barker long preamble */
/* only is gone */
uint ofdm_ibss_timeout; /* #sec until ofdm IBSS beacons gone */
uint ofdm_ovlp_timeout; /* #sec until ofdm overlapping BSS bcns gone */
uint nonerp_ibss_timeout; /* #sec until nonerp IBSS beacons gone */
uint nonerp_ovlp_timeout; /* #sec until nonerp overlapping BSS bcns gone */
uint g_ibss_timeout; /* #sec until bcns signaling Use_Protection gone */
uint n_ibss_timeout; /* #sec until bcns signaling Use_OFDM_Protection gone */
uint ht20in40_ovlp_timeout; /* #sec until 20MHz overlapping OPMODE gone */
uint ht20in40_ibss_timeout; /* #sec until 20MHz-only HT station bcns gone */
uint non_gf_ibss_timeout; /* #sec until non-GF bcns gone */
};
/* anything affects the single/dual streams/antenna operation */
@ -276,6 +297,49 @@ struct wlc_stf {
#define WLC_HT_WEP_RESTRICT 0x01 /* restrict HT with WEP */
#define WLC_HT_TKIP_RESTRICT 0x02 /* restrict HT with TKIP */
/* Maximum # of keys that wl driver supports in S/W.
* Keys supported in H/W is less than or equal to WSEC_MAX_KEYS.
*/
#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
#define WLC_DEFAULT_KEYS 4 /* Default # of keys */
/*
* Max # of keys currently supported:
*
* s/w keys if WSEC_SW(wlc->wsec).
* h/w keys otherwise.
*/
#define WLC_MAX_WSEC_KEYS(wlc) WSEC_MAX_KEYS
/* number of 802.11 default (non-paired, group keys) */
#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
typedef struct wsec_iv {
u32 hi; /* upper 32 bits of IV */
u16 lo; /* lower 16 bits of IV */
} wsec_iv_t;
#define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */
typedef struct wsec_key {
u8 ea[ETH_ALEN]; /* per station */
u8 idx; /* key index in wsec_keys array */
u8 id; /* key ID [0-3] */
u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
u8 rcmta; /* rcmta entry index, same as idx by default */
u16 flags; /* misc flags */
u8 algo_hw; /* cache for hw register */
u8 aes_mode; /* cache for hw register */
s8 iv_len; /* IV length */
s8 icv_len; /* ICV length */
u32 len; /* key length..don't move this var */
/* data is 4byte aligned */
u8 data[WLAN_MAX_KEY_LEN]; /* key data */
wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */
wsec_iv_t txiv; /* Tx IV */
} wsec_key_t;
/*
* core state (mac)
*/
@ -303,7 +367,7 @@ struct wlcband {
wlc_phy_t *pi; /* pointer to phy specific information */
bool abgphy_encore;
u8 gmode; /* currently active gmode (see wlioctl.h) */
u8 gmode; /* currently active gmode */
struct scb *hwrs_scb; /* permanent scb for hw rateset */
@ -336,7 +400,7 @@ struct pkt_cb {
/* module control blocks */
struct modulecb {
char name[32]; /* module name : NULL indicates empty array member */
const bcm_iovar_t *iovars; /* iovar table */
const struct brcmu_iovar *iovars; /* iovar table */
void *hdl; /* handle passed when handler 'doiovar' is called */
watchdog_fn_t watchdog_fn; /* watchdog handler */
iovar_fn_t iovar_fn; /* iovar handler */
@ -355,6 +419,24 @@ struct dumpcb_s {
struct dumpcb_s *next;
};
struct edcf_acparam {
u8 ACI;
u8 ECW;
u16 TXOP;
} __attribute__((packed));
typedef struct edcf_acparam edcf_acparam_t;
struct wme_param_ie {
u8 oui[3];
u8 type;
u8 subtype;
u8 version;
u8 qosinfo;
u8 rsvd;
edcf_acparam_t acparam[AC_COUNT];
} __attribute__((packed));
typedef struct wme_param_ie wme_param_ie_t;
/* virtual interface */
struct wlc_if {
struct wlc_if *next;
@ -364,7 +446,7 @@ struct wlc_if {
* AID2PVBMAP(scb).
*/
u8 flags; /* flags for the interface */
struct wl_if *wlif; /* pointer to wlif */
struct brcms_if *wlif; /* pointer to wlif */
struct wlc_txq_info *qi; /* pointer to associated tx queue */
union {
struct scb *scb; /* pointer to scb if WLC_IFTYPE_WDS */
@ -372,8 +454,8 @@ struct wlc_if {
} u;
};
/* flags for the interface */
#define WLC_IF_LINKED 0x02 /* this interface is linked to a wl_if */
/* flags for the interface, this interface is linked to a brcms_if */
#define WLC_IF_LINKED 0x02
struct wlc_hwband {
int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */
@ -397,7 +479,7 @@ struct wlc_hw_info {
struct wlc_info *wlc;
/* fifo */
struct hnddma_pub *di[NFIFO]; /* hnddma handles, per fifo */
struct dma_pub *di[NFIFO]; /* dma handles, per fifo */
uint unit; /* device instance number */
@ -413,7 +495,7 @@ struct wlc_hw_info {
u32 machwcap_backup; /* backup of machwcap */
u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */
si_t *sih; /* SB handle (cookie for siutils calls) */
struct si_pub *sih; /* SI handle (cookie for siutils calls) */
char *vars; /* "environment" name=value */
uint vars_size; /* size of vars, free vars on detach */
d11regs_t *regs; /* pointer to device registers */
@ -484,7 +566,7 @@ struct wlc_txq_info {
*/
struct wlc_info {
struct wlc_pub *pub; /* pointer to wlc public state */
struct wl_info *wl; /* pointer to os-specific private state */
struct brcms_info *wl; /* pointer to os-specific private state */
d11regs_t *regs; /* pointer to device registers */
struct wlc_hw_info *hw; /* HW related state used primarily by BMAC */
@ -528,8 +610,6 @@ struct wlc_info {
struct antsel_info *asi; /* antsel module handler */
wlc_cm_info_t *cmi; /* channel manager module handler */
void *btparam; /* bus type specific cookie */
uint vars_size; /* size of vars, free vars on detach */
u16 vendorid; /* PCI vendor id */
@ -544,7 +624,6 @@ struct wlc_info {
bool bandinit_pending; /* track band init in auto band */
bool radio_monitor; /* radio timer is running */
bool down_override; /* true=down */
bool going_down; /* down path intermediate variable */
bool mpc; /* enable minimum power consumption */
@ -553,16 +632,10 @@ struct wlc_info {
u8 mpc_delay_off; /* delay radio disable by # of watchdog cnt */
u8 prev_non_delay_mpc; /* prev state wlc_is_non_delay_mpc */
/* timer */
struct wl_timer *wdtimer; /* timer for watchdog routine */
uint fast_timer; /* Periodic timeout for 'fast' timer */
uint slow_timer; /* Periodic timeout for 'slow' timer */
uint glacial_timer; /* Periodic timeout for 'glacial' timer */
uint phycal_mlo; /* last time measurelow calibration was done */
uint phycal_txpower; /* last time txpower calibration was done */
struct wl_timer *radio_timer; /* timer for hw radio button monitor routine */
struct wl_timer *pspoll_timer; /* periodic pspoll timer */
/* timer for watchdog routine */
struct brcms_timer *wdtimer;
/* timer for hw radio button monitor routine */
struct brcms_timer *radio_timer;
/* promiscuous */
bool monitor; /* monitor (MPDU sniffing) mode */
@ -570,30 +643,11 @@ struct wlc_info {
bool bcnmisc_scan; /* bcns promisc mode override for scan */
bool bcnmisc_monitor; /* bcns promisc mode override for monitor */
u8 bcn_wait_prd; /* max waiting period (for beacon) in 1024TU */
/* driver feature */
bool _rifs; /* enable per-packet rifs */
s32 rifs_advert; /* RIFS mode advertisement */
s8 sgi_tx; /* sgi tx */
bool wet; /* true if wireless ethernet bridging mode */
/* AP-STA synchronization, power save */
bool check_for_unaligned_tbtt; /* check unaligned tbtt flag */
bool PM_override; /* no power-save flag, override PM(user input) */
bool PMenabled; /* current power-management state (CAM or PS) */
bool PMpending; /* waiting for tx status with PM indicated set */
bool PMblocked; /* block any PSPolling in PS mode, used to buffer
* AP traffic, also used to indicate in progress
* of scan, rm, etc. off home channel activity.
*/
bool PSpoll; /* whether there is an outstanding PS-Poll frame */
u8 PM; /* power-management mode (CAM, PS or FASTPS) */
bool PMawakebcn; /* bcn recvd during current waking state */
bool WME_PM_blocked; /* Can STA go to PM when in WME Auto mode */
bool wake; /* host-specified PS-mode sleep state */
u8 pspoll_prd; /* pspoll interval in milliseconds */
u8 bcn_li_bcn; /* beacon listen interval in # beacons */
u8 bcn_li_dtim; /* beacon listen interval in # dtims */
@ -602,18 +656,14 @@ struct wlc_info {
/* WME */
ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */
bool wme_apsd; /* enable Advanced Power Save Delivery */
ac_bitmap_t wme_admctl; /* bit i set if AC i under admission control */
u16 edcf_txop[AC_COUNT]; /* current txop for each ac */
wme_param_ie_t wme_param_ie; /* WME parameter info element, which on STA
* contains parameters in use locally, and on
* AP contains parameters advertised to STA
* in beacons and assoc responses.
*/
bool wme_prec_queuing; /* enable/disable non-wme STA prec queuing */
u16 wme_retries[AC_COUNT]; /* per-AC retry limits */
int vlan_mode; /* OK to use 802.1Q Tags (ON, OFF, AUTO) */
u16 tx_prec_map; /* Precedence map based on HW FIFO space */
u16 fifo2prec_map[NFIFO]; /* pointer to fifo2_prec map based on WME */
@ -623,10 +673,6 @@ struct wlc_info {
*/
struct wlc_bsscfg *bsscfg[WLC_MAXBSSCFG];
struct wlc_bsscfg *cfg; /* the primary bsscfg (can be AP or STA) */
u8 stas_associated; /* count of ASSOCIATED STA bsscfgs */
u8 aps_associated; /* count of UP AP bsscfgs */
u8 block_datafifo; /* prohibit posting frames to data fifos */
bool bcmcfifo_drain; /* TX_BCMC_FIFO is set to drain */
/* tx queue */
struct wlc_txq_info *tx_queues; /* common TX Queue list */
@ -638,43 +684,24 @@ struct wlc_info {
* treated as sw keys (used for debugging)
*/
struct modulecb *modulecb;
struct dumpcb_s *dumpcb_head;
u8 mimoft; /* SIGN or 11N */
u8 mimo_band_bwcap; /* bw cap per band type */
s8 txburst_limit_override; /* tx burst limit override */
u16 txburst_limit; /* tx burst limit value */
s8 cck_40txbw; /* 11N, cck tx b/w override when in 40MHZ mode */
s8 ofdm_40txbw; /* 11N, ofdm tx b/w override when in 40MHZ mode */
s8 mimo_40txbw; /* 11N, mimo tx b/w override when in 40MHZ mode */
/* HT CAP IE being advertised by this node: */
struct ieee80211_ht_cap ht_cap;
uint seckeys; /* 54 key table shm address */
uint tkmickeys; /* 12 TKIP MIC key table shm address */
wlc_bss_info_t *default_bss; /* configured BSS parameters */
u16 AID; /* association ID */
u16 counter; /* per-sdu monotonically increasing counter */
u16 mc_fid_counter; /* BC/MC FIFO frame ID counter */
bool ibss_allowed; /* false, all IBSS will be ignored during a scan
* and the driver will not allow the creation of
* an IBSS network
*/
bool ibss_coalesce_allowed;
char country_default[WLC_CNTRY_BUF_SZ]; /* saved country for leaving 802.11d
* auto-country mode
*/
char autocountry_default[WLC_CNTRY_BUF_SZ]; /* initial country for 802.11d
* auto-country mode
*/
#ifdef BCMDBG
bcm_tlv_t *country_ie_override; /* debug override of announced Country IE */
#endif
u16 prb_resp_timeout; /* do not send prb resp if request older than this,
* 0 = disable
*/
@ -696,44 +723,17 @@ struct wlc_info {
u16 LFBL; /* Long Frame Rate Fallback Limit */
/* network config */
bool shortpreamble; /* currently operating with CCK ShortPreambles */
bool shortslot; /* currently using 11g ShortSlot timing */
s8 barker_preamble; /* current Barker Preamble Mode */
s8 shortslot_override; /* 11g ShortSlot override */
bool include_legacy_erp; /* include Legacy ERP info elt ID 47 as well as g ID 42 */
bool barker_overlap_control; /* true: be aware of overlapping BSSs for barker */
bool ignore_bcns; /* override: ignore non shortslot bcns in a 11g network */
bool legacy_probe; /* restricts probe requests to CCK rates */
struct wlc_protection *protection;
s8 PLCPHdr_override; /* 802.11b Preamble Type override */
struct wlc_stf *stf;
struct pkt_cb *pkt_callback; /* tx completion callback handlers */
u32 txretried; /* tx retried number in one msdu */
ratespec_t bcn_rspec; /* save bcn ratespec purpose */
bool apsd_sta_usp; /* Unscheduled Service Period in progress on STA */
struct wl_timer *apsd_trigger_timer; /* timer for wme apsd trigger frames */
u32 apsd_trigger_timeout; /* timeout value for apsd_trigger_timer (in ms)
* 0 == disable
*/
ac_bitmap_t apsd_trigger_ac; /* Permissible Access Category in which APSD Null
* Trigger frames can be send
*/
u8 htphy_membership; /* HT PHY membership */
bool _regulatory_domain; /* 802.11d enabled? */
u8 mimops_PM;
u8 txpwr_percent; /* power output percentage */
u8 ht_wsec_restriction; /* the restriction of HT with TKIP or WEP */
uint tempsense_lasttime;
u16 tx_duty_cycle_ofdm; /* maximum allowed duty cycle for OFDM */
@ -741,7 +741,6 @@ struct wlc_info {
u16 next_bsscfg_ID;
struct wlc_if *wlcif_list; /* linked list of wlc_if structs */
struct wlc_txq_info *pkt_queue; /* txq for transmit packets */
u32 mpc_dur; /* total time (ms) in mpc mode except for the
* portion since radio is turned off last time
@ -749,8 +748,6 @@ struct wlc_info {
u32 mpc_laston_ts; /* timestamp (ms) when radio is turned off last
* time
*/
bool pr80838_war;
uint hwrxoff;
struct wiphy *wiphy;
};
@ -767,6 +764,84 @@ struct antsel_info {
wlc_antselcfg_t antcfg_cur; /* current antenna config (auto) */
};
/* BSS configuration state */
struct wlc_bsscfg {
struct wlc_info *wlc; /* wlc to which this bsscfg belongs to. */
bool up; /* is this configuration up operational */
bool enable; /* is this configuration enabled */
bool associated; /* is BSS in ASSOCIATED state */
bool BSS; /* infraustructure or adhac */
bool dtim_programmed;
u8 SSID_len; /* the length of SSID */
u8 SSID[IEEE80211_MAX_SSID_LEN]; /* SSID string */
struct scb *bcmc_scb[MAXBANDS]; /* one bcmc_scb per band */
s8 _idx; /* the index of this bsscfg,
* assigned at wlc_bsscfg_alloc()
*/
/* MAC filter */
uint nmac; /* # of entries on maclist array */
int macmode; /* allow/deny stations on maclist array */
struct ether_addr *maclist; /* list of source MAC addrs to match */
/* security */
u32 wsec; /* wireless security bitvec */
s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
s16 openshared; /* try Open auth first, then Shared Key */
bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
bool eap_restrict; /* restrict data until 802.1X auth succeeds */
u16 WPA_auth; /* WPA: authenticated key management */
bool wpa2_preauth; /* default is true, wpa_cap sets value */
bool wsec_portopen; /* indicates keys are plumbed */
wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */
int wsec_index; /* 0-3: default tx key, -1: not set */
wsec_key_t *bss_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
/* TKIP countermeasures */
bool tkip_countermeasures; /* flags TKIP no-assoc period */
u32 tk_cm_dt; /* detect timer */
u32 tk_cm_bt; /* blocking timer */
u32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
u8 BSSID[ETH_ALEN]; /* BSSID (associated) */
u8 cur_etheraddr[ETH_ALEN]; /* h/w address */
u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
u32 flags; /* WLC_BSSCFG flags; see below */
u8 *bcn; /* AP beacon */
uint bcn_len; /* AP beacon length */
bool ar_disassoc; /* disassociated in associated recreation */
int auth_atmptd; /* auth type (open/shared) attempted */
pmkid_cand_t pmkid_cand[MAXPMKID]; /* PMKID candidate list */
uint npmkid_cand; /* num PMKID candidates */
pmkid_t pmkid[MAXPMKID]; /* PMKID cache */
uint npmkid; /* num cached PMKIDs */
wlc_bss_info_t *current_bss; /* BSS parms in ASSOCIATED state */
/* PM states */
bool PMawakebcn; /* bcn recvd during current waking state */
bool PMpending; /* waiting for tx status with PM indicated set */
bool priorPMstate; /* Detecting PM state transitions */
bool PSpoll; /* whether there is an outstanding PS-Poll frame */
/* BSSID entry in RCMTA, use the wsec key management infrastructure to
* manage the RCMTA entries.
*/
wsec_key_t *rcmta;
/* 'unique' ID of this bsscfg, assigned at bsscfg allocation */
u16 ID;
uint txrspecidx; /* index into tx rate circular buffer */
ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */
};
#define CHANNEL_BANDUNIT(wlc, ch) (((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX)
#define OTHERBANDUNIT(wlc) ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
@ -784,7 +859,7 @@ struct antsel_info {
#define TXPKTPENDCLR(wlc, fifo) ((wlc)->core->txpktpend[(fifo)] = 0)
#define TXAVAIL(wlc, fifo) (*(wlc)->core->txavail[(fifo)])
#define GETNEXTTXP(wlc, _queue) \
dma_getnexttxp((wlc)->hw->di[(_queue)], HNDDMA_RANGE_TRANSMITTED)
dma_getnexttxp((wlc)->hw->di[(_queue)], DMA_RANGE_TRANSMITTED)
#define WLC_IS_MATCH_SSID(wlc, ssid1, ssid2, len1, len2) \
((len1 == len2) && !memcmp(ssid1, ssid2, len1))
@ -805,8 +880,6 @@ extern void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
void *buf);
extern void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
bool both);
extern void wlc_set_cwmin(struct wlc_info *wlc, u16 newmin);
extern void wlc_set_cwmax(struct wlc_info *wlc, u16 newmax);
extern void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit);
extern void wlc_reset_bmac_done(struct wlc_info *wlc);
@ -862,8 +935,8 @@ extern void wlc_inval_dma_pkts(struct wlc_hw_info *hw,
void (*dma_callback_fn));
#if defined(BCMDBG)
extern void wlc_dump_ie(struct wlc_info *wlc, bcm_tlv_t *ie,
struct bcmstrbuf *b);
extern void wlc_dump_ie(struct wlc_info *wlc, struct brcmu_tlv *ie,
struct brcmu_strbuf *b);
#endif
extern void wlc_reprate_init(struct wlc_info *wlc);
@ -900,12 +973,6 @@ extern void wlc_set_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
extern bool wlc_timers_init(struct wlc_info *wlc, int unit);
extern const bcm_iovar_t wlc_iovars[];
extern int wlc_doiovar(void *hdl, const bcm_iovar_t *vi, u32 actionid,
const char *name, void *params, uint p_len, void *arg,
int len, int val_size, struct wlc_if *wlcif);
#if defined(BCMDBG)
extern void wlc_print_ies(struct wlc_info *wlc, u8 *ies, uint ies_len);
#endif
@ -928,12 +995,9 @@ extern ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc,
wlc_rateset_t *rs);
extern void wlc_radio_disable(struct wlc_info *wlc);
extern void wlc_bcn_li_upd(struct wlc_info *wlc);
extern int wlc_get_revision_info(struct wlc_info *wlc, void *buf, uint len);
extern void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
extern void wlc_watchdog_upd(struct wlc_info *wlc, bool tbtt);
extern bool wlc_ps_allowed(struct wlc_info *wlc);
extern bool wlc_stay_awake(struct wlc_info *wlc);
extern void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe);
#endif /* _wlc_h_ */
#endif /* _BRCM_MAIN_H_ */

391
drivers/staging/brcm80211/brcmsmac/nicpci.c
View File

@ -17,17 +17,170 @@
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <defs.h>
#include "types.h"
#include <brcmu_utils.h>
#include <aiutils.h>
#include <hndsoc.h>
#include <bcmdevs.h>
#include <sbchipc.h>
#include <pci_core.h>
#include <pcie_core.h>
#include <soc.h>
#include <brcm_hw_ids.h>
#include <chipcommon.h>
#include <scb.h>
#include <pub.h>
#include <nicpci.h>
#include <pcicfg.h>
/* SPROM offsets */
#define SRSH_ASPM_OFFSET 4 /* word 4 */
#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
#define SRSH_BD_OFFSET 6 /* word 6 */
/* chipcontrol */
#define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */
/* MDIO control */
#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
#define MDIOCTL_DIVISOR_VAL 0x2
#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
/* MDIO Data */
#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
#define MDIODATA_TA 0x00020000 /* Turnaround */
#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
#define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
#define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
#define MDIODATA_WRITE 0x10000000 /* write Transaction */
#define MDIODATA_READ 0x20000000 /* Read Transaction */
#define MDIODATA_START 0x40000000 /* start of Transaction */
#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
/* serdes regs (rev < 10) */
#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
/* SERDES RX registers */
#define SERDES_RX_CTRL 1 /* Rx cntrl */
#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
#define SERDES_RX_CDR 6 /* CDR */
#define SERDES_RX_CDRBW 7 /* CDR BW */
/* SERDES RX control register */
#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
/* SERDES PLL registers */
#define SERDES_PLL_CTRL 1 /* PLL control reg */
#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
/* Linkcontrol reg offset in PCIE Cap */
#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
/* Power management threshold */
#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
#define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
/* different register spaces to access thr'u pcie indirect access */
#define PCIE_CONFIGREGS 1 /* Access to config space */
#define PCIE_PCIEREGS 2 /* Access to pcie registers */
/* PCIE protocol PHY diagnostic registers */
#define PCIE_PLP_STATUSREG 0x204 /* Status */
/* Status reg PCIE_PLP_STATUSREG */
#define PCIE_PLP_POLARITYINV_STAT 0x10
/* PCIE protocol DLLP diagnostic registers */
#define PCIE_DLLP_LCREG 0x100 /* Link Control */
#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
/* PCIE protocol TLP diagnostic registers */
#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
/* Sonics side: PCI core and host control registers */
struct sbpciregs {
u32 control; /* PCI control */
u32 PAD[3];
u32 arbcontrol; /* PCI arbiter control */
u32 clkrun; /* Clkrun Control (>=rev11) */
u32 PAD[2];
u32 intstatus; /* Interrupt status */
u32 intmask; /* Interrupt mask */
u32 sbtopcimailbox; /* Sonics to PCI mailbox */
u32 PAD[9];
u32 bcastaddr; /* Sonics broadcast address */
u32 bcastdata; /* Sonics broadcast data */
u32 PAD[2];
u32 gpioin; /* ro: gpio input (>=rev2) */
u32 gpioout; /* rw: gpio output (>=rev2) */
u32 gpioouten; /* rw: gpio output enable (>= rev2) */
u32 gpiocontrol; /* rw: gpio control (>= rev2) */
u32 PAD[36];
u32 sbtopci0; /* Sonics to PCI translation 0 */
u32 sbtopci1; /* Sonics to PCI translation 1 */
u32 sbtopci2; /* Sonics to PCI translation 2 */
u32 PAD[189];
u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
u16 sprom[36]; /* SPROM shadow Area */
u32 PAD[46];
};
/* SB side: PCIE core and host control registers */
typedef struct sbpcieregs {
u32 control; /* host mode only */
u32 PAD[2];
u32 biststatus; /* bist Status: 0x00C */
u32 gpiosel; /* PCIE gpio sel: 0x010 */
u32 gpioouten; /* PCIE gpio outen: 0x14 */
u32 PAD[2];
u32 intstatus; /* Interrupt status: 0x20 */
u32 intmask; /* Interrupt mask: 0x24 */
u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
u32 PAD[53];
u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
u32 PAD[5];
/* pcie core supports in direct access to config space */
u32 configaddr; /* pcie config space access: Address field: 0x120 */
u32 configdata; /* pcie config space access: Data field: 0x124 */
/* mdio access to serdes */
u32 mdiocontrol; /* controls the mdio access: 0x128 */
u32 mdiodata; /* Data to the mdio access: 0x12c */
/* pcie protocol phy/dllp/tlp register indirect access mechanism */
u32 pcieindaddr; /* indirect access to the internal register: 0x130 */
u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
u32 PAD[177];
u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
u16 sprom[64]; /* SPROM shadow Area */
} sbpcieregs_t;
typedef struct {
union {
@ -35,7 +188,7 @@ typedef struct {
struct sbpciregs *pciregs;
} regs; /* Memory mapped register to the core */
si_t *sih; /* System interconnect handle */
struct si_pub *sih; /* System interconnect handle */
struct pci_dev *dev;
u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
bool pcie_pr42767;
@ -69,8 +222,6 @@ static void pcie_war_noplldown(pcicore_info_t *pi);
static void pcie_war_polarity(pcicore_info_t *pi);
static void pcie_war_pci_setup(pcicore_info_t *pi);
static bool pcicore_pmecap(pcicore_info_t *pi);
#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
@ -80,7 +231,7 @@ static bool pcicore_pmecap(pcicore_info_t *pi);
/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
* only once
*/
void *pcicore_init(si_t *sih, void *pdev, void *regs)
void *pcicore_init(struct si_pub *sih, void *pdev, void *regs)
{
pcicore_info_t *pi;
@ -178,7 +329,7 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
}
/* ***** Register Access API */
uint
static uint
pcie_readreg(sbpcieregs_t *pcieregs, uint addrtype,
uint offset)
{
@ -202,7 +353,7 @@ pcie_readreg(sbpcieregs_t *pcieregs, uint addrtype,
return retval;
}
uint
static uint
pcie_writereg(sbpcieregs_t *pcieregs, uint addrtype,
uint offset, uint val)
{
@ -327,7 +478,7 @@ pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
}
/* ***** Support functions ***** */
u8 pcie_clkreq(void *pch, u32 mask, u32 val)
static u8 pcie_clkreq(void *pch, u32 mask, u32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u32 reg_val;
@ -356,7 +507,7 @@ u8 pcie_clkreq(void *pch, u32 mask, u32 val)
static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
{
u32 w;
si_t *sih = pi->sih;
struct si_pub *sih = pi->sih;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
if (!PCIE_PUB(sih) || sih->buscorerev < 7)
@ -374,7 +525,7 @@ static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
/* centralized clkreq control policy */
static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
{
si_t *sih = pi->sih;
struct si_pub *sih = pi->sih;
switch (state) {
case SI_DOATTACH:
@ -440,7 +591,7 @@ static void pcie_war_polarity(pcicore_info_t *pi)
static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
si_t *sih = pi->sih;
struct si_pub *sih = pi->sih;
u16 val16, *reg16;
u32 w;
@ -535,7 +686,7 @@ static void pcie_war_noplldown(pcicore_info_t *pi)
/* Needs to happen when coming out of 'standby'/'hibernate' */
static void pcie_war_pci_setup(pcicore_info_t *pi)
{
si_t *sih = pi->sih;
struct si_pub *sih = pi->sih;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
u32 w;
@ -577,28 +728,11 @@ static void pcie_war_pci_setup(pcicore_info_t *pi)
pcie_misc_config_fixup(pi);
}
void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
if (!PCIE_ASPM(pi->sih))
return;
/* Validate */
if (aspm > PCIE_ASPM_ENAB)
return;
pi->pcie_war_aspm_ovr = aspm;
/* Update the current state */
pcie_war_aspm_clkreq(pi);
}
/* ***** Functions called during driver state changes ***** */
void pcicore_attach(void *pch, char *pvars, int state)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
si_t *sih = pi->sih;
struct si_pub *sih = pi->sih;
/* Determine if this board needs override */
if (PCIE_ASPM(sih)) {
@ -672,165 +806,52 @@ void pcicore_down(void *pch, int state)
pcie_extendL1timer(pi, false);
}
/* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */
/* Just uses PCI config accesses to find out, when needed before sb_attach is done */
bool pcicore_pmecap_fast(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u8 cap_ptr;
u32 pmecap;
cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_PM, NULL,
NULL);
if (!cap_ptr)
return false;
pci_read_config_dword(pi->dev, cap_ptr, &pmecap);
return (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
}
/* return true if PM capability exists in the pci config space
* Uses and caches the information using core handle
/*
* precondition: current core is sii->buscoretype
*/
static bool pcicore_pmecap(pcicore_info_t *pi)
{
u8 cap_ptr;
u32 pmecap;
if (!pi->pmecap_offset) {
cap_ptr = pcicore_find_pci_capability(pi->dev,
PCI_CAP_ID_PM,
NULL, NULL);
if (!cap_ptr)
return false;
pi->pmecap_offset = cap_ptr;
pci_read_config_dword(pi->dev, pi->pmecap_offset,
&pmecap);
/* At least one state can generate PME */
pi->pmecap = (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
}
return pi->pmecap;
}
/* Enable PME generation */
void pcicore_pmeen(void *pch)
void pcicore_fixcfg(void *pch, void *regs)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u32 w;
struct si_info *sii = SI_INFO(pi->sih);
struct sbpciregs *pciregs = regs;
sbpcieregs_t *pcieregs = regs;
u16 val16, *reg16 = NULL;
uint pciidx;
/* if not pmecapable return */
if (!pcicore_pmecap(pi))
return;
pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
w |= (PCI_PM_CTRL_PME_ENABLE);
pci_write_config_dword(pi->dev,
pi->pmecap_offset + PCI_PM_CTRL, w);
/* check 'pi' is correct and fix it if not */
if (sii->pub.buscoretype == PCIE_CORE_ID) {
reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
} else if (sii->pub.buscoretype == PCI_CORE_ID) {
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
}
pciidx = ai_coreidx(&sii->pub);
val16 = R_REG(reg16);
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
val16 =
(u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
~SRSH_PI_MASK);
W_REG(reg16, val16);
}
}
/*
* Return true if PME status set
* precondition: current core is pci core
*/
bool pcicore_pmestat(void *pch)
void pcicore_pci_setup(void *pch, void *regs)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
struct sbpciregs *pciregs = regs;
u32 w;
if (!pcicore_pmecap(pi))
return false;
OR_REG(&pciregs->sbtopci2,
(SBTOPCI_PREF | SBTOPCI_BURST));
pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
return (w & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
}
/* Disable PME generation, clear the PME status bit if set
*/
void pcicore_pmeclr(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u32 w;
if (!pcicore_pmecap(pi))
return;
pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
&w);
PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
/* PMESTAT is cleared by writing 1 to it */
w &= ~(PCI_PM_CTRL_PME_ENABLE);
pci_write_config_dword(pi->dev,
pi->pmecap_offset + PCI_PM_CTRL, w);
}
u32 pcie_lcreg(void *pch, u32 mask, u32 val)
{
pcicore_info_t *pi = (pcicore_info_t *) pch;
u8 offset;
u32 tmpval;
offset = pi->pciecap_lcreg_offset;
if (!offset)
return 0;
/* set operation */
if (mask)
pci_write_config_dword(pi->dev, offset, val);
pci_read_config_dword(pi->dev, offset, &tmpval);
return tmpval;
}
u32
pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
{
u32 reg_val = 0;
pcicore_info_t *pi = (pcicore_info_t *) pch;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
if (mask) {
PCI_ERROR(("PCIEREG: 0x%x writeval 0x%x\n", offset, val));
pcie_writereg(pcieregs, type, offset, val);
if (SI_INFO(pi->sih)->pub.buscorerev >= 11) {
OR_REG(&pciregs->sbtopci2,
SBTOPCI_RC_READMULTI);
w = R_REG(&pciregs->clkrun);
W_REG(&pciregs->clkrun,
(w | PCI_CLKRUN_DSBL));
w = R_REG(&pciregs->clkrun);
}
/* Should not read register 0x154 */
if (pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11
&& type == PCIE_PCIEREGS)
return reg_val;
reg_val = pcie_readreg(pcieregs, type, offset);
PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
return reg_val;
}
u32
pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
u32 val)
{
u32 reg_val = 0;
pcicore_info_t *pi = (pcicore_info_t *) pch;
if (mask) {
PCI_ERROR(("PCIEMDIOREG: 0x%x writeval 0x%x\n", offset, val));
pcie_mdiowrite(pi, mdioslave, offset, val);
}
if (pcie_mdioread(pi, mdioslave, offset, &reg_val))
reg_val = 0xFFFFFFFF;
PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave,
offset, reg_val));
return reg_val;
}

85
drivers/staging/brcm80211/brcmsmac/nicpci.h Normal file
View File

@ -0,0 +1,85 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BRCM_NICPCI_H_
#define _BRCM_NICPCI_H_
/* PCI configuration address space size */
#define PCI_SZPCR 256
/* Brcm PCI configuration registers */
/* backplane address space accessed by BAR0 */
#define PCI_BAR0_WIN 0x80
/* sprom property control */
#define PCI_SPROM_CONTROL 0x88
/* mask of PCI and other cores interrupts */
#define PCI_INT_MASK 0x94
/* backplane core interrupt mask bits offset */
#define PCI_SBIM_SHIFT 8
/* backplane address space accessed by second 4KB of BAR0 */
#define PCI_BAR0_WIN2 0xac
/* pci config space gpio input (>=rev3) */
#define PCI_GPIO_IN 0xb0
/* pci config space gpio output (>=rev3) */
#define PCI_GPIO_OUT 0xb4
/* pci config space gpio output enable (>=rev3) */
#define PCI_GPIO_OUTEN 0xb8
/* bar0 + 4K accesses external sprom */
#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
/* bar0 + 6K accesses pci core registers */
#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
/*
* pci core SB registers are at the end of the
* 8KB window, so their address is the "regular"
* address plus 4K
*/
#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
/* bar0 window size Match with corerev 13 */
#define PCI_BAR0_WINSZ (16 * 1024)
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
/* bar0 + 8K accesses pci/pcie core registers */
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
/* bar0 + 12K accesses chipc core registers */
#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
/* Sonics to PCI translation types */
#define SBTOPCI_PREF 0x4 /* prefetch enable */
#define SBTOPCI_BURST 0x8 /* burst enable */
#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
/* PCI core index in SROM shadow area */
#define SRSH_PI_OFFSET 0 /* first word */
#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
#define SRSH_PI_SHIFT 12 /* bit 15:12 */
struct si_pub;
extern void *pcicore_init(struct si_pub *sih, void *pdev, void *regs);
extern void pcicore_deinit(void *pch);
extern void pcicore_attach(void *pch, char *pvars, int state);
extern void pcicore_hwup(void *pch);
extern void pcicore_up(void *pch, int state);
extern void pcicore_sleep(void *pch);
extern void pcicore_down(void *pch, int state);
extern u8 pcicore_find_pci_capability(void *dev, u8 req_cap_id,
unsigned char *buf, u32 *buflen);
extern void pcicore_fixcfg(void *pch, void *regs);
extern void pcicore_pci_setup(void *pch, void *regs);
#endif /* _BRCM_NICPCI_H_ */

215
drivers/staging/brcm80211/brcmsmac/nvram.c
View File

@ -1,215 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/slab.h>
#include <linux/string.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <sbchipc.h>
#include <bcmdevs.h>
#include <hndsoc.h>
#define NVR_MSG(x)
typedef struct _vars {
struct _vars *next;
int bufsz; /* allocated size */
int size; /* actual vars size */
char *vars;
} vars_t;
#define VARS_T_OH sizeof(vars_t)
static vars_t *vars;
#define NVRAM_FILE 1
static char *findvar(char *vars, char *lim, const char *name);
int nvram_init(void)
{
/* Make sure we read nvram in flash just once before freeing the memory */
if (vars != NULL) {
NVR_MSG(("nvram_init: called again without calling nvram_exit()\n"));
return 0;
}
return 0;
}
int nvram_append(char *varlst, uint varsz)
{
uint bufsz = VARS_T_OH;
vars_t *new;
new = kmalloc(bufsz, GFP_ATOMIC);
if (new == NULL)
return -ENOMEM;
new->vars = varlst;
new->bufsz = bufsz;
new->size = varsz;
new->next = vars;
vars = new;
return 0;
}
void nvram_exit(void)
{
vars_t *this, *next;
this = vars;
if (this)
kfree(this->vars);
while (this) {
next = this->next;
kfree(this);
this = next;
}
vars = NULL;
}
static char *findvar(char *vars, char *lim, const char *name)
{
char *s;
int len;
len = strlen(name);
for (s = vars; (s < lim) && *s;) {
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
return &s[len + 1];
while (*s++)
;
}
return NULL;
}
/*
* Search the name=value vars for a specific one and return its value.
* Returns NULL if not found.
*/
char *getvar(char *vars, const char *name)
{
char *s;
int len;
if (!name)
return NULL;
len = strlen(name);
if (len == 0)
return NULL;
/* first look in vars[] */
for (s = vars; s && *s;) {
if ((memcmp(s, name, len) == 0) && (s[len] == '='))
return &s[len + 1];
while (*s++)
;
}
/* then query nvram */
return nvram_get(name);
}
/*
* Search the vars for a specific one and return its value as
* an integer. Returns 0 if not found.
*/
int getintvar(char *vars, const char *name)
{
char *val;
val = getvar(vars, name);
if (val == NULL)
return 0;
return simple_strtoul(val, NULL, 0);
}
char *nvram_get(const char *name)
{
char *v = NULL;
vars_t *cur;
for (cur = vars; cur; cur = cur->next) {
v = findvar(cur->vars, cur->vars + cur->size, name);
if (v)
break;
}
return v;
}
int nvram_set(const char *name, const char *value)
{
return 0;
}
int nvram_unset(const char *name)
{
return 0;
}
int nvram_reset(void)
{
return 0;
}
int nvram_commit(void)
{
return 0;
}
int nvram_getall(char *buf, int count)
{
int len, resid = count;
vars_t *this;
this = vars;
while (this) {
char *from, *lim, *to;
int acc;
from = this->vars;
lim = (char *)(this->vars + this->size);
to = buf;
acc = 0;
while ((from < lim) && (*from)) {
len = strlen(from) + 1;
if (resid < (acc + len))
return -EOVERFLOW;
memcpy(to, from, len);
acc += len;
from += len;
to += len;
}
resid -= acc;
buf += acc;
this = this->next;
}
if (resid < 1)
return -EOVERFLOW;
*buf = '\0';
return 0;
}

460
drivers/staging/brcm80211/brcmsmac/bcmotp.c → drivers/staging/brcm80211/brcmsmac/otp.c
View File

@ -21,46 +21,58 @@
#include <linux/pci.h>
#include <linux/crc-ccitt.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcm_hw_ids.h>
#include "types.h"
#include <brcmu_utils.h>
#include <aiutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <bcmotp.h>
#include <soc.h>
#include <chipcommon.h>
#include "otp.h"
/*
* There are two different OTP controllers so far:
* 1. new IPX OTP controller: chipc 21, >=23
* 2. older HND OTP controller: chipc 12, 17, 22
*
* Define BCMHNDOTP to include support for the HND OTP controller.
* Define BCMIPXOTP to include support for the IPX OTP controller.
*
* NOTE 1: More than one may be defined
* NOTE 2: If none are defined, the default is to include them all.
*/
#define OTPS_GUP_MASK 0x00000f00
#define OTPS_GUP_SHIFT 8
#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
#if !defined(BCMHNDOTP) && !defined(BCMIPXOTP)
#define BCMHNDOTP 1
#define BCMIPXOTP 1
#endif
/* Fields in otpprog in rev >= 21 */
#define OTPP_COL_MASK 0x000000ff
#define OTPP_COL_SHIFT 0
#define OTPP_ROW_MASK 0x0000ff00
#define OTPP_ROW_SHIFT 8
#define OTPP_OC_MASK 0x0f000000
#define OTPP_OC_SHIFT 24
#define OTPP_READERR 0x10000000
#define OTPP_VALUE_MASK 0x20000000
#define OTPP_VALUE_SHIFT 29
#define OTPP_START_BUSY 0x80000000
#define OTPP_READ 0x40000000
/* Opcodes for OTPP_OC field */
#define OTPPOC_READ 0
#define OTPPOC_BIT_PROG 1
#define OTPPOC_VERIFY 3
#define OTPPOC_INIT 4
#define OTPPOC_SET 5
#define OTPPOC_RESET 6
#define OTPPOC_OCST 7
#define OTPPOC_ROW_LOCK 8
#define OTPPOC_PRESCN_TEST 9
#define OTPTYPE_HND(ccrev) ((ccrev) < 21 || (ccrev) == 22)
#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
#define OTPP_TRIES 10000000 /* # of tries for OTPP */
#ifdef BCMIPXOTP
#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
#endif
/* OTP common function type */
typedef int (*otp_status_t) (void *oh);
typedef int (*otp_size_t) (void *oh);
typedef void *(*otp_init_t) (si_t *sih);
typedef void *(*otp_init_t) (struct si_pub *sih);
typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
typedef int (*otp_read_region_t) (si_t *sih, int region, u16 *data,
typedef int (*otp_read_region_t) (struct si_pub *sih, int region, u16 *data,
uint *wlen);
typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
@ -77,9 +89,8 @@ typedef struct otp_fn_s {
typedef struct {
uint ccrev; /* chipc revision */
otp_fn_t *fn; /* OTP functions */
si_t *sih; /* Saved sb handle */
struct si_pub *sih; /* Saved sb handle */
#ifdef BCMIPXOTP
/* IPX OTP section */
u16 wsize; /* Size of otp in words */
u16 rows; /* Geometry */
@ -94,15 +105,6 @@ typedef struct {
u16 fbase; /* fuse subregion offset */
u16 flim; /* fuse subregion boundary */
int otpgu_base; /* offset to General Use Region */
#endif /* BCMIPXOTP */
#ifdef BCMHNDOTP
/* HND OTP section */
uint size; /* Size of otp in bytes */
uint hwprot; /* Hardware protection bits */
uint signvalid; /* Signature valid bits */
int boundary; /* hw/sw boundary */
#endif /* BCMHNDOTP */
} otpinfo_t;
static otpinfo_t otpinfo;
@ -120,8 +122,6 @@ static otpinfo_t otpinfo;
*
*/
#ifdef BCMIPXOTP
#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w")
/* OTP layout */
@ -214,7 +214,7 @@ static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
/* Calculate max HW/SW region byte size by subtracting fuse region and checksum size,
* osizew is oi->wsize (OTP size - GU size) in words
*/
static int ipxotp_max_rgnsz(si_t *sih, int osizew)
static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
{
int ret = 0;
@ -304,7 +304,7 @@ static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
oi->flim = oi->wsize;
}
static void *ipxotp_init(si_t *sih)
static void *ipxotp_init(struct si_pub *sih)
{
uint idx;
chipcregs_t *cc;
@ -466,374 +466,7 @@ static otp_fn_t ipxotp_fn = {
(otp_status_t) ipxotp_status
};
#endif /* BCMIPXOTP */
/*
* HND OTP Code
*
* Exported functions:
* hndotp_status()
* hndotp_size()
* hndotp_init()
* hndotp_read_bit()
* hndotp_read_region()
* hndotp_nvread()
*
*/
#ifdef BCMHNDOTP
/* Fields in otpstatus */
#define OTPS_PROGFAIL 0x80000000
#define OTPS_PROTECT 0x00000007
#define OTPS_HW_PROTECT 0x00000001
#define OTPS_SW_PROTECT 0x00000002
#define OTPS_CID_PROTECT 0x00000004
#define OTPS_RCEV_MSK 0x00003f00
#define OTPS_RCEV_SHIFT 8
/* Fields in the otpcontrol register */
#define OTPC_RECWAIT 0xff000000
#define OTPC_PROGWAIT 0x00ffff00
#define OTPC_PRW_SHIFT 8
#define OTPC_MAXFAIL 0x00000038
#define OTPC_VSEL 0x00000006
#define OTPC_SELVL 0x00000001
/* OTP regions (Word offsets from otp size) */
#define OTP_SWLIM_OFF (-4)
#define OTP_CIDBASE_OFF 0
#define OTP_CIDLIM_OFF 4
/* Predefined OTP words (Word offset from otp size) */
#define OTP_BOUNDARY_OFF (-4)
#define OTP_HWSIGN_OFF (-3)
#define OTP_SWSIGN_OFF (-2)
#define OTP_CIDSIGN_OFF (-1)
#define OTP_CID_OFF 0
#define OTP_PKG_OFF 1
#define OTP_FID_OFF 2
#define OTP_RSV_OFF 3
#define OTP_LIM_OFF 4
#define OTP_RD_OFF 4 /* Redundancy row starts here */
#define OTP_RC0_OFF 28 /* Redundancy control word 1 */
#define OTP_RC1_OFF 32 /* Redundancy control word 2 */
#define OTP_RC_LIM_OFF 36 /* Redundancy control word end */
#define OTP_HW_REGION OTPS_HW_PROTECT
#define OTP_SW_REGION OTPS_SW_PROTECT
#define OTP_CID_REGION OTPS_CID_PROTECT
#if OTP_HW_REGION != OTP_HW_RGN
#error "incompatible OTP_HW_RGN"
#endif
#if OTP_SW_REGION != OTP_SW_RGN
#error "incompatible OTP_SW_RGN"
#endif
#if OTP_CID_REGION != OTP_CI_RGN
#error "incompatible OTP_CI_RGN"
#endif
/* Redundancy entry definitions */
#define OTP_RCE_ROW_SZ 6
#define OTP_RCE_SIGN_MASK 0x7fff
#define OTP_RCE_ROW_MASK 0x3f
#define OTP_RCE_BITS 21
#define OTP_RCE_SIGN_SZ 15
#define OTP_RCE_BIT0 1
#define OTP_WPR 4
#define OTP_SIGNATURE 0x578a
#define OTP_MAGIC 0x4e56
static int hndotp_status(void *oh)
{
otpinfo_t *oi = (otpinfo_t *) oh;
return (int)(oi->hwprot | oi->signvalid);
}
static int hndotp_size(void *oh)
{
otpinfo_t *oi = (otpinfo_t *) oh;
return (int)(oi->size);
}
static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
{
volatile u16 *ptr;
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(&ptr[wn]);
}
static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
{
otpinfo_t *oi = (otpinfo_t *) oh;
volatile u16 *ptr;
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(&ptr[(oi->size / 2) + woff]);
}
static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
{
uint k, row, col;
u32 otpp, st;
row = idx / 65;
col = idx % 65;
otpp = OTPP_START_BUSY | OTPP_READ |
((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | (col & OTPP_COL_MASK);
W_REG(&cc->otpprog, otpp);
st = R_REG(&cc->otpprog);
for (k = 0;
((st & OTPP_START_BUSY) == OTPP_START_BUSY) && (k < OTPP_TRIES);
k++)
st = R_REG(&cc->otpprog);
if (k >= OTPP_TRIES) {
return 0xffff;
}
if (st & OTPP_READERR) {
return 0xffff;
}
st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
return (u16) st;
}
static void *hndotp_init(si_t *sih)
{
uint idx;
chipcregs_t *cc;
otpinfo_t *oi;
u32 cap = 0, clkdiv, otpdiv = 0;
void *ret = NULL;
oi = &otpinfo;
idx = ai_coreidx(sih);
/* Check for otp */
cc = ai_setcoreidx(sih, SI_CC_IDX);
if (cc != NULL) {
cap = R_REG(&cc->capabilities);
if ((cap & CC_CAP_OTPSIZE) == 0) {
/* Nothing there */
goto out;
}
if (!((oi->ccrev == 12) || (oi->ccrev == 17)
|| (oi->ccrev == 22)))
return NULL;
/* Read the OTP byte size. chipcommon rev >= 18 has RCE so the size is
* 8 row (64 bytes) smaller
*/
oi->size =
1 << (((cap & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT)
+ CC_CAP_OTPSIZE_BASE);
if (oi->ccrev >= 18)
oi->size -= ((OTP_RC0_OFF - OTP_BOUNDARY_OFF) * 2);
oi->hwprot = (int)(R_REG(&cc->otpstatus) & OTPS_PROTECT);
oi->boundary = -1;
/* Check the region signature */
if (hndotp_otproff(oi, cc, OTP_HWSIGN_OFF) == OTP_SIGNATURE) {
oi->signvalid |= OTP_HW_REGION;
oi->boundary = hndotp_otproff(oi, cc, OTP_BOUNDARY_OFF);
}
if (hndotp_otproff(oi, cc, OTP_SWSIGN_OFF) == OTP_SIGNATURE)
oi->signvalid |= OTP_SW_REGION;
if (hndotp_otproff(oi, cc, OTP_CIDSIGN_OFF) == OTP_SIGNATURE)
oi->signvalid |= OTP_CID_REGION;
/* Set OTP clkdiv for stability */
if (oi->ccrev == 22)
otpdiv = 12;
if (otpdiv) {
clkdiv = R_REG(&cc->clkdiv);
clkdiv =
(clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
W_REG(&cc->clkdiv, clkdiv);
}
udelay(10);
ret = (void *)oi;
}
out: /* All done */
ai_setcoreidx(sih, idx);
return ret;
}
static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
{
otpinfo_t *oi = (otpinfo_t *) oh;
u32 idx, st;
chipcregs_t *cc;
int i;
if (region != OTP_HW_REGION) {
/*
* Only support HW region
* (no active chips use HND OTP SW region)
* */
return -ENOTSUPP;
}
/* Region empty? */
st = oi->hwprot | oi->signvalid;
if ((st & region) == 0)
return -ENODATA;
*wlen =
((int)*wlen < oi->boundary / 2) ? *wlen : (uint) oi->boundary / 2;
idx = ai_coreidx(oi->sih);
cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
for (i = 0; i < (int)*wlen; i++)
data[i] = hndotp_otpr(oh, cc, i);
ai_setcoreidx(oi->sih, idx);
return 0;
}
static int hndotp_nvread(void *oh, char *data, uint *len)
{
int rc = 0;
otpinfo_t *oi = (otpinfo_t *) oh;
u32 base, bound, lim = 0, st;
int i, chunk, gchunks, tsz = 0;
u32 idx;
chipcregs_t *cc;
uint offset;
u16 *rawotp = NULL;
/* save the orig core */
idx = ai_coreidx(oi->sih);
cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
st = hndotp_status(oh);
if (!(st & (OTP_HW_REGION | OTP_SW_REGION))) {
rc = -1;
goto out;
}
/* Read the whole otp so we can easily manipulate it */
lim = hndotp_size(oh);
rawotp = kmalloc(lim, GFP_ATOMIC);
if (rawotp == NULL) {
rc = -2;
goto out;
}
for (i = 0; i < (int)(lim / 2); i++)
rawotp[i] = hndotp_otpr(oh, cc, i);
if ((st & OTP_HW_REGION) == 0) {
/* This could be a programming failure in the first
* chunk followed by one or more good chunks
*/
for (i = 0; i < (int)(lim / 2); i++)
if (rawotp[i] == OTP_MAGIC)
break;
if (i < (int)(lim / 2)) {
base = i;
bound = (i * 2) + rawotp[i + 1];
} else {
rc = -3;
goto out;
}
} else {
bound = rawotp[(lim / 2) + OTP_BOUNDARY_OFF];
/* There are two cases: 1) The whole otp is used as nvram
* and 2) There is a hardware header followed by nvram.
*/
if (rawotp[0] == OTP_MAGIC) {
base = 0;
} else
base = bound;
}
/* Find and copy the data */
chunk = 0;
gchunks = 0;
i = base / 2;
offset = 0;
while ((i < (int)(lim / 2)) && (rawotp[i] == OTP_MAGIC)) {
int dsz, rsz = rawotp[i + 1];
if (((i * 2) + rsz) >= (int)lim) {
/* Bad length, try to find another chunk anyway */
rsz = 6;
}
if (crc_ccitt(CRC16_INIT_VALUE, (u8 *) &rawotp[i], rsz) ==
CRC16_GOOD_VALUE) {
/* Good crc, copy the vars */
gchunks++;
dsz = rsz - 6;
tsz += dsz;
if (offset + dsz >= *len) {
goto out;
}
memcpy(&data[offset], &rawotp[i + 2], dsz);
offset += dsz;
/* Remove extra null characters at the end */
while (offset > 1 &&
data[offset - 1] == 0 && data[offset - 2] == 0)
offset--;
i += rsz / 2;
} else {
/* bad length or crc didn't check, try to find the next set */
if (rawotp[i + (rsz / 2)] == OTP_MAGIC) {
/* Assume length is good */
i += rsz / 2;
} else {
while (++i < (int)(lim / 2))
if (rawotp[i] == OTP_MAGIC)
break;
}
}
chunk++;
}
*len = offset;
out:
kfree(rawotp);
ai_setcoreidx(oi->sih, idx);
return rc;
}
static otp_fn_t hndotp_fn = {
(otp_size_t) hndotp_size,
(otp_read_bit_t) hndotp_read_bit,
(otp_init_t) hndotp_init,
(otp_read_region_t) hndotp_read_region,
(otp_nvread_t) hndotp_nvread,
(otp_status_t) hndotp_status
};
#endif /* BCMHNDOTP */
/*
* Common Code: Compiled for IPX / HND / AUTO
* otp_status()
* otp_size()
* otp_read_bit()
@ -866,7 +499,7 @@ u16 otp_read_bit(void *oh, uint offset)
return readBit;
}
void *otp_init(si_t *sih)
void *otp_init(struct si_pub *sih)
{
otpinfo_t *oi;
void *ret = NULL;
@ -876,15 +509,8 @@ void *otp_init(si_t *sih)
oi->ccrev = sih->ccrev;
#ifdef BCMIPXOTP
if (OTPTYPE_IPX(oi->ccrev))
oi->fn = &ipxotp_fn;
#endif
#ifdef BCMHNDOTP
if (OTPTYPE_HND(oi->ccrev))
oi->fn = &hndotp_fn;
#endif
if (oi->fn == NULL) {
return NULL;
@ -898,7 +524,7 @@ void *otp_init(si_t *sih)
}
int
otp_read_region(si_t *sih, int region, u16 *data,
otp_read_region(struct si_pub *sih, int region, u16 *data,
uint *wlen) {
bool wasup = false;
void *oh;

11
drivers/staging/brcm80211/include/bcmotp.h → drivers/staging/brcm80211/brcmsmac/otp.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmotp_h_
#define _bcmotp_h_
#ifndef _BRCM_OTP_H_
#define _BRCM_OTP_H_
/* OTP regions */
#define OTP_HW_RGN 1
@ -37,8 +37,9 @@
extern int otp_status(void *oh);
extern int otp_size(void *oh);
extern u16 otp_read_bit(void *oh, uint offset);
extern void *otp_init(si_t *sih);
extern int otp_read_region(si_t *sih, int region, u16 *data, uint *wlen);
extern void *otp_init(struct si_pub *sih);
extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
uint *wlen);
extern int otp_nvread(void *oh, char *data, uint *len);
#endif /* _bcmotp_h_ */
#endif /* _BRCM_OTP_H_ */

106
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c → drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c
View File

@ -14,8 +14,6 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <wlc_cfg.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/bitops.h>
@ -23,16 +21,16 @@
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmnvram.h>
#include <sbchipc.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
#include <defs.h>
#include <chipcommon.h>
#include <brcm_hw_ids.h>
#include <dma.h>
#include <wlc_phy_int.h>
#include <wlc_phyreg_n.h>
#include <wlc_phy_radio.h>
#include <wlc_phy_lcn.h>
#include <types.h>
#include <phy_int.h>
#include <phyreg_n.h>
#include <phy_radio.h>
#include <phy_lcn.h>
u32 phyhal_msg_level = PHYHAL_ERROR;
@ -172,7 +170,7 @@ char *phy_getvar(phy_info_t *pi, const char *name)
;
}
return nvram_get(name);
return NULL;
}
int phy_getintvar(phy_info_t *pi, const char *name)
@ -247,16 +245,10 @@ u16 read_radio_reg(phy_info_t *pi, u16 addr)
if ((D11REV_GE(pi->sh->corerev, 24)) ||
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
W_REG(&pi->regs->radioregaddr, addr);
#ifdef __mips__
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG_FLUSH(&pi->regs->radioregaddr, addr);
data = R_REG(&pi->regs->radioregdata);
} else {
W_REG(&pi->regs->phy4waddr, addr);
#ifdef __mips__
(void)R_REG(&pi->regs->phy4waddr);
#endif
W_REG_FLUSH(&pi->regs->phy4waddr, addr);
#ifdef __ARM_ARCH_4T__
__asm__(" .align 4 ");
@ -281,16 +273,10 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
W_REG(&pi->regs->radioregaddr, addr);
#ifdef __mips__
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG_FLUSH(&pi->regs->radioregaddr, addr);
W_REG(&pi->regs->radioregdata, val);
} else {
W_REG(&pi->regs->phy4waddr, addr);
#ifdef __mips__
(void)R_REG(&pi->regs->phy4waddr);
#endif
W_REG_FLUSH(&pi->regs->phy4waddr, addr);
W_REG(&pi->regs->phy4wdatalo, val);
}
@ -312,29 +298,17 @@ static u32 read_radio_id(phy_info_t *pi)
if (D11REV_GE(pi->sh->corerev, 24)) {
u32 b0, b1, b2;
W_REG(&pi->regs->radioregaddr, 0);
#ifdef __mips__
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG_FLUSH(&pi->regs->radioregaddr, 0);
b0 = (u32) R_REG(&pi->regs->radioregdata);
W_REG(&pi->regs->radioregaddr, 1);
#ifdef __mips__
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG_FLUSH(&pi->regs->radioregaddr, 1);
b1 = (u32) R_REG(&pi->regs->radioregdata);
W_REG(&pi->regs->radioregaddr, 2);
#ifdef __mips__
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG_FLUSH(&pi->regs->radioregaddr, 2);
b2 = (u32) R_REG(&pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf);
} else {
W_REG(&pi->regs->phy4waddr, RADIO_IDCODE);
#ifdef __mips__
(void)R_REG(&pi->regs->phy4waddr);
#endif
W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
id = (u32) R_REG(&pi->regs->phy4wdatalo);
id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
}
@ -397,10 +371,7 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
regs = pi->regs;
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(&regs->phyregaddr);
#endif
W_REG_FLUSH(&regs->phyregaddr, addr);
pi->phy_wreg = 0;
return R_REG(&regs->phyregdata);
@ -413,8 +384,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
regs = pi->regs;
#ifdef __mips__
W_REG(&regs->phyregaddr, addr);
(void)R_REG(&regs->phyregaddr);
W_REG_FLUSH(&regs->phyregaddr, addr);
W_REG(&regs->phyregdata, val);
if (addr == 0x72)
(void)R_REG(&regs->phyregdata);
@ -436,10 +406,7 @@ void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
regs = pi->regs;
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(&regs->phyregaddr);
#endif
W_REG_FLUSH(&regs->phyregaddr, addr);
W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) & val));
pi->phy_wreg = 0;
@ -451,10 +418,7 @@ void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
regs = pi->regs;
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(&regs->phyregaddr);
#endif
W_REG_FLUSH(&regs->phyregaddr, addr);
W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) | val));
pi->phy_wreg = 0;
@ -466,10 +430,7 @@ void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
regs = pi->regs;
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(&regs->phyregaddr);
#endif
W_REG_FLUSH(&regs->phyregaddr, addr);
W_REG(&regs->phyregdata,
((R_REG(&regs->phyregdata) & ~mask) | (val & mask)));
@ -2350,27 +2311,6 @@ bool wlc_phy_test_ison(wlc_phy_t *ppi)
return pi->phytest_on;
}
bool wlc_phy_ant_rxdiv_get(wlc_phy_t *ppi, u8 *pval)
{
phy_info_t *pi = (phy_info_t *) ppi;
bool ret = true;
wlc_phyreg_enter(ppi);
if (ISNPHY(pi)) {
ret = false;
} else if (ISLCNPHY(pi)) {
u16 crsctrl = read_phy_reg(pi, 0x410);
u16 div = crsctrl & (0x1 << 1);
*pval = (div | ((crsctrl & (0x1 << 0)) ^ (div >> 1)));
}
wlc_phyreg_exit(ppi);
return ret;
}
void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
{
phy_info_t *pi = (phy_info_t *) ppi;

51
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_hal.h → drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
View File

@ -14,14 +14,18 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_h_
#define _wlc_phy_h_
/*
* phy_hal.h: functionality exported from the phy to higher layers
*/
#ifndef _BRCM_PHY_HAL_H_
#define _BRCM_PHY_HAL_H_
#include <wlioctl.h>
#include <aiutils.h>
#include <d11.h>
#include <wlc_phy_shim.h>
#include <phy_shim.h>
#include <net/mac80211.h> /* struct wiphy */
#include "brcmu_wifi.h" /* chanspec_t */
#define IDCODE_VER_MASK 0x0000000f
#define IDCODE_VER_SHIFT 0
@ -87,12 +91,20 @@
#define WLC_TXPWR_DB_FACTOR 4
/* a large TX Power as an init value to factor out of min() calculations,
* keep low enough to fit in an s8, units are .25 dBm
*/
#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
#define WLC_NUM_RATES_CCK 4
#define WLC_NUM_RATES_OFDM 8
#define WLC_NUM_RATES_MCS_1_STREAM 8
#define WLC_NUM_RATES_MCS_2_STREAM 8
#define WLC_NUM_RATES_MCS_3_STREAM 8
#define WLC_NUM_RATES_MCS_4_STREAM 8
#define WLC_RSSI_INVALID 0 /* invalid RSSI value */
typedef struct txpwr_limits {
u8 cck[WLC_NUM_RATES_CCK];
u8 ofdm[WLC_NUM_RATES_OFDM];
@ -114,6 +126,32 @@ typedef struct txpwr_limits {
u8 mcs32;
} txpwr_limits_t;
typedef struct {
u32 flags;
chanspec_t chanspec; /* txpwr report for this channel */
chanspec_t local_chanspec; /* channel on which we are associated */
u8 local_max; /* local max according to the AP */
u8 local_constraint; /* local constraint according to the AP */
s8 antgain[2]; /* Ant gain for each band - from SROM */
u8 rf_cores; /* count of RF Cores being reported */
u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */
u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain
* without adjustment
*/
u8 est_Pout_cck; /* Latest CCK tx power out estimate */
u8 tx_power_max[4]; /* Maximum target power among all rates */
u8 tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */
u8 user_limit[WL_TX_POWER_RATES]; /* User limit */
u8 reg_limit[WL_TX_POWER_RATES]; /* Regulatory power limit */
u8 board_limit[WL_TX_POWER_RATES]; /* Max power board can support (SROM) */
u8 target[WL_TX_POWER_RATES]; /* Latest target power */
} tx_power_t;
typedef struct tx_inst_power {
u8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */
u8 txpwr_est_Pout_gofdm; /* Pwr estimate for 2.4 OFDM */
} tx_inst_power_t;
typedef struct {
u8 vec[MAXCHANNEL / NBBY];
} chanvec_t;
@ -126,7 +164,7 @@ struct phy_pub;
typedef struct phy_pub wlc_phy_t;
typedef struct shared_phy_params {
si_t *sih;
struct si_pub *sih;
void *physhim;
uint unit;
uint corerev;
@ -226,7 +264,6 @@ extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);
extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
extern bool wlc_phy_ant_rxdiv_get(wlc_phy_t *ppi, u8 *pval);
extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);
@ -253,4 +290,4 @@ extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
extern s8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
u8 mcs_offset);
extern s8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
#endif /* _wlc_phy_h_ */
#endif /* _BRCM_PHY_HAL_H_ */

31
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h → drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
View File

@ -14,15 +14,16 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_int_h_
#define _wlc_phy_int_h_
#ifndef _BRCM_PHY_INT_H_
#define _BRCM_PHY_INT_H_
#include <linux/kernel.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <bcmsrom_fmt.h>
#include <wlc_phy_hal.h>
#include <phy_hal.h>
#define PHY_VERSION { 1, 82, 8, 0 }
#define PHYHAL_ERROR 0x0001
#define PHYHAL_TRACE 0x0002
@ -42,6 +43,14 @@ extern u32 phyhal_msg_level;
#define LCNXN_BASEREV 16
typedef struct {
u8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
u8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
u8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
u8 triso; /* TR switch isolation */
u8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
} wlc_phy_srom_fem_t;
struct wlc_hw_info;
typedef struct phy_info phy_info_t;
typedef void (*initfn_t) (phy_info_t *);
@ -248,7 +257,7 @@ typedef enum {
#define PHY_CHAIN_TX_DISABLE_TEMP 115
#define PHY_HYSTERESIS_DELTATEMP 5
#define PHY_BITSCNT(x) bcm_bitcount((u8 *)&(x), sizeof(u8))
#define PHY_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
#define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
@ -527,7 +536,7 @@ typedef struct {
struct shared_phy {
struct phy_info *phy_head;
uint unit;
si_t *sih;
struct si_pub *sih;
void *physhim;
uint corerev;
u32 machwcap;
@ -653,8 +662,8 @@ struct phy_info {
s8 tx_power_offset[TXP_NUM_RATES];
u8 tx_power_target[TXP_NUM_RATES];
srom_fem_t srom_fem2g;
srom_fem_t srom_fem5g;
wlc_phy_srom_fem_t srom_fem2g;
wlc_phy_srom_fem_t srom_fem5g;
u8 tx_power_max;
u8 tx_power_max_rate_ind;
@ -1223,4 +1232,4 @@ extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
chanspec_t chanspec);
extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
#endif /* _wlc_phy_int_h_ */
#endif /* _BRCM_PHY_INT_H_ */

21
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c → drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
View File

@ -18,20 +18,21 @@
#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <wlc_cfg.h>
#include <linux/pci.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <wlc_pmu.h>
#include <bcmnvram.h>
#include <pmu.h>
#include <scb.h>
#include <pub.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
#include <brcm_hw_ids.h>
#include <dma.h>
#include "wlc_phy_radio.h"
#include "wlc_phy_int.h"
#include "wlc_phy_qmath.h"
#include "wlc_phy_lcn.h"
#include "wlc_phytbl_lcn.h"
#include "phy_radio.h"
#include "phy_int.h"
#include "phy_qmath.h"
#include "phy_lcn.h"
#include "phytbl_lcn.h"
#define PLL_2064_NDIV 90
#define PLL_2064_LOW_END_VCO 3000

6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.h → drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_lcn_h_
#define _wlc_phy_lcn_h_
#ifndef _BRCM_PHY_LCN_H_
#define _BRCM_PHY_LCN_H_
struct phy_info_lcnphy {
int lcnphy_txrf_sp_9_override;
@ -116,4 +116,4 @@ struct phy_info_lcnphy {
uint lcnphy_aci_start_time;
s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
};
#endif /* _wlc_phy_lcn_h_ */
#endif /* _BRCM_PHY_LCN_H_ */

24
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c → drivers/staging/brcm80211/brcmsmac/phy/phy_n.c
View File

@ -16,21 +16,21 @@
#include <linux/kernel.h>
#include <linux/string.h>
#include <bcmdefs.h>
#include <wlc_cfg.h>
#include <defs.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <aiutils.h>
#include <sbchipc.h>
#include <wlc_pmu.h>
#include <chipcommon.h>
#include <pmu.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
#include <brcm_hw_ids.h>
#include <dma.h>
#include <wlc_phy_radio.h>
#include <wlc_phy_int.h>
#include <wlc_phyreg_n.h>
#include <wlc_phytbl_n.h>
#include <types.h>
#include <phy_radio.h>
#include <phy_int.h>
#include <phyreg_n.h>
#include <phytbl_n.h>
#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
@ -141,6 +141,10 @@
#define NPHY_ADJUSTED_MINCRSPOWER 0x1e
/* 5357 Chip specific ChipControl register bits */
#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
typedef struct _nphy_iqcal_params {
u16 txlpf;
u16 txgm;

2
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.c → drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.c
View File

@ -16,7 +16,7 @@
#include <linux/types.h>
#include "wlc_phy_qmath.h"
#include "phy_qmath.h"
/*
Description: This function make 16 bit unsigned multiplication. To fit the output into

6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.h → drivers/staging/brcm80211/brcmsmac/phy/phy_qmath.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __QMATH_H__
#define __QMATH_H__
#ifndef _BRCM_QMATH_H_
#define _BRCM_QMATH_H_
u16 qm_mulu16(u16 op1, u16 op2);
@ -37,4 +37,4 @@ s16 qm_norm32(s32 op);
void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
#endif /* #ifndef __QMATH_H__ */
#endif /* #ifndef _BRCM_QMATH_H_ */

6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_radio.h → drivers/staging/brcm80211/brcmsmac/phy/phy_radio.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCM20XX_H
#define _BCM20XX_H
#ifndef _BRCM_PHY_RADIO_H_
#define _BRCM_PHY_RADIO_H_
#define RADIO_IDCODE 0x01
@ -1530,4 +1530,4 @@
#define RADIO_2057_VCM_MASK 0x7
#endif /* _BCM20XX_H */
#endif /* _BRCM_PHY_RADIO_H_ */

36
drivers/staging/brcm80211/brcmsmac/phy/phy_version.h
View File

@ -1,36 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef phy_version_h_
#define phy_version_h_
#define PHY_MAJOR_VERSION 1
#define PHY_MINOR_VERSION 82
#define PHY_RC_NUMBER 8
#define PHY_INCREMENTAL_NUMBER 0
#define PHY_BUILD_NUMBER 0
#define PHY_VERSION { 1, 82, 8, 0 }
#define PHY_VERSION_NUM 0x01520800
#define PHY_VERSION_STR "1.82.8.0"
#endif /* phy_version_h_ */

0
drivers/staging/brcm80211/brcmsmac/phy/wlc_phyreg_n.h → drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
View File

6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phytbl_lcn.c → drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.c
View File

@ -15,9 +15,9 @@
*/
#include <linux/types.h>
#include <sbhnddma.h>
#include <wlc_phy_int.h>
#include <wlc_phytbl_lcn.h>
#include <dma.h>
#include <phy_int.h>
#include <phytbl_lcn.h>
const u32 dot11lcn_gain_tbl_rev0[] = {
0x00000000,

0
drivers/staging/brcm80211/brcmsmac/phy/wlc_phytbl_lcn.h → drivers/staging/brcm80211/brcmsmac/phy/phytbl_lcn.h
View File

6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phytbl_n.c → drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.c
View File

@ -16,9 +16,9 @@
#include <linux/kernel.h>
#include <sbhnddma.h>
#include <wlc_phy_int.h>
#include <wlc_phytbl_n.h>
#include <dma.h>
#include <phy_int.h>
#include <phytbl_n.h>
const u32 frame_struct_rev0[] = {
0x08004a04,

0
drivers/staging/brcm80211/brcmsmac/phy/wlc_phytbl_n.h → drivers/staging/brcm80211/brcmsmac/phy/phytbl_n.h
View File

60
drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.c → drivers/staging/brcm80211/brcmsmac/phy_shim.c
View File

@ -23,37 +23,28 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <proto/802.11.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmwifi.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <aiutils.h>
#include <wlioctl.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <sbhnddma.h>
#include <hnddma.h>
#include <wlc_pmu.h>
#include <chipcommon.h>
#include "dma.h"
#include <pmu.h>
#include "wlc_types.h"
#include "wl_dbg.h"
#include "wlc_cfg.h"
#include "types.h"
#include "d11.h"
#include "wlc_rate.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_channel.h"
#include "bcmsrom.h"
#include "wlc_key.h"
#include "wlc_bmac.h"
#include "wlc_phy_hal.h"
#include "wl_export.h"
#include "wlc_main.h"
#include "wlc_phy_shim.h"
#include "rate.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "channel.h"
#include "srom.h"
#include "bmac.h"
#include "phy_hal.h"
#include "main.h"
#include "phy_shim.h"
#include "mac80211_if.h"
/* PHY SHIM module specific state */
struct wlc_phy_shim_info {
@ -89,39 +80,40 @@ struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
void (*fn) (void *arg), void *arg,
const char *name)
{
return (struct wlapi_timer *)wl_init_timer(physhim->wl, fn, arg, name);
return (struct wlapi_timer *)
brcms_init_timer(physhim->wl, fn, arg, name);
}
void wlapi_free_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
{
wl_free_timer(physhim->wl, (struct wl_timer *)t);
brcms_free_timer(physhim->wl, (struct brcms_timer *)t);
}
void
wlapi_add_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t, uint ms,
int periodic)
{
wl_add_timer(physhim->wl, (struct wl_timer *)t, ms, periodic);
brcms_add_timer(physhim->wl, (struct brcms_timer *)t, ms, periodic);
}
bool wlapi_del_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
{
return wl_del_timer(physhim->wl, (struct wl_timer *)t);
return brcms_del_timer(physhim->wl, (struct brcms_timer *)t);
}
void wlapi_intrson(wlc_phy_shim_info_t *physhim)
{
wl_intrson(physhim->wl);
brcms_intrson(physhim->wl);
}
u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim)
{
return wl_intrsoff(physhim->wl);
return brcms_intrsoff(physhim->wl);
}
void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, u32 macintmask)
{
wl_intrsrestore(physhim->wl, macintmask);
brcms_intrsrestore(physhim->wl, macintmask);
}
void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, u16 v)

61
drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.h → drivers/staging/brcm80211/brcmsmac/phy_shim.h
View File

@ -14,8 +14,12 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_shim_h_
#define _wlc_phy_shim_h_
/*
* phy_shim.h: stuff defined in phy_shim.c and included only by the phy
*/
#ifndef _BRCM_PHY_SHIM_H_
#define _BRCM_PHY_SHIM_H_
#define RADAR_TYPE_NONE 0 /* Radar type None */
#define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
@ -51,6 +55,57 @@
#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
#define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
#define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */
#define WL_ANT_IDX_1 0 /* antenna index 1 */
#define WL_ANT_IDX_2 1 /* antenna index 2 */
/* values for n_preamble_type */
#define WLC_N_PREAMBLE_MIXEDMODE 0
#define WLC_N_PREAMBLE_GF 1
#define WLC_N_PREAMBLE_GF_BRCM 2
#define WL_TX_POWER_RATES_LEGACY 45
#define WL_TX_POWER_MCS20_FIRST 12
#define WL_TX_POWER_MCS20_NUM 16
#define WL_TX_POWER_MCS40_FIRST 28
#define WL_TX_POWER_MCS40_NUM 17
#define WL_TX_POWER_RATES 101
#define WL_TX_POWER_CCK_FIRST 0
#define WL_TX_POWER_CCK_NUM 4
#define WL_TX_POWER_OFDM_FIRST 4 /* Index for first 20MHz OFDM SISO rate */
#define WL_TX_POWER_OFDM20_CDD_FIRST 12 /* Index for first 20MHz OFDM CDD rate */
#define WL_TX_POWER_OFDM40_SISO_FIRST 52 /* Index for first 40MHz OFDM SISO rate */
#define WL_TX_POWER_OFDM40_CDD_FIRST 60 /* Index for first 40MHz OFDM CDD rate */
#define WL_TX_POWER_OFDM_NUM 8
#define WL_TX_POWER_MCS20_SISO_FIRST 20 /* Index for first 20MHz MCS SISO rate */
#define WL_TX_POWER_MCS20_CDD_FIRST 28 /* Index for first 20MHz MCS CDD rate */
#define WL_TX_POWER_MCS20_STBC_FIRST 36 /* Index for first 20MHz MCS STBC rate */
#define WL_TX_POWER_MCS20_SDM_FIRST 44 /* Index for first 20MHz MCS SDM rate */
#define WL_TX_POWER_MCS40_SISO_FIRST 68 /* Index for first 40MHz MCS SISO rate */
#define WL_TX_POWER_MCS40_CDD_FIRST 76 /* Index for first 40MHz MCS CDD rate */
#define WL_TX_POWER_MCS40_STBC_FIRST 84 /* Index for first 40MHz MCS STBC rate */
#define WL_TX_POWER_MCS40_SDM_FIRST 92 /* Index for first 40MHz MCS SDM rate */
#define WL_TX_POWER_MCS_1_STREAM_NUM 8
#define WL_TX_POWER_MCS_2_STREAM_NUM 8
#define WL_TX_POWER_MCS_32 100 /* Index for 40MHz rate MCS 32 */
#define WL_TX_POWER_MCS_32_NUM 1
/* sslpnphy specifics */
#define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12 /* Index for first 20MHz MCS SISO rate */
/* tx_power_t.flags bits */
#define WL_TX_POWER_F_ENABLED 1
#define WL_TX_POWER_F_HW 2
#define WL_TX_POWER_F_MIMO 4
#define WL_TX_POWER_F_SISO 8
/* values to force tx/rx chain */
#define WLC_N_TXRX_CHAIN0 0
#define WLC_N_TXRX_CHAIN1 1
/* Forward declarations */
struct wlc_hw_info;
typedef struct wlc_phy_shim_info wlc_phy_shim_info_t;
@ -109,4 +164,4 @@ extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint,
extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim,
u32 phy_mode);
extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim);
#endif /* _wlc_phy_shim_h_ */
#endif /* _BRCM_PHY_SHIM_H_ */

552
drivers/staging/brcm80211/brcmsmac/wlc_pmu.c → drivers/staging/brcm80211/brcmsmac/pmu.c
View File

@ -18,11 +18,13 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <bcmdevs.h>
#include <sbchipc.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include "wlc_pmu.h"
#include <brcm_hw_ids.h>
#include "types.h"
#include <chipcommon.h>
#include <brcmu_utils.h>
#include "scb.h"
#include "pub.h"
#include "pmu.h"
/*
* d11 slow to fast clock transition time in slow clock cycles
@ -128,9 +130,474 @@
#define RES_DEPEND_ADD 1
#define RES_DEPEND_REMOVE -1
/* Fields in pmucontrol */
#define PCTL_ILP_DIV_MASK 0xffff0000
#define PCTL_ILP_DIV_SHIFT 16
#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
#define PCTL_HT_REQ_EN 0x00000100
#define PCTL_ALP_REQ_EN 0x00000080
#define PCTL_XTALFREQ_MASK 0x0000007c
#define PCTL_XTALFREQ_SHIFT 2
#define PCTL_ILP_DIV_EN 0x00000002
#define PCTL_LPO_SEL 0x00000001
/* Fields in clkstretch */
#define CSTRETCH_HT 0xffff0000
#define CSTRETCH_ALP 0x0000ffff
/* d11 slow to fast clock transition time in slow clock cycles */
#define D11SCC_SLOW2FAST_TRANSITION 2
/* ILP clock */
#define ILP_CLOCK 32000
/* ALP clock on pre-PMU chips */
#define ALP_CLOCK 20000000
/* HT clock */
#define HT_CLOCK 80000000
#define OTPS_READY 0x00001000
/* pmustatus */
#define PST_EXTLPOAVAIL 0x0100
#define PST_WDRESET 0x0080
#define PST_INTPEND 0x0040
#define PST_SBCLKST 0x0030
#define PST_SBCLKST_ILP 0x0010
#define PST_SBCLKST_ALP 0x0020
#define PST_SBCLKST_HT 0x0030
#define PST_ALPAVAIL 0x0008
#define PST_HTAVAIL 0x0004
#define PST_RESINIT 0x0003
/* PMU Resource Request Timer registers */
/* This is based on PmuRev0 */
#define PRRT_TIME_MASK 0x03ff
#define PRRT_INTEN 0x0400
#define PRRT_REQ_ACTIVE 0x0800
#define PRRT_ALP_REQ 0x1000
#define PRRT_HT_REQ 0x2000
/* PMU resource bit position */
#define PMURES_BIT(bit) (1 << (bit))
/* PMU resource number limit */
#define PMURES_MAX_RESNUM 30
/* PMU chip control0 register */
#define PMU_CHIPCTL0 0
/* PMU chip control1 register */
#define PMU_CHIPCTL1 1
#define PMU_CC1_RXC_DLL_BYPASS 0x00010000
#define PMU_CC1_IF_TYPE_MASK 0x00000030
#define PMU_CC1_IF_TYPE_RMII 0x00000000
#define PMU_CC1_IF_TYPE_MII 0x00000010
#define PMU_CC1_IF_TYPE_RGMII 0x00000020
#define PMU_CC1_SW_TYPE_MASK 0x000000c0
#define PMU_CC1_SW_TYPE_EPHY 0x00000000
#define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
#define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
#define PMU_CC1_SW_TYPE_RGMII 0x000000c0
/* PMU corerev and chip specific PLL controls.
* PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
* to differentiate different PLLs controlled by the same PMU rev.
*/
/* pllcontrol registers */
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
#define PMU0_PLL0_PLLCTL0 0
#define PMU0_PLL0_PC0_PDIV_MASK 1
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
/* PC0_DIV_ARM for PLLOUT_ARM */
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
#define PMU0_PLL0_PLLCTL1 1
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
#define PMU0_PLL0_PLLCTL2 2
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
/* pllcontrol registers */
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
#define PMU1_PLL0_PLLCTL0 0
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
/* m<x>div */
#define PMU1_PLL0_PLLCTL1 1
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
#define PMU1_PLL0_CHIPCTL0 0
#define PMU1_PLL0_CHIPCTL1 1
#define PMU1_PLL0_CHIPCTL2 2
#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
#define PMU1_PLL0_PLLCTL2 2
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
#define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
#define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
/* ndiv_frac */
#define PMU1_PLL0_PLLCTL3 3
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
/* pll_ctrl */
#define PMU1_PLL0_PLLCTL4 4
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
#define PMU1_PLL0_PLLCTL5 5
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
/* PMU rev 2 control words */
#define PMU2_PHY_PLL_PLLCTL 4
#define PMU2_SI_PLL_PLLCTL 10
/* PMU rev 2 */
/* pllcontrol registers */
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
#define PMU2_PLL_PLLCTL0 0
#define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
#define PMU2_PLL_PC0_P1DIV_SHIFT 20
#define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
#define PMU2_PLL_PC0_P2DIV_SHIFT 24
/* m<x>div */
#define PMU2_PLL_PLLCTL1 1
#define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
#define PMU2_PLL_PC1_M1DIV_SHIFT 0
#define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
#define PMU2_PLL_PC1_M2DIV_SHIFT 8
#define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
#define PMU2_PLL_PC1_M3DIV_SHIFT 16
#define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
#define PMU2_PLL_PC1_M4DIV_SHIFT 24
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
#define PMU2_PLL_PLLCTL2 2
#define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
#define PMU2_PLL_PC2_M5DIV_SHIFT 0
#define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
#define PMU2_PLL_PC2_M6DIV_SHIFT 8
#define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
#define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
#define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
#define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
/* ndiv_frac */
#define PMU2_PLL_PLLCTL3 3
#define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
/* pll_ctrl */
#define PMU2_PLL_PLLCTL4 4
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
#define PMU2_PLL_PLLCTL5 5
#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
/* PMU rev 5 (& 6) */
#define PMU5_PLL_P1P2_OFF 0
#define PMU5_PLL_P1_MASK 0x0f000000
#define PMU5_PLL_P1_SHIFT 24
#define PMU5_PLL_P2_MASK 0x00f00000
#define PMU5_PLL_P2_SHIFT 20
#define PMU5_PLL_M14_OFF 1
#define PMU5_PLL_MDIV_MASK 0x000000ff
#define PMU5_PLL_MDIV_WIDTH 8
#define PMU5_PLL_NM5_OFF 2
#define PMU5_PLL_NDIV_MASK 0xfff00000
#define PMU5_PLL_NDIV_SHIFT 20
#define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
#define PMU5_PLL_NDIV_MODE_SHIFT 17
#define PMU5_PLL_FMAB_OFF 3
#define PMU5_PLL_MRAT_MASK 0xf0000000
#define PMU5_PLL_MRAT_SHIFT 28
#define PMU5_PLL_ABRAT_MASK 0x08000000
#define PMU5_PLL_ABRAT_SHIFT 27
#define PMU5_PLL_FDIV_MASK 0x07ffffff
#define PMU5_PLL_PLLCTL_OFF 4
#define PMU5_PLL_PCHI_OFF 5
#define PMU5_PLL_PCHI_MASK 0x0000003f
/* pmu XtalFreqRatio */
#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
/* Divider allocation in 4716/47162/5356/5357 */
#define PMU5_MAINPLL_CPU 1
#define PMU5_MAINPLL_MEM 2
#define PMU5_MAINPLL_SI 3
#define PMU7_PLL_PLLCTL7 7
#define PMU7_PLL_PLLCTL8 8
#define PMU7_PLL_PLLCTL11 11
/* PLL usage in 4716/47162 */
#define PMU4716_MAINPLL_PLL0 12
/* PLL usage in 5356/5357 */
#define PMU5356_MAINPLL_PLL0 0
#define PMU5357_MAINPLL_PLL0 0
/* 4328 resources */
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
#define RES4328_RADIO_LDO 9 /* 0x00200 */
#define RES4328_AFE_LDO 10 /* 0x00400 */
#define RES4328_PLL_LDO 11 /* 0x00800 */
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
#define RES4328_XTAL_PU 15 /* 0x08000 */
#define RES4328_XTAL_EN 16 /* 0x10000 */
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
/* 4325 A0/A1 resources */
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
#define RES4325_OTP_PU 10 /* 0x00000400 */
#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
#define RES4325_XTAL_PU 13 /* 0x00002000 */
#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define RES4325_HT_AVAIL 21 /* 0x00200000 */
/* 4325 B0/C0 resources */
#define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
#define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
#define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
#define RES4325B0_CLDO_PU 4 /* 0x00000010 */
/* 4325 C1 resources */
#define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
#define RES4329_RESERVED0 0 /* 0x00000001 */
#define RES4329_CBUCK_LPOM 1 /* 0x00000002 */
#define RES4329_CBUCK_BURST 2 /* 0x00000004 */
#define RES4329_CBUCK_PWM 3 /* 0x00000008 */
#define RES4329_CLDO_PU 4 /* 0x00000010 */
#define RES4329_PALDO_PU 5 /* 0x00000020 */
#define RES4329_ILP_REQUEST 6 /* 0x00000040 */
#define RES4329_RESERVED7 7 /* 0x00000080 */
#define RES4329_RESERVED8 8 /* 0x00000100 */
#define RES4329_LNLDO1_PU 9 /* 0x00000200 */
#define RES4329_OTP_PU 10 /* 0x00000400 */
#define RES4329_RESERVED11 11 /* 0x00000800 */
#define RES4329_LNLDO2_PU 12 /* 0x00001000 */
#define RES4329_XTAL_PU 13 /* 0x00002000 */
#define RES4329_ALP_AVAIL 14 /* 0x00004000 */
#define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */
#define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */
#define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */
#define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */
#define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */
#define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define RES4329_HT_AVAIL 21 /* 0x00200000 */
/* 4315 resources */
#define RES4315_CBUCK_LPOM 1 /* 0x00000002 */
#define RES4315_CBUCK_BURST 2 /* 0x00000004 */
#define RES4315_CBUCK_PWM 3 /* 0x00000008 */
#define RES4315_CLDO_PU 4 /* 0x00000010 */
#define RES4315_PALDO_PU 5 /* 0x00000020 */
#define RES4315_ILP_REQUEST 6 /* 0x00000040 */
#define RES4315_LNLDO1_PU 9 /* 0x00000200 */
#define RES4315_OTP_PU 10 /* 0x00000400 */
#define RES4315_LNLDO2_PU 12 /* 0x00001000 */
#define RES4315_XTAL_PU 13 /* 0x00002000 */
#define RES4315_ALP_AVAIL 14 /* 0x00004000 */
#define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */
#define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */
#define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */
#define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */
#define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */
#define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define RES4315_HT_AVAIL 21 /* 0x00200000 */
/* 4319 resources */
#define RES4319_CBUCK_LPOM 1 /* 0x00000002 */
#define RES4319_CBUCK_BURST 2 /* 0x00000004 */
#define RES4319_CBUCK_PWM 3 /* 0x00000008 */
#define RES4319_CLDO_PU 4 /* 0x00000010 */
#define RES4319_PALDO_PU 5 /* 0x00000020 */
#define RES4319_ILP_REQUEST 6 /* 0x00000040 */
#define RES4319_LNLDO1_PU 9 /* 0x00000200 */
#define RES4319_OTP_PU 10 /* 0x00000400 */
#define RES4319_LNLDO2_PU 12 /* 0x00001000 */
#define RES4319_XTAL_PU 13 /* 0x00002000 */
#define RES4319_ALP_AVAIL 14 /* 0x00004000 */
#define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */
#define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */
#define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */
#define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */
#define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */
#define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */
#define RES4319_HT_AVAIL 21 /* 0x00200000 */
#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
#define CCTL_4319USB_XTAL_SEL_SHIFT 19
#define CCTL_4319USB_48MHZ_PLL_SEL 1
#define CCTL_4319USB_24MHZ_PLL_SEL 2
/* PMU resources for 4336 */
#define RES4336_CBUCK_LPOM 0
#define RES4336_CBUCK_BURST 1
#define RES4336_CBUCK_LP_PWM 2
#define RES4336_CBUCK_PWM 3
#define RES4336_CLDO_PU 4
#define RES4336_DIS_INT_RESET_PD 5
#define RES4336_ILP_REQUEST 6
#define RES4336_LNLDO_PU 7
#define RES4336_LDO3P3_PU 8
#define RES4336_OTP_PU 9
#define RES4336_XTAL_PU 10
#define RES4336_ALP_AVAIL 11
#define RES4336_RADIO_PU 12
#define RES4336_BG_PU 13
#define RES4336_VREG1p4_PU_PU 14
#define RES4336_AFE_PWRSW_PU 15
#define RES4336_RX_PWRSW_PU 16
#define RES4336_TX_PWRSW_PU 17
#define RES4336_BB_PWRSW_PU 18
#define RES4336_SYNTH_PWRSW_PU 19
#define RES4336_MISC_PWRSW_PU 20
#define RES4336_LOGEN_PWRSW_PU 21
#define RES4336_BBPLL_PWRSW_PU 22
#define RES4336_MACPHY_CLKAVAIL 23
#define RES4336_HT_AVAIL 24
#define RES4336_RSVD 25
/* 4330 resources */
#define RES4330_CBUCK_LPOM 0
#define RES4330_CBUCK_BURST 1
#define RES4330_CBUCK_LP_PWM 2
#define RES4330_CBUCK_PWM 3
#define RES4330_CLDO_PU 4
#define RES4330_DIS_INT_RESET_PD 5
#define RES4330_ILP_REQUEST 6
#define RES4330_LNLDO_PU 7
#define RES4330_LDO3P3_PU 8
#define RES4330_OTP_PU 9
#define RES4330_XTAL_PU 10
#define RES4330_ALP_AVAIL 11
#define RES4330_RADIO_PU 12
#define RES4330_BG_PU 13
#define RES4330_VREG1p4_PU_PU 14
#define RES4330_AFE_PWRSW_PU 15
#define RES4330_RX_PWRSW_PU 16
#define RES4330_TX_PWRSW_PU 17
#define RES4330_BB_PWRSW_PU 18
#define RES4330_SYNTH_PWRSW_PU 19
#define RES4330_MISC_PWRSW_PU 20
#define RES4330_LOGEN_PWRSW_PU 21
#define RES4330_BBPLL_PWRSW_PU 22
#define RES4330_MACPHY_CLKAVAIL 23
#define RES4330_HT_AVAIL 24
#define RES4330_5gRX_PWRSW_PU 25
#define RES4330_5gTX_PWRSW_PU 26
#define RES4330_5g_LOGEN_PWRSW_PU 27
/* 4313 resources */
#define RES4313_BB_PU_RSRC 0
#define RES4313_ILP_REQ_RSRC 1
#define RES4313_XTAL_PU_RSRC 2
#define RES4313_ALP_AVAIL_RSRC 3
#define RES4313_RADIO_PU_RSRC 4
#define RES4313_BG_PU_RSRC 5
#define RES4313_VREG1P4_PU_RSRC 6
#define RES4313_AFE_PWRSW_RSRC 7
#define RES4313_RX_PWRSW_RSRC 8
#define RES4313_TX_PWRSW_RSRC 9
#define RES4313_BB_PWRSW_RSRC 10
#define RES4313_SYNTH_PWRSW_RSRC 11
#define RES4313_MISC_PWRSW_RSRC 12
#define RES4313_BB_PLL_PWRSW_RSRC 13
#define RES4313_HT_AVAIL_RSRC 14
#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
/* PMU resource up transition time in ILP cycles */
#define PMURES_UP_TRANSITION 2
/* Setup resource up/down timers */
typedef struct {
u8 resnum;
@ -142,7 +609,8 @@ typedef struct {
u32 res_mask; /* resources (chip specific) */
s8 action; /* action */
u32 depend_mask; /* changes to the dependancies mask */
bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */
/* action is taken when filter is NULL or return true: */
bool(*filter) (struct si_pub *sih);
} pmu_res_depend_t;
/* setup pll and query clock speed */
@ -158,10 +626,10 @@ typedef struct {
/*
* prototypes used in resource tables
*/
static bool si_pmu_res_depfltr_bb(si_t *sih);
static bool si_pmu_res_depfltr_ncb(si_t *sih);
static bool si_pmu_res_depfltr_paldo(si_t *sih);
static bool si_pmu_res_depfltr_npaldo(si_t *sih);
static bool si_pmu_res_depfltr_bb(struct si_pub *sih);
static bool si_pmu_res_depfltr_ncb(struct si_pub *sih);
static bool si_pmu_res_depfltr_paldo(struct si_pub *sih);
static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih);
static const pmu_res_updown_t bcm4328a0_res_updown[] = {
{
@ -505,33 +973,33 @@ static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
};
/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
static bool si_pmu_res_depfltr_bb(si_t *sih)
static bool si_pmu_res_depfltr_bb(struct si_pub *sih)
{
return (sih->boardflags & BFL_BUCKBOOST) != 0;
}
/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
static bool si_pmu_res_depfltr_ncb(si_t *sih)
static bool si_pmu_res_depfltr_ncb(struct si_pub *sih)
{
return (sih->boardflags & BFL_NOCBUCK) != 0;
}
/* true if the power topology uses the PALDO */
static bool si_pmu_res_depfltr_paldo(si_t *sih)
static bool si_pmu_res_depfltr_paldo(struct si_pub *sih)
{
return (sih->boardflags & BFL_PALDO) != 0;
}
/* true if the power topology doesn't use the PALDO */
static bool si_pmu_res_depfltr_npaldo(si_t *sih)
static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih)
{
return (sih->boardflags & BFL_PALDO) == 0;
}
/* Return dependancies (direct or all/indirect) for the given resources */
static u32
si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs,
si_pmu_res_deps(struct si_pub *sih, chipcregs_t *cc, u32 rsrcs,
bool all)
{
u32 deps = 0;
@ -551,7 +1019,7 @@ si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs,
}
/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
{
u32 min_mask = 0, max_mask = 0;
uint rsrcs;
@ -638,7 +1106,7 @@ static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
/* Return up time in ILP cycles for the given resource. */
static uint
si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc) {
si_pmu_res_uptime(struct si_pub *sih, chipcregs_t *cc, u8 rsrc) {
u32 deps;
uint up, i, dup, dmax;
u32 min_mask = 0, max_mask = 0;
@ -671,7 +1139,7 @@ si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc) {
}
static void
si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
si_pmu_spuravoid_pllupdate(struct si_pub *sih, chipcregs_t *cc, u8 spuravoid)
{
u32 tmp = 0;
u8 phypll_offset = 0;
@ -871,7 +1339,7 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
}
/* select default xtal frequency for each chip */
static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(struct si_pub *sih)
{
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -896,7 +1364,7 @@ static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
}
/* select xtal table for each chip */
static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(struct si_pub *sih)
{
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -918,7 +1386,7 @@ static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
/* query alp/xtal clock frequency */
static u32
si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc)
si_pmu1_alpclk0(struct si_pub *sih, chipcregs_t *cc)
{
const pmu1_xtaltab0_t *xt;
u32 xf;
@ -936,7 +1404,7 @@ si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc)
}
/* select default pll fvco for each chip */
static u32 si_pmu1_pllfvco0(si_t *sih)
static u32 si_pmu1_pllfvco0(struct si_pub *sih)
{
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -956,7 +1424,7 @@ static u32 si_pmu1_pllfvco0(si_t *sih)
return 0;
}
static void si_pmu_set_4330_plldivs(si_t *sih)
static void si_pmu_set_4330_plldivs(struct si_pub *sih)
{
u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
u32 m1div, m2div, m3div, m4div, m5div, m6div;
@ -990,7 +1458,7 @@ static void si_pmu_set_4330_plldivs(si_t *sih)
* case the xtal frequency is unknown to the s/w so we need to call
* si_pmu1_xtaldef0() wherever it is needed to return a default value.
*/
static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal)
static void si_pmu1_pllinit0(struct si_pub *sih, chipcregs_t *cc, u32 xtal)
{
const pmu1_xtaltab0_t *xt;
u32 tmp;
@ -1210,7 +1678,7 @@ static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal)
W_REG(&cc->pmucontrol, tmp);
}
u32 si_pmu_ilp_clock(si_t *sih)
u32 si_pmu_ilp_clock(struct si_pub *sih)
{
static u32 ilpcycles_per_sec;
@ -1232,7 +1700,7 @@ u32 si_pmu_ilp_clock(si_t *sih)
return ilpcycles_per_sec;
}
void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage)
{
u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
u8 addr = 0;
@ -1282,7 +1750,7 @@ void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
mask << shift, (voltage & mask) << shift);
}
u16 si_pmu_fast_pwrup_delay(si_t *sih)
u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
{
uint delay = PMU_MAX_TRANSITION_DLY;
chipcregs_t *cc;
@ -1356,7 +1824,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
return (u16) delay;
}
void si_pmu_sprom_enable(si_t *sih, bool enable)
void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
{
chipcregs_t *cc;
uint origidx;
@ -1370,7 +1838,7 @@ void si_pmu_sprom_enable(si_t *sih, bool enable)
}
/* Read/write a chipcontrol reg */
u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
reg);
@ -1379,7 +1847,7 @@ u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
}
/* Read/write a regcontrol reg */
u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
reg);
@ -1388,7 +1856,7 @@ u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
}
/* Read/write a pllcontrol reg */
u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
{
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
reg);
@ -1397,14 +1865,14 @@ u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
}
/* PMU PLL update */
void si_pmu_pllupd(si_t *sih)
void si_pmu_pllupd(struct si_pub *sih)
{
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
}
/* query alp/xtal clock frequency */
u32 si_pmu_alp_clock(si_t *sih)
u32 si_pmu_alp_clock(struct si_pub *sih)
{
chipcregs_t *cc;
uint origidx;
@ -1455,7 +1923,7 @@ u32 si_pmu_alp_clock(si_t *sih)
return clock;
}
void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
{
chipcregs_t *cc;
uint origidx, intr_val;
@ -1490,7 +1958,7 @@ void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
}
/* initialize PMU */
void si_pmu_init(si_t *sih)
void si_pmu_init(struct si_pub *sih)
{
chipcregs_t *cc;
uint origidx;
@ -1518,7 +1986,7 @@ void si_pmu_init(si_t *sih)
}
/* initialize PMU chip controls and other chip level stuff */
void si_pmu_chip_init(si_t *sih)
void si_pmu_chip_init(struct si_pub *sih)
{
uint origidx;
@ -1533,7 +2001,7 @@ void si_pmu_chip_init(si_t *sih)
}
/* initialize PMU switch/regulators */
void si_pmu_swreg_init(si_t *sih)
void si_pmu_swreg_init(struct si_pub *sih)
{
switch (sih->chip) {
case BCM4336_CHIP_ID:
@ -1558,7 +2026,7 @@ void si_pmu_swreg_init(si_t *sih)
}
/* initialize PLL */
void si_pmu_pll_init(si_t *sih, uint xtalfreq)
void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
{
chipcregs_t *cc;
uint origidx;
@ -1598,7 +2066,7 @@ void si_pmu_pll_init(si_t *sih, uint xtalfreq)
}
/* initialize PMU resources */
void si_pmu_res_init(si_t *sih)
void si_pmu_res_init(struct si_pub *sih)
{
chipcregs_t *cc;
uint origidx;
@ -1769,7 +2237,7 @@ void si_pmu_res_init(si_t *sih)
ai_setcoreidx(sih, origidx);
}
u32 si_pmu_measure_alpclk(si_t *sih)
u32 si_pmu_measure_alpclk(struct si_pub *sih)
{
chipcregs_t *cc;
uint origidx;
@ -1822,7 +2290,7 @@ u32 si_pmu_measure_alpclk(si_t *sih)
return alp_khz;
}
bool si_pmu_is_otp_powered(si_t *sih)
bool si_pmu_is_otp_powered(struct si_pub *sih)
{
uint idx;
chipcregs_t *cc;
@ -1872,7 +2340,7 @@ bool si_pmu_is_otp_powered(si_t *sih)
}
/* power up/down OTP through PMU resources */
void si_pmu_otp_power(si_t *sih, bool on)
void si_pmu_otp_power(struct si_pub *sih, bool on)
{
chipcregs_t *cc;
uint origidx;

42
drivers/staging/brcm80211/brcmsmac/wlc_pmu.h → drivers/staging/brcm80211/brcmsmac/pmu.h
View File

@ -15,8 +15,8 @@
*/
#ifndef WLC_PMU_H_
#define WLC_PMU_H_
#ifndef _BRCM_PMU_H_
#define _BRCM_PMU_H_
#include <linux/types.h>
@ -36,23 +36,23 @@
#define SET_LDO_VOLTAGE_LNLDO1 9
#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
extern void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage);
extern u16 si_pmu_fast_pwrup_delay(si_t *sih);
extern void si_pmu_sprom_enable(si_t *sih, bool enable);
extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_ilp_clock(si_t *sih);
extern u32 si_pmu_alp_clock(si_t *sih);
extern void si_pmu_pllupd(si_t *sih);
extern void si_pmu_spuravoid(si_t *sih, u8 spuravoid);
extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern void si_pmu_init(si_t *sih);
extern void si_pmu_chip_init(si_t *sih);
extern void si_pmu_pll_init(si_t *sih, u32 xtalfreq);
extern void si_pmu_res_init(si_t *sih);
extern void si_pmu_swreg_init(si_t *sih);
extern u32 si_pmu_measure_alpclk(si_t *sih);
extern bool si_pmu_is_otp_powered(si_t *sih);
extern void si_pmu_otp_power(si_t *sih, bool on);
extern void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage);
extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
extern void si_pmu_sprom_enable(struct si_pub *sih, bool enable);
extern u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_ilp_clock(struct si_pub *sih);
extern u32 si_pmu_alp_clock(struct si_pub *sih);
extern void si_pmu_pllupd(struct si_pub *sih);
extern void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid);
extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
extern void si_pmu_init(struct si_pub *sih);
extern void si_pmu_chip_init(struct si_pub *sih);
extern void si_pmu_pll_init(struct si_pub *sih, u32 xtalfreq);
extern void si_pmu_res_init(struct si_pub *sih);
extern void si_pmu_swreg_init(struct si_pub *sih);
extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
extern bool si_pmu_is_otp_powered(struct si_pub *sih);
extern void si_pmu_otp_power(struct si_pub *sih, bool on);
#endif /* WLC_PMU_H_ */
#endif /* _BRCM_PMU_H_ */

160
drivers/staging/brcm80211/brcmsmac/wlc_pub.h → drivers/staging/brcm80211/brcmsmac/pub.h
View File

@ -14,8 +14,11 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_pub_h_
#define _wlc_pub_h_
#ifndef _BRCM_PUB_H_
#define _BRCM_PUB_H_
#include "types.h" /* forward structure declarations */
#include "brcmu_wifi.h" /* for chanspec_t */
#define WLC_NUMRATES 16 /* max # of rates in a rateset */
#define MAXMULTILIST 32 /* max # multicast addresses */
@ -96,6 +99,12 @@
#define AIDMAPSZ (roundup(MAXSCB, NBBY)/NBBY) /* aid bitmap size in bytes */
#endif /* AIDMAPSZ */
#define MAX_STREAMS_SUPPORTED 4 /* max number of streams supported */
#define WL_SPURAVOID_OFF 0
#define WL_SPURAVOID_ON1 1
#define WL_SPURAVOID_ON2 2
struct ieee80211_tx_queue_params;
typedef struct wlc_tunables {
@ -134,7 +143,6 @@ struct rsn_parms {
};
/*
* buffer length needed for wlc_format_ssid
* 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
*/
#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
@ -152,7 +160,7 @@ struct rsn_parms {
IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_GRN_FLD |\
IEEE80211_HT_CAP_MAX_AMSDU | IEEE80211_HT_CAP_DSSSCCK40)
/* wlc internal bss_info, wl external one is in wlioctl.h */
/* wlc internal bss_info */
typedef struct wlc_bss_info {
u8 BSSID[ETH_ALEN]; /* network BSSID */
u16 flags; /* flags for internal attributes */
@ -211,7 +219,7 @@ struct wlc_if;
/* watchdog down and dump callback function proto's */
typedef int (*watchdog_fn_t) (void *handle);
typedef int (*down_fn_t) (void *handle);
typedef int (*dump_fn_t) (void *handle, struct bcmstrbuf *b);
typedef int (*dump_fn_t) (void *handle, struct brcmu_strbuf *b);
/* IOVar handler
*
@ -226,7 +234,7 @@ typedef int (*dump_fn_t) (void *handle, struct bcmstrbuf *b);
*
* All pointers may point into the same buffer.
*/
typedef int (*iovar_fn_t) (void *handle, const bcm_iovar_t *vi,
typedef int (*iovar_fn_t) (void *handle, const struct brcmu_iovar *vi,
u32 actionid, const char *name, void *params,
uint plen, void *arg, int alen, int vsize,
struct wlc_if *wlcif);
@ -247,7 +255,7 @@ struct wlc_pub {
uint mac80211_state;
uint unit; /* device instance number */
uint corerev; /* core revision */
si_t *sih; /* SB handle (cookie for siutils calls) */
struct si_pub *sih; /* SI handle (cookie for siutils calls) */
char *vars; /* "environment" name=value */
bool up; /* interface up and running */
bool hw_off; /* HW is off */
@ -311,9 +319,6 @@ struct wlc_pub {
u32 boardflags; /* Board specific flags from srom */
u32 boardflags2; /* More board flags if sromrev >= 4 */
bool tempsense_disable; /* disable periodic tempsense check */
bool _lmac; /* lmac module included and enabled */
bool _lmacproto; /* lmac protocol module included and enabled */
bool phy_11ncapable; /* the PHY/HW is capable of 802.11N */
bool _ampdumac; /* mac assist ampdu enabled or not */
@ -335,7 +340,7 @@ typedef struct wl_rxsts {
uint preamble; /* Unknown, short, long */
uint encoding; /* Unknown, CCK, PBCC, OFDM */
uint nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
struct wl_if *wlif; /* wl interface */
struct brcms_if *wlif; /* wl interface */
} wl_rxsts_t;
/* status per error RX pkt */
@ -371,6 +376,13 @@ typedef struct wl_rxsts {
#define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
#define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
enum wlc_par_id {
IOV_MPC = 1,
IOV_RTSTHRESH,
IOV_QTXPOWER,
IOV_BCN_LI_BCN /* Beacon listen interval in # of beacons */
};
/* forward declare and use the struct notation so we don't have to
* have it defined if not necessary.
*/
@ -483,18 +495,108 @@ extern const u8 wme_fifo2ac[];
#define WLC_PROT_N_PAM_OVR 15 /* n preamble override */
#define WLC_PROT_N_OBSS 16 /* non-HT OBSS present */
/*
* 54g modes (basic bits may still be overridden)
*
* GMODE_LEGACY_B Rateset: 1b, 2b, 5.5, 11
* Preamble: Long
* Shortslot: Off
* GMODE_AUTO Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
* Extended Rateset: 6, 9, 12, 48
* Preamble: Long
* Shortslot: Auto
* GMODE_ONLY Rateset: 1b, 2b, 5.5b, 11b, 18, 24b, 36, 54
* Extended Rateset: 6b, 9, 12b, 48
* Preamble: Short required
* Shortslot: Auto
* GMODE_B_DEFERRED Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
* Extended Rateset: 6, 9, 12, 48
* Preamble: Long
* Shortslot: On
* GMODE_PERFORMANCE Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
* Preamble: Short required
* Shortslot: On and required
* GMODE_LRS Rateset: 1b, 2b, 5.5b, 11b
* Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
* Preamble: Long
* Shortslot: Auto
*/
#define GMODE_LEGACY_B 0
#define GMODE_AUTO 1
#define GMODE_ONLY 2
#define GMODE_B_DEFERRED 3
#define GMODE_PERFORMANCE 4
#define GMODE_LRS 5
#define GMODE_MAX 6
/* values for PLCPHdr_override */
#define WLC_PLCP_AUTO -1
#define WLC_PLCP_SHORT 0
#define WLC_PLCP_LONG 1
/* values for g_protection_override and n_protection_override */
#define WLC_PROTECTION_AUTO -1
#define WLC_PROTECTION_OFF 0
#define WLC_PROTECTION_ON 1
#define WLC_PROTECTION_MMHDR_ONLY 2
#define WLC_PROTECTION_CTS_ONLY 3
/* values for g_protection_control and n_protection_control */
#define WLC_PROTECTION_CTL_OFF 0
#define WLC_PROTECTION_CTL_LOCAL 1
#define WLC_PROTECTION_CTL_OVERLAP 2
/* values for n_protection */
#define WLC_N_PROTECTION_OFF 0
#define WLC_N_PROTECTION_OPTIONAL 1
#define WLC_N_PROTECTION_20IN40 2
#define WLC_N_PROTECTION_MIXEDMODE 3
/* values for band specific 40MHz capabilities */
#define WLC_N_BW_20ALL 0
#define WLC_N_BW_40ALL 1
#define WLC_N_BW_20IN2G_40IN5G 2
/* bitflags for SGI support (sgi_rx iovar) */
#define WLC_N_SGI_20 0x01
#define WLC_N_SGI_40 0x02
/* defines used by the nrate iovar */
#define NRATE_MCS_INUSE 0x00000080 /* MSC in use,indicates b0-6 holds an mcs */
#define NRATE_RATE_MASK 0x0000007f /* rate/mcs value */
#define NRATE_STF_MASK 0x0000ff00 /* stf mode mask: siso, cdd, stbc, sdm */
#define NRATE_STF_SHIFT 8 /* stf mode shift */
#define NRATE_OVERRIDE 0x80000000 /* bit indicates override both rate & mode */
#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicate to override mcs only */
#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
#define NRATE_SGI_SHIFT 23 /* sgi mode */
#define NRATE_LDPC_CODING 0x00400000 /* bit indicates adv coding in use */
#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
#define NRATE_STF_SISO 0 /* stf mode SISO */
#define NRATE_STF_CDD 1 /* stf mode CDD */
#define NRATE_STF_STBC 2 /* stf mode STBC */
#define NRATE_STF_SDM 3 /* stf mode SDM */
#define ANT_SELCFG_MAX 4 /* max number of antenna configurations */
#define HIGHEST_SINGLE_STREAM_MCS 7 /* MCS values greater than this enable multiple streams */
typedef struct {
u8 ant_config[ANT_SELCFG_MAX]; /* antenna configuration */
u8 num_antcfg; /* number of available antenna configurations */
} wlc_antselcfg_t;
/* common functions for every port */
extern void *wlc_attach(struct wl_info *wl, u16 vendor, u16 device, uint unit,
bool piomode, void *regsva, uint bustype, void *btparam,
uint *perr);
extern void *wlc_attach(struct brcms_info *wl, u16 vendor, u16 device,
uint unit, bool piomode, void *regsva, uint bustype,
void *btparam, uint *perr);
extern uint wlc_detach(struct wlc_info *wlc);
extern int wlc_up(struct wlc_info *wlc);
extern uint wlc_down(struct wlc_info *wlc);
extern int wlc_set(struct wlc_info *wlc, int cmd, int arg);
extern int wlc_get(struct wlc_info *wlc, int cmd, int *arg);
extern int wlc_iovar_getint(struct wlc_info *wlc, const char *name, int *arg);
extern int wlc_iovar_setint(struct wlc_info *wlc, const char *name, int arg);
extern bool wlc_chipmatch(u16 vendor, u16 device);
extern void wlc_init(struct wlc_info *wlc);
extern void wlc_reset(struct wlc_info *wlc);
@ -507,9 +609,6 @@ extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc);
extern bool wlc_dpc(struct wlc_info *wlc, bool bounded);
extern bool wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
struct ieee80211_hw *hw);
extern int wlc_iovar_op(struct wlc_info *wlc, const char *name, void *params,
int p_len, void *arg, int len, bool set,
struct wlc_if *wlcif);
extern int wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
struct wlc_if *wlcif);
extern bool wlc_aggregatable(struct wlc_info *wlc, u8 tid);
@ -535,18 +634,17 @@ extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs);
struct ieee80211_sta;
extern void wlc_ampdu_flush(struct wlc_info *wlc, struct ieee80211_sta *sta,
u16 tid);
extern int wlc_set_par(struct wlc_info *wlc, enum wlc_par_id par_id, int val);
extern int wlc_get_par(struct wlc_info *wlc, enum wlc_par_id par_id, int *ret_int_ptr);
extern char *getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
/* wlc_phy.c helper functions */
extern void wlc_set_ps_ctrl(struct wlc_info *wlc);
extern void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val);
/* ioctl */
extern int wlc_iovar_check(struct wlc_pub *pub, const bcm_iovar_t *vi,
void *arg,
int len, bool set);
extern int wlc_module_register(struct wlc_pub *pub, const bcm_iovar_t *iovars,
const char *name, void *hdl, iovar_fn_t iovar_fn,
extern int wlc_module_register(struct wlc_pub *pub,
const char *name, void *hdl,
watchdog_fn_t watchdog_fn, down_fn_t down_fn);
extern int wlc_module_unregister(struct wlc_pub *pub, const char *name,
void *hdl);
@ -558,18 +656,10 @@ extern void wlc_scan_stop(struct wlc_info *wlc);
extern int wlc_get_curband(struct wlc_info *wlc);
extern void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop);
#if defined(BCMDBG)
extern int wlc_iocregchk(struct wlc_info *wlc, uint band);
#endif
/* helper functions */
extern bool wlc_check_radio_disabled(struct wlc_info *wlc);
extern bool wlc_radio_monitor_stop(struct wlc_info *wlc);
#if defined(BCMDBG)
extern int wlc_format_ssid(char *buf, const unsigned char ssid[], uint ssid_len);
#endif
#define MAXBANDS 2 /* Maximum #of bands */
/* bandstate array indices */
#define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
@ -581,4 +671,4 @@ extern int wlc_format_ssid(char *buf, const unsigned char ssid[], uint ssid_len)
/* BMAC RPC: 7 u32 params: pkttotlen, fifo, commit, fid, txpktpend, pktflag, rpc_id */
#define WLC_RPCTX_PARAMS 32
#endif /* _wlc_pub_h_ */
#endif /* _BRCM_PUB_H_ */

18
drivers/staging/brcm80211/brcmsmac/wlc_rate.c → drivers/staging/brcm80211/brcmsmac/rate.c
View File

@ -16,20 +16,16 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <proto/802.11.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
#include "dma.h"
#include "wlc_types.h"
#include "types.h"
#include "d11.h"
#include "wl_dbg.h"
#include "wlc_cfg.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_rate.h"
#include "scb.h"
#include "pub.h"
#include "rate.h"
/* Rate info per rate: It tells whether a rate is ofdm or not and its phy_rate value */
const u8 rate_info[WLC_MAXRATE + 1] = {

0
drivers/staging/brcm80211/brcmsmac/wlc_rate.h → drivers/staging/brcm80211/brcmsmac/rate.h
View File

9
drivers/staging/brcm80211/brcmsmac/wlc_scb.h → drivers/staging/brcm80211/brcmsmac/scb.h
View File

@ -14,8 +14,11 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_scb_h_
#define _wlc_scb_h_
#ifndef _BRCM_SCB_H_
#define _BRCM_SCB_H_
#include <linux/if_ether.h> /* for ETH_ALEN */
#include <defs.h>
#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
/* structure to store per-tid state for the ampdu initiator */
@ -77,4 +80,4 @@ struct scb {
#define SCB_PS(a) NULL
#define SCB_STBC_CAP(a) ((a)->flags & SCB_STBCCAP)
#define SCB_AMPDU(a) true
#endif /* _wlc_scb_h_ */
#endif /* _BRCM_SCB_H_ */

977
drivers/staging/brcm80211/brcmsmac/bcmsrom_tbl.h → drivers/staging/brcm80211/brcmsmac/srom.c
View File

File diff suppressed because it is too large Load Diff

12
drivers/staging/brcm80211/include/bcmsrom.h → drivers/staging/brcm80211/brcmsmac/srom.h
View File

@ -14,16 +14,14 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_h_
#define _bcmsrom_h_
#include <bcmsrom_fmt.h>
#ifndef _BRCM_SROM_H_
#define _BRCM_SROM_H_
/* Prototypes */
extern int srom_var_init(si_t *sih, uint bus, void *curmap,
extern int srom_var_init(struct si_pub *sih, uint bus, void *curmap,
char **vars, uint *count);
extern int srom_read(si_t *sih, uint bus, void *curmap,
extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
uint byteoff, uint nbytes, u16 *buf, bool check_crc);
/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
@ -31,4 +29,4 @@ extern int srom_read(si_t *sih, uint bus, void *curmap,
*/
extern int srom_parsecis(u8 **pcis, uint ciscnt,
char **vars, uint *count);
#endif /* _bcmsrom_h_ */
#endif /* _BRCM_SROM_H_ */

67
drivers/staging/brcm80211/brcmsmac/wlc_stf.c → drivers/staging/brcm80211/brcmsmac/stf.c
View File

@ -17,30 +17,22 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <proto/802.11.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <aiutils.h>
#include <wlioctl.h>
#include <bcmwifi.h>
#include <bcmnvram.h>
#include <sbhnddma.h>
#include <brcmu_wifi.h>
#include "dma.h"
#include "wlc_types.h"
#include "types.h"
#include "d11.h"
#include "wl_dbg.h"
#include "wlc_cfg.h"
#include "wlc_rate.h"
#include "wlc_scb.h"
#include "wlc_pub.h"
#include "wlc_key.h"
#include "phy/wlc_phy_hal.h"
#include "wlc_channel.h"
#include "wlc_main.h"
#include "wl_export.h"
#include "wlc_bmac.h"
#include "wlc_stf.h"
#include "rate.h"
#include "scb.h"
#include "pub.h"
#include "phy/phy_hal.h"
#include "channel.h"
#include "main.h"
#include "bmac.h"
#include "stf.h"
#define MIN_SPATIAL_EXPANSION 0
#define MAX_SPATIAL_EXPANSION 1
@ -364,39 +356,6 @@ void wlc_stf_detach(struct wlc_info *wlc)
{
}
int wlc_stf_ant_txant_validate(struct wlc_info *wlc, s8 val)
{
int bcmerror = 0;
/* when there is only 1 tx_streams, don't allow to change the txant */
if (WLCISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
return ((val == wlc->stf->txant) ? bcmerror : -EINVAL);
switch (val) {
case -1:
val = ANT_TX_DEF;
break;
case 0:
val = ANT_TX_FORCE_0;
break;
case 1:
val = ANT_TX_FORCE_1;
break;
case 3:
val = ANT_TX_LAST_RX;
break;
default:
bcmerror = -EINVAL;
break;
}
if (bcmerror == 0)
wlc->stf->txant = (s8) val;
return bcmerror;
}
/*
* Centralized txant update function. call it whenever wlc->stf->txant and/or wlc->stf->txchain
* change

8
drivers/staging/brcm80211/brcmsmac/wlc_stf.h → drivers/staging/brcm80211/brcmsmac/stf.h
View File

@ -14,8 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_stf_h_
#define _wlc_stf_h_
#ifndef _BRCM_STF_H_
#define _BRCM_STF_H_
extern int wlc_stf_attach(struct wlc_info *wlc);
extern void wlc_stf_detach(struct wlc_info *wlc);
@ -28,11 +28,9 @@ extern int wlc_stf_ss_update(struct wlc_info *wlc, struct wlcband *band);
extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
extern int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force);
extern bool wlc_stf_stbc_rx_set(struct wlc_info *wlc, s32 int_val);
extern int wlc_stf_ant_txant_validate(struct wlc_info *wlc, s8 val);
extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
extern void wlc_stf_phy_chain_calc(struct wlc_info *wlc);
extern u16 wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec);
extern u16 wlc_stf_d11hdrs_phyctl_txant(struct wlc_info *wlc, ratespec_t rspec);
#endif /* _wlc_stf_h_ */
#endif /* _BRCM_STF_H_ */

278
drivers/staging/brcm80211/brcmsmac/wlc_cfg.h → drivers/staging/brcm80211/brcmsmac/types.h
View File

@ -14,21 +14,69 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_cfg_h_
#define _wlc_cfg_h_
#ifndef _BRCM_TYPES_H_
#define _BRCM_TYPES_H_
#define NBANDS(wlc) ((wlc)->pub->_nbands)
#define NBANDS_PUB(pub) ((pub)->_nbands)
#define NBANDS_HW(hw) ((hw)->_nbands)
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
#define IS_SINGLEBAND_5G(device) 0
#define WL_CHAN_FREQ_RANGE_2G 0
#define WL_CHAN_FREQ_RANGE_5GL 1
#define WL_CHAN_FREQ_RANGE_5GM 2
#define WL_CHAN_FREQ_RANGE_5GH 3
#define MAX_DMA_SEGS 4
/* boardflags */
#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
#define BFL_NOPA 0x00010000 /* Board has no PA */
#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
/* boardflags2 */
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
#define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
#define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
#define BFL2_LEGACY 0x00000080
#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
#define BFL2_IPALVLSHIFT_3P3 0x00020000
#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
#define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
* Most drivers will turn it off without this flag
* to save power.
*/
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
#define BOARD_GPIO_12 0x1000 /* gpio 12 */
#define BOARD_GPIO_13 0x2000 /* gpio 13 */
/* **** Core type/rev defaults **** */
#define D11_DEFAULT 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
#define D11CONF 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
* also need to update wlc.h MAXCOREREV
*/
#define NPHY_DEFAULT 0x000001ff /* Supported nphy revs:
#define NCONF 0x000001ff /* Supported nphy revs:
* 0 4321a0
* 1 4321a1
* 2 4321b0/b1/c0/c1
@ -40,35 +88,19 @@
* 8 5357a0, 43236a0
*/
#define LCNPHY_DEFAULT 0x00000007 /* Supported lcnphy revs:
#define LCNCONF 0x00000007 /* Supported lcnphy revs:
* 0 4313a0, 4336a0, 4330a0
* 1
* 2 4330a0
*/
#define SSLPNPHY_DEFAULT 0x0000000f /* Supported sslpnphy revs:
#define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
* 0 4329a0/k0
* 1 4329b0/4329C0
* 2 4319a0
* 3 5356a0
*/
/* For undefined values, use defaults */
#ifndef D11CONF
#define D11CONF D11_DEFAULT
#endif
#ifndef NCONF
#define NCONF NPHY_DEFAULT
#endif
#ifndef LCNCONF
#define LCNCONF LCNPHY_DEFAULT
#endif
#ifndef SSLPNCONF
#define SSLPNCONF SSLPNPHY_DEFAULT
#endif
/********************************************************************
* Phy/Core Configuration. Defines macros to to check core phy/rev *
* compile-time configuration. Defines default core support. *
@ -142,40 +174,11 @@
#define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
#define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
#if (D11CONF ^ (D11CONF & D11_DEFAULT))
#error "Unsupported MAC revision configured"
#endif
#if (NCONF ^ (NCONF & NPHY_DEFAULT))
#error "Unsupported NPHY revision configured"
#endif
#if (LCNCONF ^ (LCNCONF & LCNPHY_DEFAULT))
#error "Unsupported LPPHY revision configured"
#endif
/* *** Consistency checks *** */
#if !D11CONF
#error "No MAC revisions configured!"
#endif
#if !NCONF && !LCNCONF && !SSLPNCONF
#error "No PHY configured!"
#endif
/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
#define _PHYCONF_N (1 << PHY_TYPE_N)
#if LCNCONF
#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
#else
#define _PHYCONF_LCN 0
#endif /* LCNCONF */
#if SSLPNCONF
#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
#else
#define _PHYCONF_SSLPN 0
#endif /* SSLPNCONF */
#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
@ -207,28 +210,11 @@
*
* ***********************************************
*/
#ifndef NTXD
#define NTXD 256 /* Max # of entries in Tx FIFO based on 4kb page size */
#endif /* NTXD */
#ifndef NRXD
#define NRXD 256 /* Max # of entries in Rx FIFO based on 4kb page size */
#endif /* NRXD */
#ifndef NRXBUFPOST
#define NRXBUFPOST 32 /* try to keep this # rbufs posted to the chip */
#endif /* NRXBUFPOST */
#ifndef MAXSCB /* station control blocks in cache */
#define MAXSCB 32 /* Maximum SCBs in cache for STA */
#endif /* MAXSCB */
#ifndef AMPDU_NUM_MPDU
#define AMPDU_NUM_MPDU 16 /* max allowed number of mpdus in an ampdu (2 streams) */
#endif /* AMPDU_NUM_MPDU */
#ifndef AMPDU_NUM_MPDU_3STREAMS
#define AMPDU_NUM_MPDU_3STREAMS 32 /* max allowed number of mpdus in an ampdu for 3+ streams */
#endif /* AMPDU_NUM_MPDU_3STREAMS */
/* Count of packet callback structures. either of following
* 1. Set to the number of SCBs since a STA
@ -236,45 +222,145 @@
* queue up an "are you there?" Null Data callback for each associated STA
* 2. controlled by tunable config file
*/
#ifndef MAXPKTCB
#define MAXPKTCB MAXSCB /* Max number of packet callbacks */
#endif /* MAXPKTCB */
#ifndef CTFPOOLSZ
#define CTFPOOLSZ 128
#endif /* CTFPOOLSZ */
/* NetBSD also needs to keep track of this */
#define WLC_MAX_UCODE_BSS (16) /* Number of BSS handled in ucode bcn/prb */
#define WLC_MAX_UCODE_BSS4 (4) /* Number of BSS handled in sw bcn/prb */
#ifndef WLC_MAXBSSCFG
#define WLC_MAXBSSCFG (1) /* max # BSS configs */
#endif /* WLC_MAXBSSCFG */
#ifndef MAXBSS
#define MAXBSS 64 /* max # available networks */
#endif /* MAXBSS */
#ifndef WLC_DATAHIWAT
#define WLC_DATAHIWAT 50 /* data msg txq hiwat mark */
#endif /* WLC_DATAHIWAT */
#ifndef WLC_AMPDUDATAHIWAT
#define WLC_AMPDUDATAHIWAT 255
#endif /* WLC_AMPDUDATAHIWAT */
/* bounded rx loops */
#ifndef RXBND
#define RXBND 8 /* max # frames to process in wlc_recv() */
#endif /* RXBND */
#ifndef TXSBND
#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
#endif /* TXSBND */
#define WLBANDINITFN(_fn) _fn
#define BAND_5G(bt) ((bt) == WLC_BAND_5G)
#define BAND_2G(bt) ((bt) == WLC_BAND_2G)
#define WLBANDINITDATA(_data) _data
#define WLBANDINITFN(_fn) _fn
#define BCMMSG(dev, fmt, args...) \
do { \
if (brcm_msg_level & LOG_TRACE_VAL) \
wiphy_err(dev, "%s: " fmt, __func__, ##args); \
} while (0)
#endif /* _wlc_cfg_h_ */
#define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
/* register access macros */
#ifndef __BIG_ENDIAN
#ifndef __mips__
#define R_REG(r) \
({\
sizeof(*(r)) == sizeof(u8) ? \
readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile u32*)(r)); \
})
#else /* __mips__ */
#define R_REG(r) \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = readb((volatile u8*)(r)); \
break; \
case sizeof(u16): \
__osl_v = readw((volatile u16*)(r)); \
break; \
case sizeof(u32): \
__osl_v = \
readl((volatile u32*)(r)); \
break; \
} \
__asm__ __volatile__("sync"); \
__osl_v; \
})
#endif /* __mips__ */
#define W_REG(r, v) do { \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), (volatile u8*)(r)); break; \
case sizeof(u16): \
writew((u16)(v), (volatile u16*)(r)); break; \
case sizeof(u32): \
writel((u32)(v), (volatile u32*)(r)); break; \
}; \
} while (0)
#else /* __BIG_ENDIAN */
#define R_REG(r) \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(u8): \
__osl_v = \
readb((volatile u8*)((r)^3)); \
break; \
case sizeof(u16): \
__osl_v = \
readw((volatile u16*)((r)^2)); \
break; \
case sizeof(u32): \
__osl_v = readl((volatile u32*)(r)); \
break; \
} \
__osl_v; \
})
#define W_REG(r, v) do { \
switch (sizeof(*(r))) { \
case sizeof(u8): \
writeb((u8)(v), \
(volatile u8*)((r)^3)); break; \
case sizeof(u16): \
writew((u16)(v), \
(volatile u16*)((r)^2)); break; \
case sizeof(u32): \
writel((u32)(v), \
(volatile u32*)(r)); break; \
} \
} while (0)
#endif /* __BIG_ENDIAN */
#ifdef __mips__
/*
* bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
* transactions. As a fix, a read after write is performed on certain places
* in the code. Older chips and the newer 5357 family don't require this fix.
*/
#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
#else
#define W_REG_FLUSH(r, v) W_REG((r), (v))
#endif /* __mips__ */
#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
#define SET_REG(r, mask, val) \
W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
/* forward declarations */
struct sk_buff;
struct brcms_info;
struct wlc_info;
struct wlc_hw_info;
struct wlc_if;
struct brcms_if;
struct ampdu_info;
struct antsel_info;
struct bmac_pmq;
struct d11init;
struct dma_pub;
struct wlc_bsscfg;
struct brcmu_strbuf;
struct si_pub;
/* brcm_msg_level is a bit vector with defs in defs.h */
extern u32 brcm_msg_level;
#endif /* _BRCM_TYPES_H_ */

78
drivers/staging/brcm80211/brcmsmac/wl_ucode_loader.c → drivers/staging/brcm80211/brcmsmac/ucode_loader.c
View File

@ -15,8 +15,8 @@
*/
#include <linux/types.h>
#include <bcmdefs.h>
#include <wl_ucode.h>
#include <defs.h>
#include <ucode_loader.h>
enum {
D11UCODE_NAMETAG_START = 0,
@ -53,59 +53,63 @@ u32 bcm43xx_24_lcnsz;
u32 *bcm43xx_bommajor;
u32 *bcm43xx_bomminor;
int wl_ucode_data_init(struct wl_info *wl)
int brcms_ucode_data_init(struct brcms_info *wl)
{
int rc;
rc = wl_check_firmwares(wl);
rc = brcms_check_firmwares(wl);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn0bsinitvals24,
D11LCN0BSINITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn0initvals24,
rc = rc < 0 ? rc :
brcms_ucode_init_buf(wl, (void **)&d11lcn0bsinitvals24,
D11LCN0BSINITVALS24);
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&d11lcn0initvals24,
D11LCN0INITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn1bsinitvals24,
D11LCN1BSINITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn1initvals24,
rc = rc < 0 ? rc :
brcms_ucode_init_buf(wl, (void **)&d11lcn1bsinitvals24,
D11LCN1BSINITVALS24);
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&d11lcn1initvals24,
D11LCN1INITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn2bsinitvals24,
D11LCN2BSINITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11lcn2initvals24,
rc = rc < 0 ? rc :
brcms_ucode_init_buf(wl, (void **)&d11lcn2bsinitvals24,
D11LCN2BSINITVALS24);
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&d11lcn2initvals24,
D11LCN2INITVALS24);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11n0absinitvals16,
D11N0ABSINITVALS16);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11n0bsinitvals16,
rc = rc < 0 ? rc :
brcms_ucode_init_buf(wl, (void **)&d11n0absinitvals16,
D11N0ABSINITVALS16);
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&d11n0bsinitvals16,
D11N0BSINITVALS16);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&d11n0initvals16,
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&d11n0initvals16,
D11N0INITVALS16);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&bcm43xx_16_mimo,
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&bcm43xx_16_mimo,
D11UCODE_OVERSIGHT16_MIMO);
rc = rc < 0 ? rc : wl_ucode_init_uint(wl, &bcm43xx_16_mimosz,
rc = rc < 0 ? rc : brcms_ucode_init_uint(wl, &bcm43xx_16_mimosz,
D11UCODE_OVERSIGHT16_MIMOSZ);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&bcm43xx_24_lcn,
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&bcm43xx_24_lcn,
D11UCODE_OVERSIGHT24_LCN);
rc = rc < 0 ? rc : wl_ucode_init_uint(wl, &bcm43xx_24_lcnsz,
rc = rc < 0 ? rc : brcms_ucode_init_uint(wl, &bcm43xx_24_lcnsz,
D11UCODE_OVERSIGHT24_LCNSZ);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&bcm43xx_bommajor,
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&bcm43xx_bommajor,
D11UCODE_OVERSIGHT_BOMMAJOR);
rc = rc < 0 ? rc : wl_ucode_init_buf(wl, (void **)&bcm43xx_bomminor,
rc = rc < 0 ? rc : brcms_ucode_init_buf(wl, (void **)&bcm43xx_bomminor,
D11UCODE_OVERSIGHT_BOMMINOR);
return rc;
}
void wl_ucode_data_free(void)
void brcms_ucode_data_free(void)
{
wl_ucode_free_buf((void *)d11lcn0bsinitvals24);
wl_ucode_free_buf((void *)d11lcn0initvals24);
wl_ucode_free_buf((void *)d11lcn1bsinitvals24);
wl_ucode_free_buf((void *)d11lcn1initvals24);
wl_ucode_free_buf((void *)d11lcn2bsinitvals24);
wl_ucode_free_buf((void *)d11lcn2initvals24);
wl_ucode_free_buf((void *)d11n0absinitvals16);
wl_ucode_free_buf((void *)d11n0bsinitvals16);
wl_ucode_free_buf((void *)d11n0initvals16);
wl_ucode_free_buf((void *)bcm43xx_16_mimo);
wl_ucode_free_buf((void *)bcm43xx_24_lcn);
wl_ucode_free_buf((void *)bcm43xx_bommajor);
wl_ucode_free_buf((void *)bcm43xx_bomminor);
brcms_ucode_free_buf((void *)d11lcn0bsinitvals24);
brcms_ucode_free_buf((void *)d11lcn0initvals24);
brcms_ucode_free_buf((void *)d11lcn1bsinitvals24);
brcms_ucode_free_buf((void *)d11lcn1initvals24);
brcms_ucode_free_buf((void *)d11lcn2bsinitvals24);
brcms_ucode_free_buf((void *)d11lcn2initvals24);
brcms_ucode_free_buf((void *)d11n0absinitvals16);
brcms_ucode_free_buf((void *)d11n0bsinitvals16);
brcms_ucode_free_buf((void *)d11n0initvals16);
brcms_ucode_free_buf((void *)bcm43xx_16_mimo);
brcms_ucode_free_buf((void *)bcm43xx_24_lcn);
brcms_ucode_free_buf((void *)bcm43xx_bommajor);
brcms_ucode_free_buf((void *)bcm43xx_bomminor);
return;
}

15
drivers/staging/brcm80211/brcmsmac/wl_ucode.h → drivers/staging/brcm80211/brcmsmac/ucode_loader.h
View File

@ -14,6 +14,8 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "types.h" /* forward structure declarations */
#define MIN_FW_SIZE 40000 /* minimum firmware file size in bytes */
#define MAX_FW_SIZE 150000
@ -39,11 +41,12 @@ extern u32 bcm43xx_16_mimosz;
extern u32 *bcm43xx_24_lcn;
extern u32 bcm43xx_24_lcnsz;
extern int wl_ucode_data_init(struct wl_info *wl);
extern void wl_ucode_data_free(void);
extern int brcms_ucode_data_init(struct brcms_info *wl);
extern void brcms_ucode_data_free(void);
extern int wl_ucode_init_buf(struct wl_info *wl, void **pbuf, unsigned int idx);
extern int wl_ucode_init_uint(struct wl_info *wl, unsigned *data,
extern int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf,
unsigned int idx);
extern int brcms_ucode_init_uint(struct brcms_info *wl, unsigned *data,
unsigned int idx);
extern void wl_ucode_free_buf(void *);
extern int wl_check_firmwares(struct wl_info *wl);
extern void brcms_ucode_free_buf(void *);
extern int brcms_check_firmwares(struct brcms_info *wl);

92
drivers/staging/brcm80211/brcmsmac/wl_dbg.h
View File

@ -1,92 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_dbg_h_
#define _wl_dbg_h_
#include <linux/device.h> /* dev_err() */
/* wl_msg_level is a bit vector with defs in wlioctl.h */
extern u32 wl_msg_level;
#define BCMMSG(dev, fmt, args...) \
do { \
if (wl_msg_level & WL_TRACE_VAL) \
wiphy_err(dev, "%s: " fmt, __func__, ##args); \
} while (0)
#ifdef BCMDBG
/* Extra message control for AMPDU debugging */
#define WL_AMPDU_UPDN_VAL 0x00000001 /* Config up/down related */
#define WL_AMPDU_ERR_VAL 0x00000002 /* Calls to beaocn update */
#define WL_AMPDU_TX_VAL 0x00000004 /* Transmit data path */
#define WL_AMPDU_RX_VAL 0x00000008 /* Receive data path */
#define WL_AMPDU_CTL_VAL 0x00000010 /* TSF-related items */
#define WL_AMPDU_HW_VAL 0x00000020 /* AMPDU_HW */
#define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */
#define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */
extern u32 wl_ampdu_dbg;
#define WL_AMPDU_PRINT(level, fmt, args...) \
do { \
if (wl_ampdu_dbg & level) { \
WL_AMPDU(fmt, ##args); \
} \
} while (0)
#define WL_AMPDU_UPDN(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_UPDN_VAL, fmt, ##args)
#define WL_AMPDU_RX(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_RX_VAL, fmt, ##args)
#define WL_AMPDU_ERR(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_ERR_VAL, fmt, ##args)
#define WL_AMPDU_TX(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_TX_VAL, fmt, ##args)
#define WL_AMPDU_CTL(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_CTL_VAL, fmt, ##args)
#define WL_AMPDU_HW(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_HW_VAL, fmt, ##args)
#define WL_AMPDU_HWTXS(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_HWTXS_VAL, fmt, ##args)
#define WL_AMPDU_HWDBG(fmt, args...) \
WL_AMPDU_PRINT(WL_AMPDU_HWDBG_VAL, fmt, ##args)
#define WL_AMPDU_ERR_ON() (wl_ampdu_dbg & WL_AMPDU_ERR_VAL)
#define WL_AMPDU_HW_ON() (wl_ampdu_dbg & WL_AMPDU_HW_VAL)
#define WL_AMPDU_HWTXS_ON() (wl_ampdu_dbg & WL_AMPDU_HWTXS_VAL)
#else /* BCMDBG */
#define WL_AMPDU_UPDN(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_RX(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_ERR(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_TX(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_CTL(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_HW(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_HWTXS(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_HWDBG(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_ERR_ON() 0
#define WL_AMPDU_HW_ON() 0
#define WL_AMPDU_HWTXS_ON() 0
#endif /* BCMDBG */
#define WL_ERROR_ON() (wl_msg_level & WL_ERROR_VAL)
#endif /* _wl_dbg_h_ */

47
drivers/staging/brcm80211/brcmsmac/wl_export.h
View File

@ -1,47 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_export_h_
#define _wl_export_h_
/* misc callbacks */
struct wl_info;
struct wl_if;
struct wlc_if;
extern void wl_init(struct wl_info *wl);
extern uint wl_reset(struct wl_info *wl);
extern void wl_intrson(struct wl_info *wl);
extern u32 wl_intrsoff(struct wl_info *wl);
extern void wl_intrsrestore(struct wl_info *wl, u32 macintmask);
extern int wl_up(struct wl_info *wl);
extern void wl_down(struct wl_info *wl);
extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state,
int prio);
extern bool wl_alloc_dma_resources(struct wl_info *wl, uint dmaddrwidth);
extern bool wl_rfkill_set_hw_state(struct wl_info *wl);
/* timer functions */
struct wl_timer;
extern struct wl_timer *wl_init_timer(struct wl_info *wl,
void (*fn) (void *arg), void *arg,
const char *name);
extern void wl_free_timer(struct wl_info *wl, struct wl_timer *timer);
extern void wl_add_timer(struct wl_info *wl, struct wl_timer *timer, uint ms,
int periodic);
extern bool wl_del_timer(struct wl_info *wl, struct wl_timer *timer);
extern void wl_msleep(struct wl_info *wl, uint ms);
#endif /* _wl_export_h_ */

135
drivers/staging/brcm80211/brcmsmac/wlc_bsscfg.h
View File

@ -1,135 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WLC_BSSCFG_H_
#define _WLC_BSSCFG_H_
/* Check if a particular BSS config is AP or STA */
#define BSSCFG_AP(cfg) (0)
#define BSSCFG_STA(cfg) (1)
#define BSSCFG_IBSS(cfg) (!(cfg)->BSS)
#define NTXRATE 64 /* # tx MPDUs rate is reported for */
#define MAXMACLIST 64 /* max # source MAC matches */
#define BCN_TEMPLATE_COUNT 2
/* Iterator for "associated" STA bss configs:
(struct wlc_info *wlc, int idx, struct wlc_bsscfg *cfg) */
#define FOREACH_AS_STA(wlc, idx, cfg) \
for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
if ((cfg = (wlc)->bsscfg[idx]) && BSSCFG_STA(cfg) && cfg->associated)
/* As above for all non-NULL BSS configs */
#define FOREACH_BSS(wlc, idx, cfg) \
for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
if ((cfg = (wlc)->bsscfg[idx]))
/* BSS configuration state */
struct wlc_bsscfg {
struct wlc_info *wlc; /* wlc to which this bsscfg belongs to. */
bool up; /* is this configuration up operational */
bool enable; /* is this configuration enabled */
bool associated; /* is BSS in ASSOCIATED state */
bool BSS; /* infraustructure or adhac */
bool dtim_programmed;
u8 SSID_len; /* the length of SSID */
u8 SSID[IEEE80211_MAX_SSID_LEN]; /* SSID string */
struct scb *bcmc_scb[MAXBANDS]; /* one bcmc_scb per band */
s8 _idx; /* the index of this bsscfg,
* assigned at wlc_bsscfg_alloc()
*/
/* MAC filter */
uint nmac; /* # of entries on maclist array */
int macmode; /* allow/deny stations on maclist array */
struct ether_addr *maclist; /* list of source MAC addrs to match */
/* security */
u32 wsec; /* wireless security bitvec */
s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
s16 openshared; /* try Open auth first, then Shared Key */
bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
bool eap_restrict; /* restrict data until 802.1X auth succeeds */
u16 WPA_auth; /* WPA: authenticated key management */
bool wpa2_preauth; /* default is true, wpa_cap sets value */
bool wsec_portopen; /* indicates keys are plumbed */
wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */
int wsec_index; /* 0-3: default tx key, -1: not set */
wsec_key_t *bss_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
/* TKIP countermeasures */
bool tkip_countermeasures; /* flags TKIP no-assoc period */
u32 tk_cm_dt; /* detect timer */
u32 tk_cm_bt; /* blocking timer */
u32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
u8 BSSID[ETH_ALEN]; /* BSSID (associated) */
u8 cur_etheraddr[ETH_ALEN]; /* h/w address */
u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
u32 flags; /* WLC_BSSCFG flags; see below */
u8 *bcn; /* AP beacon */
uint bcn_len; /* AP beacon length */
bool ar_disassoc; /* disassociated in associated recreation */
int auth_atmptd; /* auth type (open/shared) attempted */
pmkid_cand_t pmkid_cand[MAXPMKID]; /* PMKID candidate list */
uint npmkid_cand; /* num PMKID candidates */
pmkid_t pmkid[MAXPMKID]; /* PMKID cache */
uint npmkid; /* num cached PMKIDs */
wlc_bss_info_t *current_bss; /* BSS parms in ASSOCIATED state */
/* PM states */
bool PMawakebcn; /* bcn recvd during current waking state */
bool PMpending; /* waiting for tx status with PM indicated set */
bool priorPMstate; /* Detecting PM state transitions */
bool PSpoll; /* whether there is an outstanding PS-Poll frame */
/* BSSID entry in RCMTA, use the wsec key management infrastructure to
* manage the RCMTA entries.
*/
wsec_key_t *rcmta;
/* 'unique' ID of this bsscfg, assigned at bsscfg allocation */
u16 ID;
uint txrspecidx; /* index into tx rate circular buffer */
ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */
};
#define WLC_BSSCFG_11N_DISABLE 0x1000 /* Do not advertise .11n IEs for this BSS */
#define WLC_BSSCFG_HW_BCN 0x20 /* The BSS is generating beacons in HW */
#define HWBCN_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_BCN) != 0)
#define HWPRB_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_PRB) != 0)
/* Extend N_ENAB to per-BSS */
#define BSS_N_ENAB(wlc, cfg) \
(N_ENAB((wlc)->pub) && !((cfg)->flags & WLC_BSSCFG_11N_DISABLE))
#define MBSS_BCN_ENAB(cfg) 0
#define MBSS_PRB_ENAB(cfg) 0
#define SOFTBCN_ENAB(pub) (0)
#define SOFTPRB_ENAB(pub) (0)
#define wlc_bsscfg_tx_check(a) do { } while (0);
#endif /* _WLC_BSSCFG_H_ */

140
drivers/staging/brcm80211/brcmsmac/wlc_key.h
View File

@ -1,140 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_key_h_
#define _wlc_key_h_
struct scb;
struct wlc_info;
struct wlc_bsscfg;
/* Maximum # of keys that wl driver supports in S/W.
* Keys supported in H/W is less than or equal to WSEC_MAX_KEYS.
*/
#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
#define WLC_DEFAULT_KEYS 4 /* Default # of keys */
#define WSEC_MAX_WOWL_KEYS 5 /* Max keys in WOWL mode (1 + 4 default keys) */
#define WPA2_GTK_MAX 3
/*
* Max # of keys currently supported:
*
* s/w keys if WSEC_SW(wlc->wsec).
* h/w keys otherwise.
*/
#define WLC_MAX_WSEC_KEYS(wlc) WSEC_MAX_KEYS
/* number of 802.11 default (non-paired, group keys) */
#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
/* Max # of hardware keys supported */
#define WLC_MAX_WSEC_HW_KEYS(wlc) WSEC_MAX_RCMTA_KEYS
/* Max # of hardware TKIP MIC keys supported */
#define WLC_MAX_TKMIC_HW_KEYS(wlc) (WSEC_MAX_TKMIC_ENGINE_KEYS)
#define WSEC_HW_TKMIC_KEY(wlc, key, bsscfg) \
((((wlc)->machwcap & MCAP_TKIPMIC)) && \
(key) && ((key)->algo == CRYPTO_ALGO_TKIP) && \
!WSEC_SOFTKEY(wlc, key, bsscfg) && \
WSEC_KEY_INDEX(wlc, key) >= WLC_DEFAULT_KEYS && \
(WSEC_KEY_INDEX(wlc, key) < WSEC_MAX_TKMIC_ENGINE_KEYS))
/* index of key in key table */
#define WSEC_KEY_INDEX(wlc, key) ((key)->idx)
#define WSEC_SOFTKEY(wlc, key, bsscfg) (WLC_SW_KEYS(wlc, bsscfg) || \
WSEC_KEY_INDEX(wlc, key) >= WLC_MAX_WSEC_HW_KEYS(wlc))
/* get a key, non-NULL only if key allocated and not clear */
#define WSEC_KEY(wlc, i) (((wlc)->wsec_keys[i] && (wlc)->wsec_keys[i]->len) ? \
(wlc)->wsec_keys[i] : NULL)
#define WSEC_SCB_KEY_VALID(scb) (((scb)->key && (scb)->key->len) ? true : false)
/* default key */
#define WSEC_BSS_DEFAULT_KEY(bsscfg) (((bsscfg)->wsec_index == -1) ? \
(struct wsec_key *)NULL:(bsscfg)->bss_def_keys[(bsscfg)->wsec_index])
/* Macros for key management in IBSS mode */
#define WSEC_IBSS_MAX_PEERS 16 /* Max # of IBSS Peers */
#define WSEC_IBSS_RCMTA_INDEX(idx) \
(((idx - WSEC_MAX_DEFAULT_KEYS) % WSEC_IBSS_MAX_PEERS) + WSEC_MAX_DEFAULT_KEYS)
/* contiguous # key slots for infrastructure mode STA */
#define WSEC_BSS_STA_KEY_GROUP_SIZE 5
typedef struct wsec_iv {
u32 hi; /* upper 32 bits of IV */
u16 lo; /* lower 16 bits of IV */
} wsec_iv_t;
#define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */
typedef struct wsec_key {
u8 ea[ETH_ALEN]; /* per station */
u8 idx; /* key index in wsec_keys array */
u8 id; /* key ID [0-3] */
u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
u8 rcmta; /* rcmta entry index, same as idx by default */
u16 flags; /* misc flags */
u8 algo_hw; /* cache for hw register */
u8 aes_mode; /* cache for hw register */
s8 iv_len; /* IV length */
s8 icv_len; /* ICV length */
u32 len; /* key length..don't move this var */
/* data is 4byte aligned */
u8 data[WLAN_MAX_KEY_LEN]; /* key data */
wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */
wsec_iv_t txiv; /* Tx IV */
} wsec_key_t;
#define broken_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
/* For use with wsec_key_t.flags */
#define WSEC_BS_UPDATE (1 << 0) /* Indicates hw needs key update on BS switch */
#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
#define WSEC_IBSS_PEER_GROUP_KEY (1 << 7) /* Flag: group key for a IBSS PEER */
#define WSEC_ICV_ERROR (1 << 8) /* Provoke deliberate ICV error */
#define wlc_key_insert(a, b, c, d, e, f, g, h, i, j) (-EBADE)
#define wlc_key_update(a, b, c) do {} while (0)
#define wlc_key_remove(a, b, c) do {} while (0)
#define wlc_key_remove_all(a, b) do {} while (0)
#define wlc_key_delete(a, b, c) do {} while (0)
#define wlc_scb_key_delete(a, b) do {} while (0)
#define wlc_key_lookup(a, b, c, d, e) (NULL)
#define wlc_key_hw_init_all(a) do {} while (0)
#define wlc_key_hw_init(a, b, c) do {} while (0)
#define wlc_key_hw_wowl_init(a, b, c, d) do {} while (0)
#define wlc_key_sw_wowl_update(a, b, c, d, e) do {} while (0)
#define wlc_key_sw_wowl_create(a, b, c) (-EBADE)
#define wlc_key_iv_update(a, b, c, d, e) do {(void)e; } while (0)
#define wlc_key_iv_init(a, b, c) do {} while (0)
#define wlc_key_set_error(a, b, c) (-EBADE)
#define wlc_key_dump_hw(a, b) (-EBADE)
#define wlc_key_dump_sw(a, b) (-EBADE)
#define wlc_key_defkeyflag(a) (0)
#define wlc_rcmta_add_bssid(a, b) do {} while (0)
#define wlc_rcmta_del_bssid(a, b) do {} while (0)
#define wlc_key_scb_delete(a, b) do {} while (0)
#endif /* _wlc_key_h_ */

37
drivers/staging/brcm80211/brcmsmac/wlc_types.h
View File

@ -1,37 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_types_h_
#define _wlc_types_h_
/* forward declarations */
struct wlc_info;
struct wlc_hw_info;
struct wlc_if;
struct wl_if;
struct ampdu_info;
struct antsel_info;
struct bmac_pmq;
struct d11init;
#ifndef _hnddma_pub_
#define _hnddma_pub_
struct hnddma_pub;
#endif /* _hnddma_pub_ */
#endif /* _wlc_types_h_ */

6
drivers/staging/brcm80211/util/Makefile → drivers/staging/brcm80211/brcmutil/Makefile
View File

@ -16,12 +16,12 @@
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
ccflags-y := \
-Idrivers/staging/brcm80211/util \
-Idrivers/staging/brcm80211/brcmutil \
-Idrivers/staging/brcm80211/include
BRCMUTIL_OFILES := \
bcmutils.o \
bcmwifi.o
utils.o \
wifi.o
MODULEPFX := brcmutil

143
drivers/staging/brcm80211/util/bcmutils.c → drivers/staging/brcm80211/brcmutil/utils.c
View File

@ -22,19 +22,17 @@
#include <linux/netdevice.h>
#include <linux/sched.h>
#include <linux/printk.h>
#include <bcmdefs.h>
#include <defs.h>
#include <stdarg.h>
#include <bcmutils.h>
#include <bcmnvram.h>
#include <bcmdevs.h>
#include <proto/802.11.h>
#include <brcmu_utils.h>
#include <brcm_hw_ids.h>
MODULE_AUTHOR("Broadcom Corporation");
MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver utilities.");
MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");
struct sk_buff *bcm_pkt_buf_get_skb(uint len)
struct sk_buff *brcmu_pkt_buf_get_skb(uint len)
{
struct sk_buff *skb;
@ -46,10 +44,10 @@ struct sk_buff *bcm_pkt_buf_get_skb(uint len)
return skb;
}
EXPORT_SYMBOL(bcm_pkt_buf_get_skb);
EXPORT_SYMBOL(brcmu_pkt_buf_get_skb);
/* Free the driver packet. Free the tag if present */
void bcm_pkt_buf_free_skb(struct sk_buff *skb)
void brcmu_pkt_buf_free_skb(struct sk_buff *skb)
{
struct sk_buff *nskb;
int nest = 0;
@ -74,11 +72,11 @@ void bcm_pkt_buf_free_skb(struct sk_buff *skb)
skb = nskb;
}
}
EXPORT_SYMBOL(bcm_pkt_buf_free_skb);
EXPORT_SYMBOL(brcmu_pkt_buf_free_skb);
/* copy a buffer into a pkt buffer chain */
uint bcm_pktfrombuf(struct sk_buff *p, uint offset, int len,
uint brcmu_pktfrombuf(struct sk_buff *p, uint offset, int len,
unsigned char *buf)
{
uint n, ret = 0;
@ -105,10 +103,10 @@ uint bcm_pktfrombuf(struct sk_buff *p, uint offset, int len,
return ret;
}
EXPORT_SYMBOL(bcm_pktfrombuf);
EXPORT_SYMBOL(brcmu_pktfrombuf);
/* return total length of buffer chain */
uint bcm_pkttotlen(struct sk_buff *p)
uint brcmu_pkttotlen(struct sk_buff *p)
{
uint total;
@ -117,13 +115,13 @@ uint bcm_pkttotlen(struct sk_buff *p)
total += p->len;
return total;
}
EXPORT_SYMBOL(bcm_pkttotlen);
EXPORT_SYMBOL(brcmu_pkttotlen);
/*
* osl multiple-precedence packet queue
* hi_prec is always >= the number of the highest non-empty precedence
*/
struct sk_buff *bcm_pktq_penq(struct pktq *pq, int prec,
struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
struct sk_buff *p)
{
struct pktq_prec *q;
@ -148,9 +146,9 @@ struct sk_buff *bcm_pktq_penq(struct pktq *pq, int prec,
return p;
}
EXPORT_SYMBOL(bcm_pktq_penq);
EXPORT_SYMBOL(brcmu_pktq_penq);
struct sk_buff *bcm_pktq_penq_head(struct pktq *pq, int prec,
struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
struct sk_buff *p)
{
struct pktq_prec *q;
@ -174,9 +172,9 @@ struct sk_buff *bcm_pktq_penq_head(struct pktq *pq, int prec,
return p;
}
EXPORT_SYMBOL(bcm_pktq_penq_head);
EXPORT_SYMBOL(brcmu_pktq_penq_head);
struct sk_buff *bcm_pktq_pdeq(struct pktq *pq, int prec)
struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec)
{
struct pktq_prec *q;
struct sk_buff *p;
@ -199,9 +197,9 @@ struct sk_buff *bcm_pktq_pdeq(struct pktq *pq, int prec)
return p;
}
EXPORT_SYMBOL(bcm_pktq_pdeq);
EXPORT_SYMBOL(brcmu_pktq_pdeq);
struct sk_buff *bcm_pktq_pdeq_tail(struct pktq *pq, int prec)
struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec)
{
struct pktq_prec *q;
struct sk_buff *p, *prev;
@ -227,10 +225,10 @@ struct sk_buff *bcm_pktq_pdeq_tail(struct pktq *pq, int prec)
return p;
}
EXPORT_SYMBOL(bcm_pktq_pdeq_tail);
EXPORT_SYMBOL(brcmu_pktq_pdeq_tail);
void
bcm_pktq_pflush(struct pktq *pq, int prec, bool dir,
brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir,
ifpkt_cb_t fn, void *arg)
{
struct pktq_prec *q;
@ -246,7 +244,7 @@ bcm_pktq_pflush(struct pktq *pq, int prec, bool dir,
else
prev->prev = p->prev;
p->prev = NULL;
bcm_pkt_buf_free_skb(p);
brcmu_pkt_buf_free_skb(p);
q->len--;
pq->len--;
p = (head ? q->head : prev->prev);
@ -260,18 +258,18 @@ bcm_pktq_pflush(struct pktq *pq, int prec, bool dir,
q->tail = NULL;
}
}
EXPORT_SYMBOL(bcm_pktq_pflush);
EXPORT_SYMBOL(brcmu_pktq_pflush);
void bcm_pktq_flush(struct pktq *pq, bool dir,
void brcmu_pktq_flush(struct pktq *pq, bool dir,
ifpkt_cb_t fn, void *arg)
{
int prec;
for (prec = 0; prec < pq->num_prec; prec++)
bcm_pktq_pflush(pq, prec, dir, fn, arg);
brcmu_pktq_pflush(pq, prec, dir, fn, arg);
}
EXPORT_SYMBOL(bcm_pktq_flush);
EXPORT_SYMBOL(brcmu_pktq_flush);
void bcm_pktq_init(struct pktq *pq, int num_prec, int max_len)
void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len)
{
int prec;
@ -286,9 +284,9 @@ void bcm_pktq_init(struct pktq *pq, int num_prec, int max_len)
for (prec = 0; prec < num_prec; prec++)
pq->q[prec].max = pq->max;
}
EXPORT_SYMBOL(bcm_pktq_init);
EXPORT_SYMBOL(brcmu_pktq_init);
struct sk_buff *bcm_pktq_peek_tail(struct pktq *pq, int *prec_out)
struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out)
{
int prec;
@ -304,10 +302,10 @@ struct sk_buff *bcm_pktq_peek_tail(struct pktq *pq, int *prec_out)
return pq->q[prec].tail;
}
EXPORT_SYMBOL(bcm_pktq_peek_tail);
EXPORT_SYMBOL(brcmu_pktq_peek_tail);
/* Return sum of lengths of a specific set of precedences */
int bcm_pktq_mlen(struct pktq *pq, uint prec_bmp)
int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp)
{
int prec, len;
@ -319,10 +317,10 @@ int bcm_pktq_mlen(struct pktq *pq, uint prec_bmp)
return len;
}
EXPORT_SYMBOL(bcm_pktq_mlen);
EXPORT_SYMBOL(brcmu_pktq_mlen);
/* Priority dequeue from a specific set of precedences */
struct sk_buff *bcm_pktq_mdeq(struct pktq *pq, uint prec_bmp,
struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
int *prec_out)
{
struct pktq_prec *q;
@ -360,10 +358,10 @@ struct sk_buff *bcm_pktq_mdeq(struct pktq *pq, uint prec_bmp,
return p;
}
EXPORT_SYMBOL(bcm_pktq_mdeq);
EXPORT_SYMBOL(brcmu_pktq_mdeq);
/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
int bcm_ether_atoe(char *p, u8 *ea)
int brcmu_ether_atoe(char *p, u8 *ea)
{
int i = 0;
@ -375,11 +373,11 @@ int bcm_ether_atoe(char *p, u8 *ea)
return i == 6;
}
EXPORT_SYMBOL(bcm_ether_atoe);
EXPORT_SYMBOL(brcmu_ether_atoe);
#if defined(BCMDBG)
/* pretty hex print a pkt buffer chain */
void bcm_prpkt(const char *msg, struct sk_buff *p0)
void brcmu_prpkt(const char *msg, struct sk_buff *p0)
{
struct sk_buff *p;
@ -389,13 +387,14 @@ void bcm_prpkt(const char *msg, struct sk_buff *p0)
for (p = p0; p; p = p->next)
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, p->data, p->len);
}
EXPORT_SYMBOL(bcm_prpkt);
EXPORT_SYMBOL(brcmu_prpkt);
#endif /* defined(BCMDBG) */
/* iovar table lookup */
const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
const struct brcmu_iovar *brcmu_iovar_lookup(const struct brcmu_iovar *table,
const char *name)
{
const bcm_iovar_t *vi;
const struct brcmu_iovar *vi;
const char *lookup_name;
/* skip any ':' delimited option prefixes */
@ -413,9 +412,10 @@ const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
return NULL; /* var name not found */
}
EXPORT_SYMBOL(bcm_iovar_lookup);
EXPORT_SYMBOL(brcmu_iovar_lookup);
int bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
int brcmu_iovar_lencheck(const struct brcmu_iovar *vi, void *arg, int len,
bool set)
{
int bcmerror = 0;
@ -458,7 +458,7 @@ int bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
return bcmerror;
}
EXPORT_SYMBOL(bcm_iovar_lencheck);
EXPORT_SYMBOL(brcmu_iovar_lencheck);
/*******************************************************************************
* crc8
@ -517,7 +517,7 @@ static const u8 crc8_table[256] = {
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
};
u8 bcm_crc8(u8 *pdata, /* pointer to array of data to process */
u8 brcmu_crc8(u8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
u8 crc /* either CRC8_INIT_VALUE or previous return value */
) {
@ -527,19 +527,19 @@ u8 bcm_crc8(u8 *pdata, /* pointer to array of data to process */
return crc;
}
EXPORT_SYMBOL(bcm_crc8);
EXPORT_SYMBOL(brcmu_crc8);
/*
* Traverse a string of 1-byte tag/1-byte length/variable-length value
* triples, returning a pointer to the substring whose first element
* matches tag
*/
bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key)
struct brcmu_tlv *brcmu_parse_tlvs(void *buf, int buflen, uint key)
{
bcm_tlv_t *elt;
struct brcmu_tlv *elt;
int totlen;
elt = (bcm_tlv_t *) buf;
elt = (struct brcmu_tlv *) buf;
totlen = buflen;
/* find tagged parameter */
@ -550,18 +550,19 @@ bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key)
if ((elt->id == key) && (totlen >= (len + 2)))
return elt;
elt = (bcm_tlv_t *) ((u8 *) elt + (len + 2));
elt = (struct brcmu_tlv *) ((u8 *) elt + (len + 2));
totlen -= (len + 2);
}
return NULL;
}
EXPORT_SYMBOL(bcm_parse_tlvs);
EXPORT_SYMBOL(brcmu_parse_tlvs);
#if defined(BCMDBG)
int
bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
brcmu_format_flags(const struct brcmu_bit_desc *bd, u32 flags, char *buf,
int len)
{
int i;
char *p = buf;
@ -612,10 +613,10 @@ bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
return (int)(p - buf);
}
EXPORT_SYMBOL(bcm_format_flags);
EXPORT_SYMBOL(brcmu_format_flags);
/* print bytes formatted as hex to a string. return the resulting string length */
int bcm_format_hex(char *str, const void *bytes, int len)
int brcmu_format_hex(char *str, const void *bytes, int len)
{
int i;
char *p = str;
@ -627,10 +628,10 @@ int bcm_format_hex(char *str, const void *bytes, int len)
}
return (int)(p - str);
}
EXPORT_SYMBOL(bcm_format_hex);
EXPORT_SYMBOL(brcmu_format_hex);
#endif /* defined(BCMDBG) */
char *bcm_chipname(uint chipid, char *buf, uint len)
char *brcmu_chipname(uint chipid, char *buf, uint len)
{
const char *fmt;
@ -638,9 +639,9 @@ char *bcm_chipname(uint chipid, char *buf, uint len)
snprintf(buf, len, fmt, chipid);
return buf;
}
EXPORT_SYMBOL(bcm_chipname);
EXPORT_SYMBOL(brcmu_chipname);
uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
uint brcmu_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
{
uint len;
@ -657,7 +658,7 @@ uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
return len;
}
EXPORT_SYMBOL(bcm_mkiovar);
EXPORT_SYMBOL(brcmu_mkiovar);
/* Quarter dBm units to mW
* Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
@ -689,7 +690,7 @@ static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
};
u16 bcm_qdbm_to_mw(u8 qdbm)
u16 brcmu_qdbm_to_mw(u8 qdbm)
{
uint factor = 1;
int idx = qdbm - QDBM_OFFSET;
@ -712,9 +713,9 @@ u16 bcm_qdbm_to_mw(u8 qdbm)
*/
return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
}
EXPORT_SYMBOL(bcm_qdbm_to_mw);
EXPORT_SYMBOL(brcmu_qdbm_to_mw);
u8 bcm_mw_to_qdbm(u16 mw)
u8 brcmu_mw_to_qdbm(u16 mw)
{
u8 qdbm;
int offset;
@ -744,9 +745,9 @@ u8 bcm_mw_to_qdbm(u16 mw)
return qdbm;
}
EXPORT_SYMBOL(bcm_mw_to_qdbm);
EXPORT_SYMBOL(brcmu_mw_to_qdbm);
uint bcm_bitcount(u8 *bitmap, uint length)
uint brcmu_bitcount(u8 *bitmap, uint length)
{
uint bitcount = 0, i;
u8 tmp;
@ -759,18 +760,18 @@ uint bcm_bitcount(u8 *bitmap, uint length)
}
return bitcount;
}
EXPORT_SYMBOL(bcm_bitcount);
EXPORT_SYMBOL(brcmu_bitcount);
/* Initialization of bcmstrbuf structure */
void bcm_binit(struct bcmstrbuf *b, char *buf, uint size)
/* Initialization of brcmu_strbuf structure */
void brcmu_binit(struct brcmu_strbuf *b, char *buf, uint size)
{
b->origsize = b->size = size;
b->origbuf = b->buf = buf;
}
EXPORT_SYMBOL(bcm_binit);
EXPORT_SYMBOL(brcmu_binit);
/* Buffer sprintf wrapper to guard against buffer overflow */
int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
int brcmu_bprintf(struct brcmu_strbuf *b, const char *fmt, ...)
{
va_list ap;
int r;
@ -780,7 +781,7 @@ int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
/* Non Ansi C99 compliant returns -1,
* Ansi compliant return r >= b->size,
* bcmstdlib returns 0, handle all
* stdlib returns 0, handle all
*/
if ((r == -1) || (r >= (int)b->size) || (r == 0)) {
b->size = 0;
@ -793,4 +794,4 @@ int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
return r;
}
EXPORT_SYMBOL(bcm_bprintf);
EXPORT_SYMBOL(brcmu_bprintf);

18
drivers/staging/brcm80211/util/bcmwifi.c → drivers/staging/brcm80211/brcmutil/wifi.c
View File

@ -16,9 +16,9 @@
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmwifi.h>
#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
/*
* Verify the chanspec is using a legal set of parameters, i.e. that the
@ -26,7 +26,7 @@
* combination could be legal given any set of circumstances.
* RETURNS: true is the chanspec is malformed, false if it looks good.
*/
bool bcm_chspec_malformed(chanspec_t chanspec)
bool brcmu_chspec_malformed(chanspec_t chanspec)
{
/* must be 2G or 5G band */
if (!CHSPEC_IS5G(chanspec) && !CHSPEC_IS2G(chanspec))
@ -46,14 +46,14 @@ bool bcm_chspec_malformed(chanspec_t chanspec)
return false;
}
EXPORT_SYMBOL(bcm_chspec_malformed);
EXPORT_SYMBOL(brcmu_chspec_malformed);
/*
* This function returns the channel number that control traffic is being sent on, for legacy
* channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
u8 bcm_chspec_ctlchan(chanspec_t chspec)
u8 brcmu_chspec_ctlchan(chanspec_t chspec)
{
u8 ctl_chan;
@ -76,7 +76,7 @@ u8 bcm_chspec_ctlchan(chanspec_t chspec)
return ctl_chan;
}
EXPORT_SYMBOL(bcm_chspec_ctlchan);
EXPORT_SYMBOL(brcmu_chspec_ctlchan);
/*
* Return the channel number for a given frequency and base frequency.
@ -97,7 +97,7 @@ EXPORT_SYMBOL(bcm_chspec_ctlchan);
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
int bcm_mhz2channel(uint freq, uint start_factor)
int brcmu_mhz2channel(uint freq, uint start_factor)
{
int ch = -1;
uint base;
@ -133,5 +133,5 @@ int bcm_mhz2channel(uint freq, uint start_factor)
return ch;
}
EXPORT_SYMBOL(bcm_mhz2channel);
EXPORT_SYMBOL(brcmu_mhz2channel);

374
drivers/staging/brcm80211/include/aidmp.h
View File

@ -1,374 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _AIDMP_H
#define _AIDMP_H
/* Manufacturer Ids */
#define MFGID_ARM 0x43b
#define MFGID_BRCM 0x4bf
#define MFGID_MIPS 0x4a7
/* Component Classes */
#define CC_SIM 0
#define CC_EROM 1
#define CC_CORESIGHT 9
#define CC_VERIF 0xb
#define CC_OPTIMO 0xd
#define CC_GEN 0xe
#define CC_PRIMECELL 0xf
/* Enumeration ROM registers */
#define ER_EROMENTRY 0x000
#define ER_REMAPCONTROL 0xe00
#define ER_REMAPSELECT 0xe04
#define ER_MASTERSELECT 0xe10
#define ER_ITCR 0xf00
#define ER_ITIP 0xf04
/* Erom entries */
#define ER_TAG 0xe
#define ER_TAG1 0x6
#define ER_VALID 1
#define ER_CI 0
#define ER_MP 2
#define ER_ADD 4
#define ER_END 0xe
#define ER_BAD 0xffffffff
/* EROM CompIdentA */
#define CIA_MFG_MASK 0xfff00000
#define CIA_MFG_SHIFT 20
#define CIA_CID_MASK 0x000fff00
#define CIA_CID_SHIFT 8
#define CIA_CCL_MASK 0x000000f0
#define CIA_CCL_SHIFT 4
/* EROM CompIdentB */
#define CIB_REV_MASK 0xff000000
#define CIB_REV_SHIFT 24
#define CIB_NSW_MASK 0x00f80000
#define CIB_NSW_SHIFT 19
#define CIB_NMW_MASK 0x0007c000
#define CIB_NMW_SHIFT 14
#define CIB_NSP_MASK 0x00003e00
#define CIB_NSP_SHIFT 9
#define CIB_NMP_MASK 0x000001f0
#define CIB_NMP_SHIFT 4
/* EROM MasterPortDesc */
#define MPD_MUI_MASK 0x0000ff00
#define MPD_MUI_SHIFT 8
#define MPD_MP_MASK 0x000000f0
#define MPD_MP_SHIFT 4
/* EROM AddrDesc */
#define AD_ADDR_MASK 0xfffff000
#define AD_SP_MASK 0x00000f00
#define AD_SP_SHIFT 8
#define AD_ST_MASK 0x000000c0
#define AD_ST_SHIFT 6
#define AD_ST_SLAVE 0x00000000
#define AD_ST_BRIDGE 0x00000040
#define AD_ST_SWRAP 0x00000080
#define AD_ST_MWRAP 0x000000c0
#define AD_SZ_MASK 0x00000030
#define AD_SZ_SHIFT 4
#define AD_SZ_4K 0x00000000
#define AD_SZ_8K 0x00000010
#define AD_SZ_16K 0x00000020
#define AD_SZ_SZD 0x00000030
#define AD_AG32 0x00000008
#define AD_ADDR_ALIGN 0x00000fff
#define AD_SZ_BASE 0x00001000 /* 4KB */
/* EROM SizeDesc */
#define SD_SZ_MASK 0xfffff000
#define SD_SG32 0x00000008
#define SD_SZ_ALIGN 0x00000fff
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _aidmp {
u32 oobselina30; /* 0x000 */
u32 oobselina74; /* 0x004 */
u32 PAD[6];
u32 oobselinb30; /* 0x020 */
u32 oobselinb74; /* 0x024 */
u32 PAD[6];
u32 oobselinc30; /* 0x040 */
u32 oobselinc74; /* 0x044 */
u32 PAD[6];
u32 oobselind30; /* 0x060 */
u32 oobselind74; /* 0x064 */
u32 PAD[38];
u32 oobselouta30; /* 0x100 */
u32 oobselouta74; /* 0x104 */
u32 PAD[6];
u32 oobseloutb30; /* 0x120 */
u32 oobseloutb74; /* 0x124 */
u32 PAD[6];
u32 oobseloutc30; /* 0x140 */
u32 oobseloutc74; /* 0x144 */
u32 PAD[6];
u32 oobseloutd30; /* 0x160 */
u32 oobseloutd74; /* 0x164 */
u32 PAD[38];
u32 oobsynca; /* 0x200 */
u32 oobseloutaen; /* 0x204 */
u32 PAD[6];
u32 oobsyncb; /* 0x220 */
u32 oobseloutben; /* 0x224 */
u32 PAD[6];
u32 oobsyncc; /* 0x240 */
u32 oobseloutcen; /* 0x244 */
u32 PAD[6];
u32 oobsyncd; /* 0x260 */
u32 oobseloutden; /* 0x264 */
u32 PAD[38];
u32 oobaextwidth; /* 0x300 */
u32 oobainwidth; /* 0x304 */
u32 oobaoutwidth; /* 0x308 */
u32 PAD[5];
u32 oobbextwidth; /* 0x320 */
u32 oobbinwidth; /* 0x324 */
u32 oobboutwidth; /* 0x328 */
u32 PAD[5];
u32 oobcextwidth; /* 0x340 */
u32 oobcinwidth; /* 0x344 */
u32 oobcoutwidth; /* 0x348 */
u32 PAD[5];
u32 oobdextwidth; /* 0x360 */
u32 oobdinwidth; /* 0x364 */
u32 oobdoutwidth; /* 0x368 */
u32 PAD[37];
u32 ioctrlset; /* 0x400 */
u32 ioctrlclear; /* 0x404 */
u32 ioctrl; /* 0x408 */
u32 PAD[61];
u32 iostatus; /* 0x500 */
u32 PAD[127];
u32 ioctrlwidth; /* 0x700 */
u32 iostatuswidth; /* 0x704 */
u32 PAD[62];
u32 resetctrl; /* 0x800 */
u32 resetstatus; /* 0x804 */
u32 resetreadid; /* 0x808 */
u32 resetwriteid; /* 0x80c */
u32 PAD[60];
u32 errlogctrl; /* 0x900 */
u32 errlogdone; /* 0x904 */
u32 errlogstatus; /* 0x908 */
u32 errlogaddrlo; /* 0x90c */
u32 errlogaddrhi; /* 0x910 */
u32 errlogid; /* 0x914 */
u32 errloguser; /* 0x918 */
u32 errlogflags; /* 0x91c */
u32 PAD[56];
u32 intstatus; /* 0xa00 */
u32 PAD[127];
u32 config; /* 0xe00 */
u32 PAD[63];
u32 itcr; /* 0xf00 */
u32 PAD[3];
u32 itipooba; /* 0xf10 */
u32 itipoobb; /* 0xf14 */
u32 itipoobc; /* 0xf18 */
u32 itipoobd; /* 0xf1c */
u32 PAD[4];
u32 itipoobaout; /* 0xf30 */
u32 itipoobbout; /* 0xf34 */
u32 itipoobcout; /* 0xf38 */
u32 itipoobdout; /* 0xf3c */
u32 PAD[4];
u32 itopooba; /* 0xf50 */
u32 itopoobb; /* 0xf54 */
u32 itopoobc; /* 0xf58 */
u32 itopoobd; /* 0xf5c */
u32 PAD[4];
u32 itopoobain; /* 0xf70 */
u32 itopoobbin; /* 0xf74 */
u32 itopoobcin; /* 0xf78 */
u32 itopoobdin; /* 0xf7c */
u32 PAD[4];
u32 itopreset; /* 0xf90 */
u32 PAD[15];
u32 peripherialid4; /* 0xfd0 */
u32 peripherialid5; /* 0xfd4 */
u32 peripherialid6; /* 0xfd8 */
u32 peripherialid7; /* 0xfdc */
u32 peripherialid0; /* 0xfe0 */
u32 peripherialid1; /* 0xfe4 */
u32 peripherialid2; /* 0xfe8 */
u32 peripherialid3; /* 0xfec */
u32 componentid0; /* 0xff0 */
u32 componentid1; /* 0xff4 */
u32 componentid2; /* 0xff8 */
u32 componentid3; /* 0xffc */
} aidmp_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* Out-of-band Router registers */
#define OOB_BUSCONFIG 0x020
#define OOB_STATUSA 0x100
#define OOB_STATUSB 0x104
#define OOB_STATUSC 0x108
#define OOB_STATUSD 0x10c
#define OOB_ENABLEA0 0x200
#define OOB_ENABLEA1 0x204
#define OOB_ENABLEA2 0x208
#define OOB_ENABLEA3 0x20c
#define OOB_ENABLEB0 0x280
#define OOB_ENABLEB1 0x284
#define OOB_ENABLEB2 0x288
#define OOB_ENABLEB3 0x28c
#define OOB_ENABLEC0 0x300
#define OOB_ENABLEC1 0x304
#define OOB_ENABLEC2 0x308
#define OOB_ENABLEC3 0x30c
#define OOB_ENABLED0 0x380
#define OOB_ENABLED1 0x384
#define OOB_ENABLED2 0x388
#define OOB_ENABLED3 0x38c
#define OOB_ITCR 0xf00
#define OOB_ITIPOOBA 0xf10
#define OOB_ITIPOOBB 0xf14
#define OOB_ITIPOOBC 0xf18
#define OOB_ITIPOOBD 0xf1c
#define OOB_ITOPOOBA 0xf30
#define OOB_ITOPOOBB 0xf34
#define OOB_ITOPOOBC 0xf38
#define OOB_ITOPOOBD 0xf3c
/* DMP wrapper registers */
#define AI_OOBSELINA30 0x000
#define AI_OOBSELINA74 0x004
#define AI_OOBSELINB30 0x020
#define AI_OOBSELINB74 0x024
#define AI_OOBSELINC30 0x040
#define AI_OOBSELINC74 0x044
#define AI_OOBSELIND30 0x060
#define AI_OOBSELIND74 0x064
#define AI_OOBSELOUTA30 0x100
#define AI_OOBSELOUTA74 0x104
#define AI_OOBSELOUTB30 0x120
#define AI_OOBSELOUTB74 0x124
#define AI_OOBSELOUTC30 0x140
#define AI_OOBSELOUTC74 0x144
#define AI_OOBSELOUTD30 0x160
#define AI_OOBSELOUTD74 0x164
#define AI_OOBSYNCA 0x200
#define AI_OOBSELOUTAEN 0x204
#define AI_OOBSYNCB 0x220
#define AI_OOBSELOUTBEN 0x224
#define AI_OOBSYNCC 0x240
#define AI_OOBSELOUTCEN 0x244
#define AI_OOBSYNCD 0x260
#define AI_OOBSELOUTDEN 0x264
#define AI_OOBAEXTWIDTH 0x300
#define AI_OOBAINWIDTH 0x304
#define AI_OOBAOUTWIDTH 0x308
#define AI_OOBBEXTWIDTH 0x320
#define AI_OOBBINWIDTH 0x324
#define AI_OOBBOUTWIDTH 0x328
#define AI_OOBCEXTWIDTH 0x340
#define AI_OOBCINWIDTH 0x344
#define AI_OOBCOUTWIDTH 0x348
#define AI_OOBDEXTWIDTH 0x360
#define AI_OOBDINWIDTH 0x364
#define AI_OOBDOUTWIDTH 0x368
#if defined(__BIG_ENDIAN) && defined(BCMHND74K)
/* Selective swapped defines for those registers we need in
* big-endian code.
*/
#define AI_IOCTRLSET 0x404
#define AI_IOCTRLCLEAR 0x400
#define AI_IOCTRL 0x40c
#define AI_IOSTATUS 0x504
#define AI_RESETCTRL 0x804
#define AI_RESETSTATUS 0x800
#else /* !__BIG_ENDIAN || !BCMHND74K */
#define AI_IOCTRLSET 0x400
#define AI_IOCTRLCLEAR 0x404
#define AI_IOCTRL 0x408
#define AI_IOSTATUS 0x500
#define AI_RESETCTRL 0x800
#define AI_RESETSTATUS 0x804
#endif /* __BIG_ENDIAN && BCMHND74K */
#define AI_IOCTRLWIDTH 0x700
#define AI_IOSTATUSWIDTH 0x704
#define AI_RESETREADID 0x808
#define AI_RESETWRITEID 0x80c
#define AI_ERRLOGCTRL 0xa00
#define AI_ERRLOGDONE 0xa04
#define AI_ERRLOGSTATUS 0xa08
#define AI_ERRLOGADDRLO 0xa0c
#define AI_ERRLOGADDRHI 0xa10
#define AI_ERRLOGID 0xa14
#define AI_ERRLOGUSER 0xa18
#define AI_ERRLOGFLAGS 0xa1c
#define AI_INTSTATUS 0xa00
#define AI_CONFIG 0xe00
#define AI_ITCR 0xf00
#define AI_ITIPOOBA 0xf10
#define AI_ITIPOOBB 0xf14
#define AI_ITIPOOBC 0xf18
#define AI_ITIPOOBD 0xf1c
#define AI_ITIPOOBAOUT 0xf30
#define AI_ITIPOOBBOUT 0xf34
#define AI_ITIPOOBCOUT 0xf38
#define AI_ITIPOOBDOUT 0xf3c
#define AI_ITOPOOBA 0xf50
#define AI_ITOPOOBB 0xf54
#define AI_ITOPOOBC 0xf58
#define AI_ITOPOOBD 0xf5c
#define AI_ITOPOOBAIN 0xf70
#define AI_ITOPOOBBIN 0xf74
#define AI_ITOPOOBCIN 0xf78
#define AI_ITOPOOBDIN 0xf7c
#define AI_ITOPRESET 0xf90
#define AI_PERIPHERIALID4 0xfd0
#define AI_PERIPHERIALID5 0xfd4
#define AI_PERIPHERIALID6 0xfd8
#define AI_PERIPHERIALID7 0xfdc
#define AI_PERIPHERIALID0 0xfe0
#define AI_PERIPHERIALID1 0xfe4
#define AI_PERIPHERIALID2 0xfe8
#define AI_PERIPHERIALID3 0xfec
#define AI_COMPONENTID0 0xff0
#define AI_COMPONENTID1 0xff4
#define AI_COMPONENTID2 0xff8
#define AI_COMPONENTID3 0xffc
/* resetctrl */
#define AIRC_RESET 1
/* config */
#define AICFG_OOB 0x00000020
#define AICFG_IOS 0x00000010
#define AICFG_IOC 0x00000008
#define AICFG_TO 0x00000004
#define AICFG_ERRL 0x00000002
#define AICFG_RST 0x00000001
#endif /* _AIDMP_H */

150
drivers/staging/brcm80211/include/bcmdefs.h
View File

@ -1,150 +0,0 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmdefs_h_
#define _bcmdefs_h_
#define SI_BUS 0
#define PCI_BUS 1
#define PCMCIA_BUS 2
#define SDIO_BUS 3
#define JTAG_BUS 4
#define USB_BUS 5
#define SPI_BUS 6
#ifndef OFF
#define OFF 0
#endif
#ifndef ON
#define ON 1 /* ON = 1 */
#endif
#define AUTO (-1) /* Auto = -1 */
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
#ifdef BCMDMA64OSL
typedef struct {
u32 loaddr;
u32 hiaddr;
} dma64addr_t;
typedef dma64addr_t dmaaddr_t;
#define PHYSADDRHI(_pa) ((_pa).hiaddr)
#define PHYSADDRHISET(_pa, _val) \
do { \
(_pa).hiaddr = (_val); \
} while (0)
#define PHYSADDRLO(_pa) ((_pa).loaddr)
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa).loaddr = (_val); \
} while (0)
#else
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa) = (_val); \
} while (0)
#endif /* BCMDMA64OSL */
/* One physical DMA segment */
typedef struct {
dmaaddr_t addr;
u32 length;
} hnddma_seg_t;
#define MAX_DMA_SEGS 4
typedef struct {
void *oshdmah; /* Opaque handle for OSL to store its information */
uint origsize; /* Size of the virtual packet */
uint nsegs;
hnddma_seg_t segs[MAX_DMA_SEGS];
} hnddma_seg_map_t;
/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
* There is a compile time check in wlc.c which ensure that this value is at least as big
* as TXOFF. This value is used in dma_rxfill (hnddma.c).
*/
#define BCMEXTRAHDROOM 172
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
* #define <NAME>_S 4
* ...
* regval = R_REG(osh, &regs->regfoo);
* field = GFIELD(regval, <NAME>);
* regval = SFIELD(regval, <NAME>, 1);
* W_REG(osh, &regs->regfoo, regval);
*/
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
/*
* Priority definitions according 802.1D
*/
#define PRIO_8021D_NONE 2
#define PRIO_8021D_BK 1
#define PRIO_8021D_BE 0
#define PRIO_8021D_EE 3
#define PRIO_8021D_CL 4
#define PRIO_8021D_VI 5
#define PRIO_8021D_VO 6
#define PRIO_8021D_NC 7
#define MAXPRIO 7
#define NUMPRIO (MAXPRIO + 1)
/* Max. nvram variable table size */
#define MAXSZ_NVRAM_VARS 4096
/* handle forward declaration */
struct wl_info;
struct wlc_bsscfg;
#endif /* _bcmdefs_h_ */

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