linux-can-fixes-for-5.18-20220514
-----BEGIN PGP SIGNATURE----- iQFHBAABCgAxFiEEBsvAIBsPu6mG7thcrX5LkNig010FAmJ/+pYTHG1rbEBwZW5n dXRyb25peC5kZQAKCRCtfkuQ2KDTXQSHB/9EEcms7LYv1N+SftYGIOA/rY+dhD+o N6aLI0aFI3K1SK7BcnSuvamO+Wi6pEH/8twe/fFSphaKiQIiy7rE+FmU0BLPcvG1 ejISzRUdxDkWW0X7fZQfObf9MGOlostXjYWPb396OfOR/z45DvFmhuJX1ye/9W5+ HFmfbsGkDKzmZhgXrkP1Zj3ag4br2qJLPGsWmiH4QBBeWT6dokfqxiM0rNjA18Hp gytGQ6AycHFhyEaAuyEQKNCpsce/s1f/dpQ5EsSxbNEHT4aV1qwc05fL4/SHmEih zR8QjIy9d0I7fprM5VXrbLt5e7aQR9XIaJIZ+iL8t2LYhCnw/g4xkEQe =ANrU -----END PGP SIGNATURE----- Merge tag 'linux-can-fixes-for-5.18-20220514' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can Marc Kleine-Budde says: ==================== pull-request: can 2022-05-14 this is a pull request of 2 patches for net/master. Changes to linux-can-fixes-for-5.18-20220513: - adjusted Fixes: Tag on "Revert "can: m_can: pci: use custom bit timings for Elkhart Lake"" (Thanks Jakub) Both patches are by Jarkko Nikula, target the m_can PCI driver bindings, and fix usage of wrong bit timing constants for the Elkhart Lake platform. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
dbd5f5d868
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@ -1495,34 +1495,22 @@ static int m_can_dev_setup(struct m_can_classdev *cdev)
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err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
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if (err)
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return err;
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_30X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_30X;
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cdev->can.bittiming_const = &m_can_bittiming_const_30X;
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cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
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break;
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case 31:
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/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
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err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
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if (err)
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return err;
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_31X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_31X;
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cdev->can.bittiming_const = &m_can_bittiming_const_31X;
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cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
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break;
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case 32:
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case 33:
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/* Support both MCAN version v3.2.x and v3.3.0 */
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_31X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_31X;
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cdev->can.bittiming_const = &m_can_bittiming_const_31X;
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cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
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cdev->can.ctrlmode_supported |=
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(m_can_niso_supported(cdev) ?
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@ -85,9 +85,6 @@ struct m_can_classdev {
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struct sk_buff *tx_skb;
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struct phy *transceiver;
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const struct can_bittiming_const *bit_timing;
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const struct can_bittiming_const *data_timing;
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struct m_can_ops *ops;
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int version;
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@ -18,14 +18,9 @@
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#define M_CAN_PCI_MMIO_BAR 0
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#define M_CAN_CLOCK_FREQ_EHL 200000000
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#define CTL_CSR_INT_CTL_OFFSET 0x508
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struct m_can_pci_config {
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const struct can_bittiming_const *bit_timing;
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const struct can_bittiming_const *data_timing;
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unsigned int clock_freq;
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};
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struct m_can_pci_priv {
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struct m_can_classdev cdev;
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@ -89,40 +84,9 @@ static struct m_can_ops m_can_pci_ops = {
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.read_fifo = iomap_read_fifo,
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};
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static const struct can_bittiming_const m_can_bittiming_const_ehl = {
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.name = KBUILD_MODNAME,
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.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
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.tseg1_max = 64,
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.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
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.tseg2_max = 128,
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.sjw_max = 128,
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.brp_min = 1,
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.brp_max = 512,
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.brp_inc = 1,
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};
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static const struct can_bittiming_const m_can_data_bittiming_const_ehl = {
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.name = KBUILD_MODNAME,
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.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
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.tseg1_max = 16,
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.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 32,
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.brp_inc = 1,
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};
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static const struct m_can_pci_config m_can_pci_ehl = {
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.bit_timing = &m_can_bittiming_const_ehl,
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.data_timing = &m_can_data_bittiming_const_ehl,
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.clock_freq = 200000000,
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};
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static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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struct device *dev = &pci->dev;
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const struct m_can_pci_config *cfg;
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struct m_can_classdev *mcan_class;
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struct m_can_pci_priv *priv;
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void __iomem *base;
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@ -150,8 +114,6 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
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if (!mcan_class)
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return -ENOMEM;
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cfg = (const struct m_can_pci_config *)id->driver_data;
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priv = cdev_to_priv(mcan_class);
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priv->base = base;
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@ -163,9 +125,7 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
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mcan_class->dev = &pci->dev;
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mcan_class->net->irq = pci_irq_vector(pci, 0);
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mcan_class->pm_clock_support = 1;
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mcan_class->bit_timing = cfg->bit_timing;
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mcan_class->data_timing = cfg->data_timing;
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mcan_class->can.clock.freq = cfg->clock_freq;
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mcan_class->can.clock.freq = id->driver_data;
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mcan_class->ops = &m_can_pci_ops;
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pci_set_drvdata(pci, mcan_class);
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@ -218,8 +178,8 @@ static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
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m_can_pci_suspend, m_can_pci_resume);
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static const struct pci_device_id m_can_pci_id_table[] = {
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{ PCI_VDEVICE(INTEL, 0x4bc1), (kernel_ulong_t)&m_can_pci_ehl, },
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{ PCI_VDEVICE(INTEL, 0x4bc2), (kernel_ulong_t)&m_can_pci_ehl, },
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{ PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
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{ PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
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{ } /* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
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