ASoC: fsl_sai: Add support for i.MX8MM, MP, ULP
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>: ASoC: fsl_sai: Add support for i.MX8MM, MP, ULP platforms
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dba2d5ae4c
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@ -1147,7 +1147,7 @@ static int fsl_sai_probe(struct platform_device *pdev)
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/* Select MCLK direction */
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if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
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sai->verid.version >= 0x0301) {
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sai->soc_data->max_register >= FSL_SAI_MCTL) {
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regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
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FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
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}
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@ -1203,6 +1203,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
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.reg_offset = 0,
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.mclk0_is_mclk1 = false,
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.flags = 0,
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.max_register = FSL_SAI_RMR,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
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@ -1213,6 +1214,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
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.reg_offset = 0,
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.mclk0_is_mclk1 = true,
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.flags = 0,
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.max_register = FSL_SAI_RMR,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
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@ -1223,6 +1225,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
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.reg_offset = 8,
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.mclk0_is_mclk1 = false,
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.flags = PMQOS_CPU_LATENCY,
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.max_register = FSL_SAI_RMR,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
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@ -1233,6 +1236,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
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.reg_offset = 8,
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.mclk0_is_mclk1 = false,
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.flags = 0,
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.max_register = FSL_SAI_RMR,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
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@ -1243,6 +1247,40 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
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.reg_offset = 0,
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.mclk0_is_mclk1 = false,
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.flags = 0,
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.max_register = FSL_SAI_RMR,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
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.use_imx_pcm = true,
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.use_edma = false,
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.fifo_depth = 128,
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.reg_offset = 8,
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.mclk0_is_mclk1 = false,
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.pins = 8,
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.flags = 0,
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.max_register = FSL_SAI_MCTL,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
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.use_imx_pcm = true,
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.use_edma = false,
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.fifo_depth = 128,
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.reg_offset = 8,
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.mclk0_is_mclk1 = false,
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.pins = 8,
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.flags = 0,
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.max_register = FSL_SAI_MDIV,
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};
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static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
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.use_imx_pcm = true,
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.use_edma = true,
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.fifo_depth = 16,
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.reg_offset = 8,
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.mclk0_is_mclk1 = false,
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.pins = 4,
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.flags = PMQOS_CPU_LATENCY,
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.max_register = FSL_SAI_RTCAP,
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};
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static const struct of_device_id fsl_sai_ids[] = {
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@ -1252,6 +1290,9 @@ static const struct of_device_id fsl_sai_ids[] = {
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{ .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
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{ .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
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{ .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
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{ .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
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{ .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
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{ .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_sai_ids);
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@ -223,6 +223,7 @@ struct fsl_sai_soc_data {
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unsigned int pins;
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unsigned int reg_offset;
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unsigned int flags;
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unsigned int max_register;
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};
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/**
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