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media: camss: Point sm8250 at the correct vdda regulators 

Reviewing the RB5 schematic its clear that we have missed out on defining
both of the power-rails associated with the CSI PHY.

Other PHYs such as the UFS, PCIe and USB connect to these rails and define
each regulator individually.

This means if we were to switch off the other various PHYs which enable
these rails, the CAMSS would not appropriately power-on the CSI PHY.

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Bryan O'Donoghue 2022-01-11 13:52:12 +01:00 committed by Mauro Carvalho Chehab
parent 0c4d7fda5c
commit db95031d8f
1 changed files with 4 additions and 4 deletions
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8
drivers/media/platform/qcom/camss/camss.c
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@ -723,7 +723,7 @@ static const struct resources csiphy_res_8250[] = {
static const struct resources csid_res_8250[] = { static const struct resources csid_res_8250[] = {
/* CSID0 */ /* CSID0 */
{ {
.regulators = { NULL }, .regulators = { "vdda-phy", "vdda-pll" },
.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
.clock_rate = { { 400000000 }, .clock_rate = { { 400000000 },
{ 400000000 }, { 400000000 },
@ -735,7 +735,7 @@ static const struct resources csid_res_8250[] = {
}, },
/* CSID1 */ /* CSID1 */
{ {
.regulators = { NULL }, .regulators = { "vdda-phy", "vdda-pll" },
.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
.clock_rate = { { 400000000 }, .clock_rate = { { 400000000 },
{ 400000000 }, { 400000000 },
@ -747,7 +747,7 @@ static const struct resources csid_res_8250[] = {
}, },
/* CSID2 */ /* CSID2 */
{ {
.regulators = { NULL }, .regulators = { "vdda-phy", "vdda-pll" },
.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
.clock_rate = { { 400000000 }, .clock_rate = { { 400000000 },
{ 400000000 }, { 400000000 },
@ -758,7 +758,7 @@ static const struct resources csid_res_8250[] = {
}, },
/* CSID3 */ /* CSID3 */
{ {
.regulators = { NULL }, .regulators = { "vdda-phy", "vdda-pll" },
.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
.clock_rate = { { 400000000 }, .clock_rate = { { 400000000 },
{ 400000000 }, { 400000000 },