drm/amd/display: Add DCN3 HUBP
Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)
HW Blocks:
+--------++------+
| HUBBUB || HUBP |
+--------++------+
|
v
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha
Alex Deucher
parent
8f712e3e5e
commit
db7b0216c4
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@ -62,6 +62,9 @@ enum dc_plane_addr_type {
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PLN_ADDR_TYPE_GRAPHICS = 0,
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PLN_ADDR_TYPE_GRPH_STEREO,
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PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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PLN_ADDR_TYPE_RGBEA
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#endif
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};
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struct dc_plane_address {
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@ -84,6 +87,16 @@ struct dc_plane_address {
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PHYSICAL_ADDRESS_LOC right_meta_addr;
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union large_integer right_dcc_const_color;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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PHYSICAL_ADDRESS_LOC left_alpha_addr;
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PHYSICAL_ADDRESS_LOC left_alpha_meta_addr;
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union large_integer left_alpha_dcc_const_color;
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PHYSICAL_ADDRESS_LOC right_alpha_addr;
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PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;
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union large_integer right_alpha_dcc_const_color;
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#endif
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} grph_stereo;
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/*video progressive*/
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@ -96,6 +109,18 @@ struct dc_plane_address {
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PHYSICAL_ADDRESS_LOC chroma_meta_addr;
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union large_integer chroma_dcc_const_color;
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} video_progressive;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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struct {
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PHYSICAL_ADDRESS_LOC addr;
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PHYSICAL_ADDRESS_LOC meta_addr;
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union large_integer dcc_const_color;
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PHYSICAL_ADDRESS_LOC alpha_addr;
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PHYSICAL_ADDRESS_LOC alpha_meta_addr;
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union large_integer alpha_dcc_const_color;
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} rgbea;
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#endif
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};
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union large_integer page_table_base;
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@ -131,9 +156,15 @@ struct dc_plane_dcc_param {
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int meta_pitch;
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bool independent_64b_blks;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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uint8_t dcc_ind_blk;
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#endif
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int meta_pitch_c;
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bool independent_64b_blks_c;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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uint8_t dcc_ind_blk_c;
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#endif
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};
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/*Displayable pixel format in fb*/
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@ -169,6 +200,10 @@ enum surface_pixel_format {
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SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
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SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
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SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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SURFACE_PIXEL_FORMAT_GRPH_RGBE,
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SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA,
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#endif
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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@ -326,6 +326,18 @@ void hubp1_program_pixel_format(
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 119);
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 0);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 1);
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break;
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#endif
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default:
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BREAK_TO_DEBUGGER();
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break;
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@ -336,6 +336,10 @@ void hubp2_program_size(
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*/
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use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
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&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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use_pitch_c = use_pitch_c
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|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
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#endif
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if (use_pitch_c) {
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ASSERT(plane_size->chroma_pitch != 0);
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/* Chroma pitch zero can cause system hang! */
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@ -360,6 +364,10 @@ void hubp2_program_size(
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PITCH, pitch, META_PITCH, meta_pitch);
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use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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use_pitch_c = use_pitch_c
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|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
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#endif
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if (use_pitch_c)
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REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
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PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
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@ -505,6 +513,18 @@ void hubp2_program_pixel_format(
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REG_UPDATE(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 119);
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break;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 0);
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
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REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
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SURFACE_PIXEL_FORMAT, 116,
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ALPHA_PLANE_EN, 1);
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break;
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#endif
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default:
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BREAK_TO_DEBUGGER();
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break;
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@ -157,6 +157,12 @@
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uint32_t VBLANK_PARAMETERS_5;\
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uint32_t VBLANK_PARAMETERS_6
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \
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DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
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uint32_t DCN_DMDATA_VM_CNTL
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#endif
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#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
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DCN_HUBP_REG_FIELD_BASE_LIST(type); \
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type DMDATA_ADDRESS_HIGH;\
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@ -192,17 +198,52 @@
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type REFCYC_PER_META_CHUNK_FLIP_C; \
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type VM_GROUP_SIZE
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
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DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
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type PRIMARY_SURFACE_DCC_IND_BLK;\
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type SECONDARY_SURFACE_DCC_IND_BLK;\
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type PRIMARY_SURFACE_DCC_IND_BLK_C;\
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type SECONDARY_SURFACE_DCC_IND_BLK_C;\
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type ALPHA_PLANE_EN;\
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type REFCYC_PER_VM_DMDATA;\
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type DMDATA_VM_FAULT_STATUS;\
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type DMDATA_VM_FAULT_STATUS_CLEAR; \
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type DMDATA_VM_UNDERFLOW_STATUS;\
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type DMDATA_VM_LATE_STATUS;\
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type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \
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type DMDATA_VM_DONE; \
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type CROSSBAR_SRC_Y_G; \
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type CROSSBAR_SRC_ALPHA; \
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type PACK_3TO2_ELEMENT_DISABLE; \
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type ROW_TTU_MODE; \
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type NUM_PKRS
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#endif
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struct dcn_hubp2_registers {
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
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#else
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DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
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#endif
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};
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struct dcn_hubp2_shift {
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
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#else
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DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
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#endif
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};
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struct dcn_hubp2_mask {
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
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#else
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DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
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#endif
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};
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struct dcn20_hubp {
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@ -0,0 +1,532 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dcn30_hubp.h"
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#include "dm_services.h"
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#include "dce_calcs.h"
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#include "reg_helper.h"
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#include "basics/conversion.h"
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#include "dcn20/dcn20_hubp.h"
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#include "dcn21/dcn21_hubp.h"
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#define REG(reg)\
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hubp2->hubp_regs->reg
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#define CTX \
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hubp2->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
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void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
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struct vm_system_aperture_param *apt)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
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PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
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// The format of default addr is 48:12 of the 48 bit addr
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mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
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// The format of high/low are 48:18 of the 48 bit addr
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mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
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mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
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REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
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REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
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MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
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REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
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ENABLE_L1_TLB, 1,
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SYSTEM_ACCESS_MODE, 0x3);
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}
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bool hubp3_program_surface_flip_and_addr(
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struct hubp *hubp,
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const struct dc_plane_address *address,
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bool flip_immediate)
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{
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
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//program flip type
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REG_UPDATE(DCSURF_FLIP_CONTROL,
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SURFACE_FLIP_TYPE, flip_immediate);
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// Program VMID reg
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if (flip_immediate == 0)
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REG_UPDATE(VMID_SETTINGS_0,
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VMID, address->vmid);
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if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
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} else {
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// turn off stereo if not in stereo
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
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REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
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}
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/* HW automatically latch rest of address register on write to
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* DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
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*
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* program high first and then the low addr, order matters!
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*/
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switch (address->type) {
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case PLN_ADDR_TYPE_GRAPHICS:
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/* DCN1.0 does not support const color
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* TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
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* base on address->grph.dcc_const_color
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* x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
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* x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
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*/
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if (address->grph.addr.quad_part == 0)
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break;
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REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
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if (address->grph.meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->grph.meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->grph.meta_addr.low_part);
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}
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->grph.addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->grph.addr.low_part);
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break;
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case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
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if (address->video_progressive.luma_addr.quad_part == 0
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|| address->video_progressive.chroma_addr.quad_part == 0)
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break;
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REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
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PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
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if (address->video_progressive.luma_meta_addr.quad_part != 0) {
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
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address->video_progressive.chroma_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
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PRIMARY_META_SURFACE_ADDRESS_C,
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address->video_progressive.chroma_meta_addr.low_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_META_SURFACE_ADDRESS_HIGH,
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address->video_progressive.luma_meta_addr.high_part);
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REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
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PRIMARY_META_SURFACE_ADDRESS,
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address->video_progressive.luma_meta_addr.low_part);
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}
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH_C,
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address->video_progressive.chroma_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
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PRIMARY_SURFACE_ADDRESS_C,
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address->video_progressive.chroma_addr.low_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
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PRIMARY_SURFACE_ADDRESS_HIGH,
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address->video_progressive.luma_addr.high_part);
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REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
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PRIMARY_SURFACE_ADDRESS,
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address->video_progressive.luma_addr.low_part);
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break;
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case PLN_ADDR_TYPE_GRPH_STEREO:
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if (address->grph_stereo.left_addr.quad_part == 0)
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break;
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if (address->grph_stereo.right_addr.quad_part == 0)
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break;
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REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
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PRIMARY_SURFACE_TMZ, address->tmz_surface,
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||||
PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
|
||||
PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
|
||||
PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
|
||||
SECONDARY_SURFACE_TMZ, address->tmz_surface,
|
||||
SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
|
||||
SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
|
||||
SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
|
||||
|
||||
if (address->grph_stereo.right_meta_addr.quad_part != 0) {
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
|
||||
address->grph_stereo.right_alpha_meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
|
||||
SECONDARY_META_SURFACE_ADDRESS_C,
|
||||
address->grph_stereo.right_alpha_meta_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
|
||||
SECONDARY_META_SURFACE_ADDRESS_HIGH,
|
||||
address->grph_stereo.right_meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
|
||||
SECONDARY_META_SURFACE_ADDRESS,
|
||||
address->grph_stereo.right_meta_addr.low_part);
|
||||
}
|
||||
if (address->grph_stereo.left_meta_addr.quad_part != 0) {
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
|
||||
address->grph_stereo.left_alpha_meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_C,
|
||||
address->grph_stereo.left_alpha_meta_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_HIGH,
|
||||
address->grph_stereo.left_meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS,
|
||||
address->grph_stereo.left_meta_addr.low_part);
|
||||
}
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
SECONDARY_SURFACE_ADDRESS_HIGH_C,
|
||||
address->grph_stereo.right_alpha_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
|
||||
SECONDARY_SURFACE_ADDRESS_C,
|
||||
address->grph_stereo.right_alpha_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
|
||||
SECONDARY_SURFACE_ADDRESS_HIGH,
|
||||
address->grph_stereo.right_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
|
||||
SECONDARY_SURFACE_ADDRESS,
|
||||
address->grph_stereo.right_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_HIGH_C,
|
||||
address->grph_stereo.left_alpha_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_C,
|
||||
address->grph_stereo.left_alpha_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_HIGH,
|
||||
address->grph_stereo.left_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
|
||||
PRIMARY_SURFACE_ADDRESS,
|
||||
address->grph_stereo.left_addr.low_part);
|
||||
break;
|
||||
case PLN_ADDR_TYPE_RGBEA:
|
||||
if (address->rgbea.addr.quad_part == 0
|
||||
|| address->rgbea.alpha_addr.quad_part == 0)
|
||||
break;
|
||||
|
||||
REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
|
||||
PRIMARY_SURFACE_TMZ, address->tmz_surface,
|
||||
PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
|
||||
PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
|
||||
PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
|
||||
|
||||
if (address->rgbea.meta_addr.quad_part != 0) {
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
|
||||
address->rgbea.alpha_meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_C,
|
||||
address->rgbea.alpha_meta_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS_HIGH,
|
||||
address->rgbea.meta_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
|
||||
PRIMARY_META_SURFACE_ADDRESS,
|
||||
address->rgbea.meta_addr.low_part);
|
||||
}
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_HIGH_C,
|
||||
address->rgbea.alpha_addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_C,
|
||||
address->rgbea.alpha_addr.low_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
|
||||
PRIMARY_SURFACE_ADDRESS_HIGH,
|
||||
address->rgbea.addr.high_part);
|
||||
|
||||
REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
|
||||
PRIMARY_SURFACE_ADDRESS,
|
||||
address->rgbea.addr.low_part);
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
break;
|
||||
}
|
||||
|
||||
hubp->request_address = *address;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void hubp3_program_tiling(
|
||||
struct dcn20_hubp *hubp2,
|
||||
const union dc_tiling_info *info,
|
||||
const enum surface_pixel_format pixel_format)
|
||||
{
|
||||
REG_UPDATE_4(DCSURF_ADDR_CONFIG,
|
||||
NUM_PIPES, log_2(info->gfx9.num_pipes),
|
||||
PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
|
||||
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
|
||||
NUM_PKRS, log_2(info->gfx9.num_pkrs));
|
||||
|
||||
REG_UPDATE_3(DCSURF_TILING_CONFIG,
|
||||
SW_MODE, info->gfx9.swizzle,
|
||||
META_LINEAR, info->gfx9.meta_linear,
|
||||
PIPE_ALIGNED, info->gfx9.pipe_aligned);
|
||||
|
||||
}
|
||||
|
||||
void hubp3_dcc_control(struct hubp *hubp, bool enable,
|
||||
enum hubp_ind_block_size blk_size)
|
||||
{
|
||||
uint32_t dcc_en = enable ? 1 : 0;
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
|
||||
REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
|
||||
PRIMARY_SURFACE_DCC_EN, dcc_en,
|
||||
PRIMARY_SURFACE_DCC_IND_BLK, blk_size,
|
||||
SECONDARY_SURFACE_DCC_EN, dcc_en,
|
||||
SECONDARY_SURFACE_DCC_IND_BLK, blk_size);
|
||||
}
|
||||
|
||||
void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
|
||||
struct dc_plane_dcc_param *dcc)
|
||||
{
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
|
||||
/*Workaround until UMD fix the new dcc_ind_blk interface */
|
||||
if (dcc->independent_64b_blks && dcc->dcc_ind_blk == 0)
|
||||
dcc->dcc_ind_blk = 1;
|
||||
if (dcc->independent_64b_blks_c && dcc->dcc_ind_blk_c == 0)
|
||||
dcc->dcc_ind_blk_c = 1;
|
||||
|
||||
REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
|
||||
PRIMARY_SURFACE_DCC_EN, dcc->enable,
|
||||
PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
|
||||
PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,
|
||||
SECONDARY_SURFACE_DCC_EN, dcc->enable,
|
||||
SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
|
||||
SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);
|
||||
}
|
||||
|
||||
void hubp3_dmdata_set_attributes(
|
||||
struct hubp *hubp,
|
||||
const struct dc_dmdata_attributes *attr)
|
||||
{
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
|
||||
/*always HW mode */
|
||||
REG_UPDATE(DMDATA_CNTL,
|
||||
DMDATA_MODE, 1);
|
||||
|
||||
/* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
|
||||
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
|
||||
|
||||
/* toggle DMDATA_UPDATED and set repeat and size */
|
||||
REG_UPDATE(DMDATA_CNTL,
|
||||
DMDATA_UPDATED, 0);
|
||||
REG_UPDATE_3(DMDATA_CNTL,
|
||||
DMDATA_UPDATED, 1,
|
||||
DMDATA_REPEAT, attr->dmdata_repeat,
|
||||
DMDATA_SIZE, attr->dmdata_size);
|
||||
|
||||
/* set DMDATA address */
|
||||
REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
|
||||
REG_UPDATE(DMDATA_ADDRESS_HIGH,
|
||||
DMDATA_ADDRESS_HIGH, attr->address.high_part);
|
||||
|
||||
REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
|
||||
|
||||
}
|
||||
|
||||
|
||||
void hubp3_program_surface_config(
|
||||
struct hubp *hubp,
|
||||
enum surface_pixel_format format,
|
||||
union dc_tiling_info *tiling_info,
|
||||
struct plane_size *plane_size,
|
||||
enum dc_rotation_angle rotation,
|
||||
struct dc_plane_dcc_param *dcc,
|
||||
bool horizontal_mirror,
|
||||
unsigned int compat_level)
|
||||
{
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
|
||||
hubp3_dcc_control_sienna_cichlid(hubp, dcc);
|
||||
hubp3_program_tiling(hubp2, tiling_info, format);
|
||||
hubp2_program_size(hubp, format, plane_size, dcc);
|
||||
hubp2_program_rotation(hubp, rotation, horizontal_mirror);
|
||||
hubp2_program_pixel_format(hubp, format);
|
||||
}
|
||||
|
||||
static void hubp3_program_deadline(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
|
||||
{
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
|
||||
hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
|
||||
REG_UPDATE(DCN_DMDATA_VM_CNTL,
|
||||
REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
|
||||
}
|
||||
|
||||
void hubp3_read_state(struct hubp *hubp)
|
||||
{
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
struct dcn_hubp_state *s = &hubp2->state;
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
|
||||
|
||||
hubp2_read_state_common(hubp);
|
||||
|
||||
REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,
|
||||
CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
|
||||
MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
|
||||
META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
|
||||
MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
|
||||
DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
|
||||
SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
|
||||
PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
|
||||
|
||||
REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
|
||||
CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
|
||||
MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
|
||||
META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
|
||||
MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
|
||||
DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
|
||||
SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
|
||||
PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
|
||||
|
||||
}
|
||||
|
||||
void hubp3_setup(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
|
||||
{
|
||||
/* otg is locked when this func is called. Register are double buffered.
|
||||
* disable the requestors is not needed
|
||||
*/
|
||||
hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
|
||||
hubp21_program_requestor(hubp, rq_regs);
|
||||
hubp3_program_deadline(hubp, dlg_attr, ttu_attr);
|
||||
}
|
||||
|
||||
void hubp3_init(struct hubp *hubp)
|
||||
{
|
||||
// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
|
||||
// This is a chicken bit to enable the ECO fix.
|
||||
|
||||
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
|
||||
//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
|
||||
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
|
||||
}
|
||||
|
||||
static struct hubp_funcs dcn30_hubp_funcs = {
|
||||
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
|
||||
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
|
||||
.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
|
||||
.hubp_program_surface_config = hubp3_program_surface_config,
|
||||
.hubp_is_flip_pending = hubp2_is_flip_pending,
|
||||
.hubp_setup = hubp3_setup,
|
||||
.hubp_setup_interdependent = hubp2_setup_interdependent,
|
||||
.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
|
||||
.set_blank = hubp2_set_blank,
|
||||
.dcc_control = hubp3_dcc_control,
|
||||
.mem_program_viewport = min_set_viewport,
|
||||
.set_cursor_attributes = hubp2_cursor_set_attributes,
|
||||
.set_cursor_position = hubp2_cursor_set_position,
|
||||
.hubp_clk_cntl = hubp2_clk_cntl,
|
||||
.hubp_vtg_sel = hubp2_vtg_sel,
|
||||
.dmdata_set_attributes = hubp3_dmdata_set_attributes,
|
||||
.dmdata_load = hubp2_dmdata_load,
|
||||
.dmdata_status_done = hubp2_dmdata_status_done,
|
||||
.hubp_read_state = hubp3_read_state,
|
||||
.hubp_clear_underflow = hubp2_clear_underflow,
|
||||
.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
|
||||
.hubp_init = hubp3_init,
|
||||
};
|
||||
|
||||
bool hubp3_construct(
|
||||
struct dcn20_hubp *hubp2,
|
||||
struct dc_context *ctx,
|
||||
uint32_t inst,
|
||||
const struct dcn_hubp2_registers *hubp_regs,
|
||||
const struct dcn_hubp2_shift *hubp_shift,
|
||||
const struct dcn_hubp2_mask *hubp_mask)
|
||||
{
|
||||
hubp2->base.funcs = &dcn30_hubp_funcs;
|
||||
hubp2->base.ctx = ctx;
|
||||
hubp2->hubp_regs = hubp_regs;
|
||||
hubp2->hubp_shift = hubp_shift;
|
||||
hubp2->hubp_mask = hubp_mask;
|
||||
hubp2->base.inst = inst;
|
||||
hubp2->base.opp_id = OPP_ID_INVALID;
|
||||
hubp2->base.mpcc_id = 0xf;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_HUBP_DCN30_H__
|
||||
#define __DC_HUBP_DCN30_H__
|
||||
|
||||
#include "dcn20/dcn20_hubp.h"
|
||||
#include "dcn21/dcn21_hubp.h"
|
||||
|
||||
#define HUBP_REG_LIST_DCN30(id)\
|
||||
HUBP_REG_LIST_DCN21(id),\
|
||||
SRI(DCN_DMDATA_VM_CNTL, HUBPREQ, id)
|
||||
|
||||
|
||||
#define HUBP_MASK_SH_LIST_DCN30_BASE(mask_sh)\
|
||||
HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh)
|
||||
|
||||
|
||||
#define HUBP_MASK_SH_LIST_DCN30(mask_sh)\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
|
||||
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
|
||||
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
|
||||
HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
|
||||
HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
|
||||
HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
|
||||
HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
|
||||
|
||||
bool hubp3_construct(
|
||||
struct dcn20_hubp *hubp2,
|
||||
struct dc_context *ctx,
|
||||
uint32_t inst,
|
||||
const struct dcn_hubp2_registers *hubp_regs,
|
||||
const struct dcn_hubp2_shift *hubp_shift,
|
||||
const struct dcn_hubp2_mask *hubp_mask);
|
||||
|
||||
bool hubp3_program_surface_flip_and_addr(
|
||||
struct hubp *hubp,
|
||||
const struct dc_plane_address *address,
|
||||
bool flip_immediate);
|
||||
|
||||
void hubp3_program_surface_config(
|
||||
struct hubp *hubp,
|
||||
enum surface_pixel_format format,
|
||||
union dc_tiling_info *tiling_info,
|
||||
struct plane_size *plane_size,
|
||||
enum dc_rotation_angle rotation,
|
||||
struct dc_plane_dcc_param *dcc,
|
||||
bool horizontal_mirror,
|
||||
unsigned int compat_level);
|
||||
|
||||
void hubp3_setup(
|
||||
struct hubp *hubp,
|
||||
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
|
||||
struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
|
||||
|
||||
void hubp3_dcc_control(struct hubp *hubp, bool enable,
|
||||
enum hubp_ind_block_size blk_size);
|
||||
|
||||
void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
|
||||
struct dc_plane_dcc_param *dcc);
|
||||
|
||||
void hubp3_dmdata_set_attributes(
|
||||
struct hubp *hubp,
|
||||
const struct dc_dmdata_attributes *attr);
|
||||
|
||||
void hubp3_read_state(struct hubp *hubp);
|
||||
|
||||
void hubp3_init(struct hubp *hubp);
|
||||
|
||||
#endif /* __DC_HUBP_DCN30_H__ */
|
||||
|
||||
|
||||
|
|
@ -48,6 +48,10 @@ enum cursor_lines_per_chunk {
|
|||
enum hubp_ind_block_size {
|
||||
hubp_ind_block_unconstrained = 0,
|
||||
hubp_ind_block_64b,
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
hubp_ind_block_128b,
|
||||
hubp_ind_block_64b_no_128bcl,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct hubp {
|
||||
|
|
|
|||
Loading…
Reference in New Issue