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clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width 

MUX bits for MMC clock register range are 25:24 where 24 is shift
and 2 is width So fix the width number from 3 to 2.

Fixes: 524353ea48 ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Jagan Teki 2018-11-01 00:06:28 +05:30 committed by Maxime Ripard
parent 859783d139
commit db75489346
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
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@ -411,7 +411,7 @@ static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
@ -419,7 +419,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
@ -427,7 +427,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);