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clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming 

Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.

This reduces the number of ISBs from 3 to 2 when programming
the timer.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-12-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
This commit is contained in:
Marc Zyngier 2021-10-17 13:42:19 +01:00 committed by Jianping Liu
parent c03cea65f4
commit db32538c11
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/include/asm/arch_timer.h
View File

@ -31,6 +31,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val)); asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
isb();
break; break;
case ARCH_TIMER_REG_CVAL: case ARCH_TIMER_REG_CVAL:
asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val)); asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
@ -42,6 +43,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val)); asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
isb();
break; break;
case ARCH_TIMER_REG_CVAL: case ARCH_TIMER_REG_CVAL:
asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val)); asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
@ -52,8 +54,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
} else { } else {
BUILD_BUG(); BUILD_BUG();
} }
isb();
} }
static __always_inline static __always_inline

4
arch/arm64/include/asm/arch_timer.h
View File

@ -95,6 +95,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntp_ctl_el0); write_sysreg(val, cntp_ctl_el0);
isb();
break; break;
case ARCH_TIMER_REG_CVAL: case ARCH_TIMER_REG_CVAL:
write_sysreg(val, cntp_cval_el0); write_sysreg(val, cntp_cval_el0);
@ -106,6 +107,7 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
switch (reg) { switch (reg) {
case ARCH_TIMER_REG_CTRL: case ARCH_TIMER_REG_CTRL:
write_sysreg(val, cntv_ctl_el0); write_sysreg(val, cntv_ctl_el0);
isb();
break; break;
case ARCH_TIMER_REG_CVAL: case ARCH_TIMER_REG_CVAL:
write_sysreg(val, cntv_cval_el0); write_sysreg(val, cntv_cval_el0);
@ -116,8 +118,6 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
} else { } else {
BUILD_BUG(); BUILD_BUG();
} }
isb();
} }
static __always_inline static __always_inline