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drm/amdgpu/swsmu: add smu support for dimgrey_cavefish(v2) 

Reuse sienna_cichlid pp table for dimgrey_cavefish.

v2: update related comment.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2020-10-02 11:51:04 -04:00 committed by Alex Deucher
parent 10e0d9ebb0
commit db1f8a8fb2
3 changed files with 16 additions and 3 deletions
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1
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
View File

@ -33,6 +33,7 @@
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0x1
/* MP Apertures */
#define MP0_Public 0x03800000

1
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -397,6 +397,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
sienna_cichlid_set_ppt_funcs(smu);
break;
case CHIP_RENOIR:

17
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
View File

@ -62,6 +62,7 @@ MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
#define SMU11_VOLTAGE_SCALE 4
@ -109,6 +110,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
case CHIP_DIMGREY_CAVEFISH:
chip_name = "dimgrey_cavefish";
break;
default:
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL;
@ -247,6 +251,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
case CHIP_VANGOGH:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
break;
case CHIP_DIMGREY_CAVEFISH:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break;
default:
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@ -330,7 +337,8 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
adev->asic_type == CHIP_NAVY_FLOUNDER) {
adev->asic_type == CHIP_NAVY_FLOUNDER ||
adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
switch (version_minor) {
case 0:
@ -702,8 +710,11 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
{
struct amdgpu_device *adev = smu->adev;
/* Navy_Flounder do not support to change display num currently */
if (adev->asic_type == CHIP_NAVY_FLOUNDER)
/* Navy_Flounder/Dimgrey_Cavefish do not support to change
* display num currently
*/
if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
return 0;
return smu_cmn_send_smc_msg_with_param(smu,