Renesas ARM64 Based SoC DT Updates for v4.9
Clean up: * Remove unnecessary cap-mmc-highspeed property from SDHI nodes on r8a7795 SoC * Add SoC-specific compatible property to audio-dmac nodes on r8a7795 SoC New Board: * Add r8a7794/h3ulcb board Enablement: * Add PFC and GPIO to r8a7796 SoC * Enable DU and USB 2.0 on r8a7795/salvator-x board * Add VTP, FCPV, FCPF and FDP1 to r8a7795 SoC * Set maximum frequency for SDHI clocks on r8a7795 SoC -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX0RWZAAoJENfPZGlqN0++Ke4P/3e/vy1wOAIgqWTbsc3mlmXw 3gOgJ5EZ+jkNTMiMGFPjmwTr3W+TABFtIDgERrhY/PC15eYLoPFmmTktDWeycLvF Rk+AkXJ8ijXpHB7J5HGT2ZJB3pWsPSoQ5iEJI53BJ084sfDJ38hn1Ew41v442j91 W5FbWsjoKbouPnPsYPDRrOclEUvUoSZPY1ouY9ywfW1zijCvjiwlZ2xRa/df5mnv w8VGqhP1bD10LTfcyVGZ0YcHH8noSazoNrz8ZUct9ECwjwPJOHelj+3fKAkuEzPa R4GTNRhnlVR560Uk7yG9LdoB39JqE/D8rUOaLkzwFBcOuO8g+vTOV6E4wbX/0LWH J5YuMH78+wD6wNj7ON4saiT5SjkGCPkd12bTXrBA14gxCCYQTp/d9r4sGaykRDYO 5NX4IRg/hbilgDMQxXLZkA5s9QRjFXe/4EIol8hF4zHU2RRKaMjMxpWOfLjKBXRQ wLrzitWtaMrrL0SLlUmKQ17TpfursVmaDU0S4F8VtPXfe8EdU52WWuN9u+e1vI9R lYwek8kq89aJqI06/N+gINCCWHKv2mbYJwcOIFIghvHub8ZBHzeoCx1SVN0W143P Cg6zJUgjvM0+OGTK3Q8IcVq/S60e/hN+ASJaHS/HJy+bQbSj/SkqAeyP1WomjQwp kX6RwdwpYxKATWr25xCa =Vd0J -----END PGP SIGNATURE----- Merge tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Pull "Renesas ARM64 Based SoC DT Updates for v4.9" from Simon Horman: Clean up: * Remove unnecessary cap-mmc-highspeed property from SDHI nodes on r8a7795 SoC * Add SoC-specific compatible property to audio-dmac nodes on r8a7795 SoC New Board: * Add r8a7794/h3ulcb board Enablement: * Add PFC and GPIO to r8a7796 SoC * Enable DU and USB 2.0 on r8a7795/salvator-x board * Add VTP, FCPV, FCPF and FDP1 to r8a7795 SoC * Set maximum frequency for SDHI clocks on r8a7795 SoC * tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits) arm64: dts: r8a7796: Add GPIO device nodes arm64: dts: r8a7796: salvator-x: add serial console pins arm64: dts: r8a7796: Add pinctrl device node arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output arm64: dts: h3ulcb: enable GPIO leds arm64: dts: h3ulcb: Sound SSI support arm64: dts: h3ulcb: enable SDHI0 arm64: dts: h3ulcb: enable GPIO keys arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property arm64: dts: h3ulcb: enable USB2.0 Host channel 1 arm64: dts: h3ulcb: enable USB2 PHY of channel 1 arm64: dts: h3ulcb: enable WDT arm64: dts: h3ulcb: enable EXTALR clk arm64: dts: h3ulcb: enable I2C2 arm64: dts: h3ulcb: enable EthernetAVB arm64: dts: h3ulcb: enable SCIF clk and pins arm64: dts: h3ulcb: initial device tree arm64: dts: h3ulcb: add H3ULCB board DT bindings arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes arm64: dts: r8a7795: renesas: salvator-x: Enable DU ...
This commit is contained in:
Arnd Bergmann
commit
da9070b35c
|
|
@ -49,6 +49,8 @@ Boards:
|
|||
compatible = "renesas,genmai", "renesas,r7s72100"
|
||||
- Gose
|
||||
compatible = "renesas,gose", "renesas,r8a7793"
|
||||
- H3ULCB (RTP0RC7795SKB00010S)
|
||||
compatible = "renesas,h3ulcb", "renesas,r8a7795";
|
||||
- Henninger
|
||||
compatible = "renesas,henninger", "renesas,r8a7791"
|
||||
- Koelsch (RTP0RC7791SEB00010S)
|
||||
|
|
|
|||
|
|
@ -17,9 +17,11 @@ Required Properties:
|
|||
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
|
||||
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
|
||||
|
||||
- reg: Base address and length of each memory resource used by the pin
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* Device Tree Source for the H3ULCB board
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a7795.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas H3ULCB board based on r8a7795";
|
||||
compatible = "renesas,h3ulcb", "renesas,r8a7795";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led5 {
|
||||
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
led6 {
|
||||
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
keyboard {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-1 {
|
||||
linux,code = <KEY_1>;
|
||||
label = "SW3";
|
||||
wakeup-source;
|
||||
debounce-interval = <20>;
|
||||
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_a";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
groups = "i2c2_a";
|
||||
function = "i2c2";
|
||||
};
|
||||
|
||||
avb_pins: avb {
|
||||
groups = "avb_mdc";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
sdhi0_pins_3v3: sd0_3v3 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_1v8: sd0_1v8 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound-clk {
|
||||
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
|
||||
"audio_clkout_a", "audio_clkout3_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4613: codec@10 {
|
||||
compatible = "asahi-kasei,ak4613";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x10>;
|
||||
clocks = <&rcar_sound 3>;
|
||||
|
||||
asahi-kasei,in1-single-end;
|
||||
asahi-kasei,in2-single-end;
|
||||
asahi-kasei,out1-single-end;
|
||||
asahi-kasei,out2-single-end;
|
||||
asahi-kasei,out3-single-end;
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <11289600>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&cs2000>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins_3v3>;
|
||||
pinctrl-1 = <&sdhi0_pins_1v8>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <900>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txc-skew-ps = <900>;
|
||||
txen-skew-ps = <0>;
|
||||
txd0-skew-ps = <0>;
|
||||
txd1-skew-ps = <0>;
|
||||
txd2-skew-ps = <0>;
|
||||
txd3-skew-ps = <0>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -110,6 +110,17 @@
|
|||
1800000 0>;
|
||||
};
|
||||
|
||||
vbus0_usb2: regulator-vbus0-usb2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB20_VBUS0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
audio_clkout: audio_clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
|
|
@ -135,6 +146,52 @@
|
|||
sound-dai = <&ak4613>;
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
|
|
@ -172,6 +229,11 @@
|
|||
function = "avb";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
|
|
@ -193,6 +255,11 @@
|
|||
function = "audio_clk";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
||||
function = "usb1";
|
||||
|
|
@ -369,6 +436,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&vbus0_usb2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -383,6 +458,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -391,6 +470,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -399,6 +482,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -328,7 +328,8 @@
|
|||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
|
||||
|
|
@ -360,7 +361,8 @@
|
|||
};
|
||||
|
||||
audma1: dma-controller@ec720000 {
|
||||
compatible = "renesas,rcar-dmac";
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xec720000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
|
||||
|
|
@ -1098,6 +1100,7 @@
|
|||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1107,6 +1110,7 @@
|
|||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1116,8 +1120,8 @@
|
|||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1126,8 +1130,8 @@
|
|||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1224,6 +1228,23 @@
|
|||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
compatible = "renesas,pcie-r8a7795";
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
|
|
@ -1273,5 +1294,252 @@
|
|||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vspbc: vsp@fe920000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe920000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 624>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
|
||||
renesas,fcp = <&fcpvb1>;
|
||||
};
|
||||
|
||||
fcpvb1: fcp@fe92f000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfe92f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 606>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
|
||||
reg = <0 0xfe950000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 615>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
fcpf1: fcp@fe951000 {
|
||||
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
|
||||
reg = <0 0xfe951000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 614>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
fcpf2: fcp@fe952000 {
|
||||
compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
|
||||
reg = <0 0xfe952000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 613>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
vspbd: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 626>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
|
||||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
vspi0: vsp@fe9a0000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe9a0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 631>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
|
||||
renesas,fcp = <&fcpvi0>;
|
||||
};
|
||||
|
||||
fcpvi0: fcp@fe9af000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfe9af000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 611>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
vspi1: vsp@fe9b0000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe9b0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 630>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
|
||||
renesas,fcp = <&fcpvi1>;
|
||||
};
|
||||
|
||||
fcpvi1: fcp@fe9bf000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfe9bf000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 610>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
vspi2: vsp@fe9c0000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe9c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 629>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
|
||||
renesas,fcp = <&fcpvi2>;
|
||||
};
|
||||
|
||||
fcpvi2: fcp@fe9cf000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfe9cf000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 609>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
vspd2: vsp@fea30000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea30000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 621>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,fcp = <&fcpvd2>;
|
||||
};
|
||||
|
||||
fcpvd2: fcp@fea37000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfea37000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 601>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
vspd3: vsp@fea38000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea38000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 620>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
||||
renesas,fcp = <&fcpvd3>;
|
||||
};
|
||||
|
||||
fcpvd3: fcp@fea3f000 {
|
||||
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
|
||||
reg = <0 0xfea3f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 600>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe940000 0 0x2400>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 119>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
renesas,fcp = <&fcpf0>;
|
||||
};
|
||||
|
||||
fdp1@fe944000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe944000 0 0x2400>;
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 118>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
renesas,fcp = <&fcpf1>;
|
||||
};
|
||||
|
||||
fdp1@fe948000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe948000 0 0x2400>;
|
||||
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 117>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
renesas,fcp = <&fcpf2>;
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
|
||||
status = "disabled";
|
||||
|
||||
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_hdmi0: endpoint {
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_hdmi1: endpoint {
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -31,11 +31,27 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_a";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -107,6 +107,123 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 16>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 29>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 15>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 16>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 18>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 26>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 906>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055800 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
reg = <0 0xe6055800 0 0x50>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 4>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 905>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7796";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7796-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -54,6 +54,11 @@ config PINCTRL_PFC_R8A7791
|
|||
depends on ARCH_R8A7791
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_R8A7792
|
||||
def_bool y
|
||||
depends on ARCH_R8A7792
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_R8A7793
|
||||
def_bool y
|
||||
depends on ARCH_R8A7793
|
||||
|
|
@ -69,6 +74,11 @@ config PINCTRL_PFC_R8A7795
|
|||
depends on ARCH_R8A7795
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_R8A7796
|
||||
def_bool y
|
||||
depends on ARCH_R8A7796
|
||||
select PINCTRL_SH_PFC
|
||||
|
||||
config PINCTRL_PFC_SH7203
|
||||
def_bool y
|
||||
depends on CPU_SUBTYPE_SH7203
|
||||
|
|
|
|||
|
|
@ -7,9 +7,11 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
|
|||
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
|
||||
|
|
|
|||
|
|
@ -494,6 +494,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
|
|||
.data = &r8a7791_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7792
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7792",
|
||||
.data = &r8a7792_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7793
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7793",
|
||||
|
|
@ -512,6 +518,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
|
|||
.data = &r8a7795_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7796
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7796",
|
||||
.data = &r8a7796_pinmux_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_SH73A0
|
||||
{
|
||||
.compatible = "renesas,pfc-sh73a0",
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* R-Car Gen3 processor support - PFC hardware block.
|
||||
* R8A7795 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation
|
||||
*
|
||||
|
|
@ -13,19 +13,23 @@
|
|||
#include "core.h"
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
|
||||
SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
|
||||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
|
|
@ -1871,6 +1875,86 @@ static const unsigned int drif3_data1_b_mux[] = {
|
|||
RIF3_D1_B_MARK,
|
||||
};
|
||||
|
||||
/* - DU --------------------------------------------------------------------- */
|
||||
static const unsigned int du_rgb666_pins[] = {
|
||||
/* R[7:2], G[7:2], B[7:2] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int du_rgb666_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK,
|
||||
};
|
||||
static const unsigned int du_rgb888_pins[] = {
|
||||
/* R[7:0], G[7:0], B[7:0] */
|
||||
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
|
||||
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
|
||||
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
|
||||
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
|
||||
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
|
||||
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int du_rgb888_mux[] = {
|
||||
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
|
||||
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
|
||||
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
|
||||
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
|
||||
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
|
||||
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
|
||||
};
|
||||
static const unsigned int du_clk_out_0_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(1, 27),
|
||||
};
|
||||
static const unsigned int du_clk_out_0_mux[] = {
|
||||
DU_DOTCLKOUT0_MARK
|
||||
};
|
||||
static const unsigned int du_clk_out_1_pins[] = {
|
||||
/* CLKOUT */
|
||||
RCAR_GP_PIN(2, 3),
|
||||
};
|
||||
static const unsigned int du_clk_out_1_mux[] = {
|
||||
DU_DOTCLKOUT1_MARK
|
||||
};
|
||||
static const unsigned int du_sync_pins[] = {
|
||||
/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
|
||||
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
|
||||
};
|
||||
static const unsigned int du_sync_mux[] = {
|
||||
DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
|
||||
};
|
||||
static const unsigned int du_oddf_pins[] = {
|
||||
/* EXDISP/EXODDF/EXCDE */
|
||||
RCAR_GP_PIN(2, 2),
|
||||
};
|
||||
static const unsigned int du_oddf_mux[] = {
|
||||
DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_cde_pins[] = {
|
||||
/* CDE */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int du_cde_mux[] = {
|
||||
DU_CDE_MARK,
|
||||
};
|
||||
static const unsigned int du_disp_pins[] = {
|
||||
/* DISP */
|
||||
RCAR_GP_PIN(2, 1),
|
||||
};
|
||||
static const unsigned int du_disp_mux[] = {
|
||||
DU_DISP_MARK,
|
||||
};
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int hscif0_data_pins[] = {
|
||||
/* RX, TX */
|
||||
|
|
@ -3593,6 +3677,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(du_rgb666),
|
||||
SH_PFC_PIN_GROUP(du_rgb888),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_0),
|
||||
SH_PFC_PIN_GROUP(du_clk_out_1),
|
||||
SH_PFC_PIN_GROUP(du_sync),
|
||||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
|
|
@ -3918,6 +4010,17 @@ static const char * const drif3_groups[] = {
|
|||
"drif3_data1_b",
|
||||
};
|
||||
|
||||
static const char * const du_groups[] = {
|
||||
"du_rgb666",
|
||||
"du_rgb888",
|
||||
"du_clk_out_0",
|
||||
"du_clk_out_1",
|
||||
"du_sync",
|
||||
"du_oddf",
|
||||
"du_cde",
|
||||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
"hscif0_data",
|
||||
"hscif0_clk",
|
||||
|
|
@ -4265,6 +4368,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
|
|
@ -5073,8 +5177,234 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
|||
return bit;
|
||||
}
|
||||
|
||||
#define PUEN 0xe6060400
|
||||
#define PUD 0xe6060440
|
||||
|
||||
#define PU0 0x00
|
||||
#define PU1 0x04
|
||||
#define PU2 0x08
|
||||
#define PU3 0x0c
|
||||
#define PU4 0x10
|
||||
#define PU5 0x14
|
||||
#define PU6 0x18
|
||||
|
||||
static const struct {
|
||||
u16 reg : 11;
|
||||
u16 bit : 5;
|
||||
} pullups[] = {
|
||||
[RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
|
||||
[RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
|
||||
[RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
|
||||
|
||||
[RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
|
||||
[RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
|
||||
[RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
|
||||
[RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
|
||||
[RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
|
||||
[RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
|
||||
[RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
|
||||
[RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
|
||||
[RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
|
||||
[RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
|
||||
[RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
|
||||
[RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
|
||||
[RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
|
||||
[RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
|
||||
[RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
|
||||
[RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
|
||||
[RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
|
||||
[RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
|
||||
[RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
|
||||
[RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
|
||||
[RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
|
||||
[RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
|
||||
[RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
|
||||
[RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
|
||||
[RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
|
||||
[RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
|
||||
[RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
|
||||
[RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
|
||||
[RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
|
||||
[RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
|
||||
[RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
|
||||
[RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
|
||||
|
||||
[RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
|
||||
[RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
|
||||
[RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
|
||||
[RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
|
||||
[RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
|
||||
[RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
|
||||
[RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
|
||||
[RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
|
||||
[RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
|
||||
[RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
|
||||
[RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
|
||||
[RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
|
||||
[RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
|
||||
[RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
|
||||
[RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
|
||||
[RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
|
||||
[RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
|
||||
[RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
|
||||
[RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
|
||||
[RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
|
||||
[RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
|
||||
[RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
|
||||
[RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
|
||||
[RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
|
||||
[RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
|
||||
[RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
|
||||
[RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
|
||||
[RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
|
||||
|
||||
[RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
|
||||
[RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
|
||||
[RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
|
||||
[RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
|
||||
[RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
|
||||
[RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
|
||||
[RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
|
||||
[RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
|
||||
[RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
|
||||
[RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
|
||||
[RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
|
||||
[RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
|
||||
[RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
|
||||
[RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
|
||||
[RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
|
||||
[RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
|
||||
[RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
|
||||
[RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
|
||||
[RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
|
||||
[RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
|
||||
[RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
|
||||
[RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
|
||||
|
||||
[RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
|
||||
[RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
|
||||
[RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
|
||||
[RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
|
||||
[RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
|
||||
[RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
|
||||
[RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
|
||||
[RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
|
||||
[RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
|
||||
[RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
|
||||
[RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
|
||||
[RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
|
||||
[RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
|
||||
[RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
|
||||
[RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
|
||||
[RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
|
||||
[RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
|
||||
[RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
|
||||
[RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
|
||||
[RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
|
||||
[RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
|
||||
[RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
|
||||
[RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
|
||||
[RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
|
||||
[RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
|
||||
[RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
|
||||
[RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
|
||||
[RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
|
||||
[RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
|
||||
[RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
|
||||
[RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
|
||||
[RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
|
||||
|
||||
[RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
|
||||
[RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
|
||||
[RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
|
||||
[RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
|
||||
[RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
|
||||
[RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
|
||||
[RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
|
||||
[RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
|
||||
[RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
|
||||
[RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
|
||||
[RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
|
||||
[RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
|
||||
[RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
|
||||
[RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
|
||||
[RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
|
||||
[RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
|
||||
[RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
|
||||
[RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
|
||||
[RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
|
||||
[RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
|
||||
[RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
|
||||
[RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
|
||||
[RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
|
||||
[RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
|
||||
[RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
|
||||
[RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
|
||||
[RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
|
||||
[RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
|
||||
[RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
|
||||
[RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
|
||||
[RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
|
||||
|
||||
[RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
|
||||
[RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
|
||||
[RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
|
||||
[RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
|
||||
[RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
|
||||
[RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
|
||||
[RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
|
||||
};
|
||||
|
||||
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
|
||||
if (WARN_ON_ONCE(!pullups[pin].reg))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
reg = pullups[pin].reg;
|
||||
bit = BIT(pullups[pin].bit);
|
||||
|
||||
if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
|
||||
if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
} else
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
}
|
||||
|
||||
static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
u32 enable, updown;
|
||||
u32 reg;
|
||||
u32 bit;
|
||||
|
||||
if (WARN_ON_ONCE(!pullups[pin].reg))
|
||||
return;
|
||||
|
||||
reg = pullups[pin].reg;
|
||||
bit = BIT(pullups[pin].bit);
|
||||
|
||||
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE)
|
||||
enable |= bit;
|
||||
|
||||
updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= bit;
|
||||
|
||||
sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
|
||||
sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
|
||||
.get_bias = r8a7795_pinmux_get_bias,
|
||||
.set_bias = r8a7795_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -257,9 +257,11 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
|
|||
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
|
||||
|
|
@ -354,72 +356,99 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
|||
* GP port style (32 ports banks)
|
||||
*/
|
||||
|
||||
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
||||
#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
|
||||
fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
|
||||
#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
|
||||
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
|
||||
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
||||
#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
|
||||
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_8(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
||||
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
|
||||
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
||||
#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
|
||||
#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_14(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_15(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
|
||||
#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_16(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
|
||||
#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_17(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
|
||||
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
|
||||
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_23(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
|
||||
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_26(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
|
||||
#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_28(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
|
||||
#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_29(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
|
||||
#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
||||
#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_30(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
|
||||
#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_32_REV(bank, fn, sfx) \
|
||||
|
|
|
|||
Loading…
Reference in New Issue